library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;


library work;
use work.mat_ply.all;


package mat_ply is

type t11 is array (0 to 2) of unsigned(15 downto 0);
type t1 is array (0 to 3) of t11; --4*3 matrix
type t22 is array (0 to 4) of unsigned(15 downto 0);
type t2 is array (0 to 2) of t22; --3*5 matrix
type t33 is array (0 to 4) of unsigned(31 downto 0);
type t3 is array (0 to 3) of t33; --4*5 matrix as output

function matmul ( a : t1; b:t2 ) return t3;

end mat_ply;

package body mat_ply is

function matmul ( a : t1; b:t2 ) return t3 is
variable i,j,k : integer:=0;
variable prod : t3:=(others => (others => (others => '0')));

begin
for i in 0 to 3 loop --(number of rows in the first matrix - 1)
for j in 0 to 4 loop --(number of columns in the second matrix - 1)
for k in 0 to 2 loop --(number of rows in the second matrix - 1)

prod(i)(j) := prod(i)(j) + (a(i)(k) * b(k)(j));

end loop;
end loop;
end loop;
return prod;
end matmul;

end mat_ply;

entity test_mat is
port (clk : in std_logic;
a : in t1;
b : in t2;
prod : out t3
);
end test_mat;

architecture Behavioral of test_mat is
begin
process(clk)
begin
if(clk'event and clk='1') then
prod<=matmul(a,b); --function is called here.
end if;
end process;
end Behavioral;





ENTITY mat_tb IS
END mat_tb;

ARCHITECTURE behavior OF mat_tb IS
--signals declared and initialized to zero.
signal clk : std_logic := '0';
signal a : t1:=(others => (others => (others => '0')));
signal b : t2:=(others => (others => (others => '0')));
signal x: unsigned(15 downto 0):=(others => '0'); --temporary variable
signal prod : t3:=(others => (others => (others => '0')));
-- Clock period definitions
constant clk_period : time := 1 ns;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: entity work.test_mat PORT MAP (clk,a,b,prod);

-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
--first set of inputs..
a <= ((x,x+1,x+4),(x+2,x,x+1),(x+1,x+5,x),(x+1,x+1,x));
b <= ((x,x+1,x+4,x+2,x+7),(x,x+1,x+3,x+2,x+4),(x,x+2,x+3,x+4,x+5));
wait for 2 ns;
--second set of inputs can be given here and so on.
end process;

END;