Started : "Synthesize - XST". Running xst... Command Line: xst -intstyle ise -ifn "D:/ISE_Projects/HexiBin_v0.1/Main.xst" -ofn "D:/ISE_Projects/HexiBin_v0.1/Main.syr" Reading design: Main.prj ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "D:/ISE_Projects/HexiBin_v0.1/Bin2ASCII.vhd" in Library work. Architecture bin2ascii of Entity bin2ascii is up to date. Compiling vhdl file "D:/ISE_Projects/HexiBin_v0.1/bin2bcd.vhd" in Library work. Architecture bin2bcd of Entity bin2bcd is up to date. Compiling vhdl file "D:/ISE_Projects/HexiBin_v0.1/Speed.vhd" in Library work. Architecture behavioral of Entity speed is up to date. Compiling vhdl file "D:/ISE_Projects/HexiBin_v0.1/BCD2ASCII_MUX.vhd" in Library work. Architecture behavioral of Entity bcd2ascii_mux is up to date. Compiling vhdl file "D:/ISE_Projects/HexiBin_v0.1/Main.vhd" in Library work. Entity
compiled. Entity
(Architecture ) compiled. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity
in library (architecture ). Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity
in library (Architecture ). INFO:Xst:2679 - Register in unit
has a constant value of 0 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register in unit
has a constant value of 0 during circuit operation. The register is replaced by logic. Entity
analyzed. Unit
generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). INFO:Xst:1561 - "D:/ISE_Projects/HexiBin_v0.1/BCD2ASCII_MUX.vhd" line 61: Mux is complete : default of case is discarded Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... INFO:Xst:2679 - Register in unit
has a constant value of 000000000000 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register in unit
has a constant value of 0000 during circuit operation. The register is replaced by logic. INFO:Xst:2679 - Register in unit
has a constant value of 000000000000 during circuit operation. The register is replaced by logic. Synthesizing Unit . Related source file is "D:/ISE_Projects/HexiBin_v0.1/Speed.vhd". Found finite state machine for signal . ----------------------------------------------------------------------- | States | 18 | | Transitions | 45 | | Inputs | 4 | | Outputs | 1 | | Clock | CLK (rising_edge) | | Reset | RESET (negative) | | Reset type | asynchronous | | Reset State | init | | Power Up State | error | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found 17-bit register for signal . Found 7-bit up counter for signal . Found 2-bit register for signal . Found 17-bit up counter for signal . Summary: inferred 1 Finite State Machine(s). inferred 2 Counter(s). inferred 19 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is "D:/ISE_Projects/HexiBin_v0.1/BCD2ASCII_MUX.vhd". Found 16x8-bit ROM for signal . Summary: inferred 1 ROM(s). Unit synthesized. Synthesizing Unit
. Related source file is "D:/ISE_Projects/HexiBin_v0.1/Main.vhd". INFO:Xst:1799 - State 011 is never reached in FSM . INFO:Xst:1799 - State showhex is never reached in FSM . INFO:Xst:1799 - State go is never reached in FSM . INFO:Xst:1799 - State user1win is never reached in FSM . INFO:Xst:1799 - State user2win is never reached in FSM . INFO:Xst:1799 - State showbin is never reached in FSM . INFO:Xst:1799 - State tooearly is never reached in FSM . INFO:Xst:1799 - State newhighscore is never reached in FSM . Found finite state machine for signal . ----------------------------------------------------------------------- | States | 3 | | Transitions | 6 | | Inputs | 2 | | Outputs | 2 | | Clock | CLK (rising_edge) | | Reset | RESET (negative) | | Reset type | asynchronous | | Reset State | 000 | | Power Up State | 000 | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Found finite state machine for signal . ----------------------------------------------------------------------- | States | 1 | | Transitions | 1 | | Inputs | 3 | | Outputs | 0 | | Clock | CLK (rising_edge) | | Reset | RESET (negative) | | Reset type | asynchronous | | Reset State | init | | Power Up State | init | | Encoding | automatic | | Implementation | LUT | ----------------------------------------------------------------------- Using one-hot encoding for signal . Found 16x8-bit ROM for signal created at line 22. Found 16x8-bit ROM for signal created at line 22. Found 8-bit 32-to-1 multiplexer for signal . Found 8-bit register for signal . Found 16-bit register for signal . Found 5-bit register for signal . Found 5-bit adder for signal created at line 651. Found 5-bit comparator less for signal created at line 650. Found 7-bit up counter for signal . Found 16-bit up counter for signal . Found 8-bit comparator equal for signal created at line 254. Found 8-bit register for signal . Found 8-bit register for signal . Found 8-bit register for signal . Found 2-bit register for signal . Found 1-bit register for signal . Found 1-bit xor2 for signal . Found 1-bit xor2 for signal . Found 1-bit xor2 for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 2 Finite State Machine(s). inferred 2 ROM(s). inferred 2 Counter(s). inferred 63 D-type flip-flop(s). inferred 1 Adder/Subtractor(s). inferred 2 Comparator(s). inferred 8 Multiplexer(s). Unit
synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # ROMs : 6 16x8-bit ROM : 6 # Adders/Subtractors : 1 5-bit adder : 1 # Counters : 2 17-bit up counter : 1 7-bit up counter : 1 # Registers : 10 1-bit register : 1 16-bit register : 1 17-bit register : 1 2-bit register : 2 5-bit register : 1 8-bit register : 4 # Comparators : 1 5-bit comparator less : 1 # Multiplexers : 1 8-bit 32-to-1 multiplexer : 1 # Xors : 3 1-bit xor2 : 3 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Analyzing FSM for best encoding. Optimizing FSM on signal with gray encoding. ------------------- State | Encoding ------------------- 000 | 00 001 | 01 010 | 11 011 | unreached ------------------- Analyzing FSM for best encoding. Optimizing FSM on signal with user encoding. ------------------- State | Encoding ------------------- error | 00000 init | 00001 v1 | 00010 v10 | 00011 v2 | 00100 v20 | 00101 v3 | 00110 v30 | 00111 v4 | 01000 v40 | 01001 r1 | 01010 r10 | 01011 r2 | 01100 r20 | 01101 r3 | 01110 r30 | 01111 r4 | 10000 r40 | 10001 ------------------- WARNING:Xst:1899 - Due to constant pushing, all outputs of the instance of the block are unconnected in block
. This instance will be removed from the design along with all underlying logic WARNING:Xst:1899 - Due to constant pushing, all outputs of the instance of the block are unconnected in block
. This instance will be removed from the design along with all underlying logic WARNING:Xst:1899 - Due to constant pushing, all outputs of the instance of the block are unconnected in block
. This instance will be removed from the design along with all underlying logic WARNING:Xst:1899 - Due to constant pushing, all outputs of the instance of the block are unconnected in block
. This instance will be removed from the design along with all underlying logic WARNING:Xst:1899 - Due to constant pushing, all outputs of the instance of the block are unconnected in block
. This instance will be removed from the design along with all underlying logic WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block
. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block
. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block
. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block
. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block
. This FF/Latch will be trimmed during the optimization process. ========================================================================= Advanced HDL Synthesis Report Macro Statistics # FSMs : 2 # Registers : 14 Flip-Flops : 14 # Comparators : 1 5-bit comparator less : 1 # Xors : 3 1-bit xor2 : 3 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:1293 - FF/Latch has a constant value of 0 in block
. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block
. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block
. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block
. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block
. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block
. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block
. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block
. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block
. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block
. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block
. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block
. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block
. This FF/Latch will be trimmed during the optimization process. WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch has a constant value of 0 in block
. This FF/Latch will be trimmed during the optimization process. Optimizing unit
... Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block Main, actual ratio is 0. Final Macro Processing ... ========================================================================= Final Register Report Macro Statistics # Registers : 2 Flip-Flops : 2 ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ CLK | BUFGP | 2 | -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- -----------------------------------------------------------+------------------------+-------+ Control Signal | Buffer(FF name) | Load | -----------------------------------------------------------+------------------------+-------+ COMMAND_FSM_Acst_FSM_inv(COMMAND_FSM_Acst_FSM_inv1_INV_0:O)| NONE(COMMAND_FSM_FFd1) | 2 | -----------------------------------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 2.102ns (Maximum Frequency: 475.737MHz) Minimum input arrival time before clock: 2.852ns Maximum output required time after clock: 4.283ns Maximum combinational path delay: 4.937ns ========================================================================= Process "Synthesize - XST" completed successfully