############# SWITCH für CBI-Instruktionen ##################

#include <avr/io.h>
#include <avr/interrupt.h>

ISR (TIMER0_COMPA_vect)
{
  static uint8_t col = 0;

  switch (col) {
    case  0: PORTD &= ~(1 << 4) ; break;
    case  1: PORTD &= ~(1 << 5) ; break;
    case  2: PORTD &= ~(1 << 6) ; break;
    case  3: PORTD &= ~(1 << 7) ; break;
    case  4: PORTB &= ~(1 << 2) ; break;
    case  5: PORTB &= ~(1 << 3) ; break;
    case  6: PORTB &= ~(1 << 4) ; break;
    case  7: PORTB &= ~(1 << 5) ; break;
    case  8: PORTB &= ~(1 << 6) ; break;
    case  9: PORTB &= ~(1 << 7) ; break;
    case 10: PORTA &= ~(1 << 0) ; break;
    case 11: PORTA &= ~(1 << 1) ; break;
    case 12: PORTA &= ~(1 << 2) ; break;
    case 13: PORTA &= ~(1 << 3) ; break;
    case 14: PORTA &= ~(1 << 4) ; break;
    case 15: PORTA &= ~(1 << 5) ; break;
    case 16: PORTA &= ~(1 << 6) ; break;
    case 17: PORTA &= ~(1 << 7) ; break;
  }

  col += 1;
  if (col == 18)
    col = 0;
}

------------------------------------------------------------

	.file	"switch-cbi.c"
__SREG__ = 0x3f
__SP_H__ = 0x3e
__SP_L__ = 0x3d
__CCP__  = 0x34
__tmp_reg__ = 0
__zero_reg__ = 1
	.global __do_copy_data
	.global __do_clear_bss
	.section	.text.__vector_16,"ax",@progbits
.global	__vector_16
	.type	__vector_16, @function
__vector_16:
	push __zero_reg__
	push r0
	in r0,__SREG__
	push r0
	clr __zero_reg__
	push r24
	push r30
	push r31
/* prologue: Signal */
/* frame size = 0 */
	lds r24,col.1095
	mov r30,r24
	ldi r31,lo8(0)
	cpi r30,18
	cpc r31,__zero_reg__
	brlo .L27                       // jump to switch
	subi r24,lo8(-(1))
	sts col.1095,r24
	cpi r24,lo8(18)
	brne .L25
.L23:
	sts col.1095,__zero_reg__
.L25:
/* epilogue start */
	pop r31
	pop r30
	pop r24
	pop r0
	out __SREG__,r0
	pop r0
	pop __zero_reg__
	reti
.L27:
	subi r30,lo8(-(gs(.L21)))     // 1
	sbci r31,hi8(-(gs(.L21)))     // 1
	lsl r30                       // 1
	rol r31                       // 1
	lpm __tmp_reg__,Z+            // 3
	lpm r31,Z                     // 3
	mov r30,__tmp_reg__           // 1
	ijmp                          // 2     (springt z.B. zu .L12)
	.data
	.section .progmem.gcc_sw_table, "a", @progbits
	.p2align 1
.L21:
	.data
	.section .progmem.gcc_sw_table, "a", @progbits
	.p2align 1
	.word gs(.L3)
	.word gs(.L4)
	.word gs(.L5)
	.word gs(.L6)
	.word gs(.L7)
	.word gs(.L8)
	.word gs(.L9)
	.word gs(.L10)
	.word gs(.L11)
	.word gs(.L12)
	.word gs(.L13)
	.word gs(.L14)
	.word gs(.L15)
	.word gs(.L16)
	.word gs(.L17)
	.word gs(.L18)
	.word gs(.L19)
	.word gs(.L20)
	.section	.text.__vector_16
.L20:
	cbi 34-32,7
	rjmp .L23
.L3:
	cbi 43-32,4
.L22:
	subi r24,lo8(-(1))
	sts col.1095,r24
	pop r31
	pop r30
	pop r24
	pop r0
	out __SREG__,r0
	pop r0
	pop __zero_reg__
	reti
.L4:
	cbi 43-32,5
	rjmp .L22
.L5:
	cbi 43-32,6
	rjmp .L22
.L6:
	cbi 43-32,7
	rjmp .L22
.L7:
	cbi 37-32,2
	rjmp .L22
.L8:
	cbi 37-32,3
	rjmp .L22
.L9:
	cbi 37-32,4
	rjmp .L22
.L10:
	cbi 37-32,5
	rjmp .L22
.L11:
	cbi 37-32,6
	rjmp .L22
.L12:
	cbi 37-32,7       // 2
	rjmp .L22         // 2
.L13:
	cbi 34-32,0
	rjmp .L22
.L14:
	cbi 34-32,1
	rjmp .L22
.L15:
	cbi 34-32,2
	rjmp .L22
.L16:
	cbi 34-32,3
	rjmp .L22
.L17:
	cbi 34-32,4
	rjmp .L22
.L18:
	cbi 34-32,5
	rjmp .L22
.L19:
	cbi 34-32,6
	rjmp .L22
	.size	__vector_16, .-__vector_16
	.lcomm col.1095,1


====================== 17 Zyklen =================================



############# SWITCH mit Tabelle ##################

#include <avr/io.h>
#include <avr/interrupt.h>

const uint8_t dataporta[] = { 0xFE, 0xFD, 0xFB, 0xF7, 0xEF, 0xDF, 0xBF, 0x7F};
const uint8_t dataportb[] = { 0xFB, 0xF7, 0xEF, 0xDF, 0xBF, 0x7F};
const uint8_t dataportd[] = { 0xEF, 0xDF, 0xBF, 0x7F};

ISR (TIMER0_COMPA_vect)
{
  static uint8_t col = 0;

  switch (col) {
     case 0:
     case 1:
     case 2:
     case 3:
       PORTD &= dataportd[col];
       break;
     case 4:
     case 5:
     case 6:
     case 7:
     case 8:
     case 9:
       col = col - 4;
       PORTB &= dataportb[col];
       break;
     case 10:
     case 11:
     case 12:
     case 13:
     case 14:
     case 15:
     case 16:
     case 17:
       col = col - 10;
       PORTA &= dataporta[col];
       break;
  }

  col += 1;
  if (col == 18)
    col = 0;
}

------------------------------------------------------------

	.file	"switch-table.c"
__SREG__ = 0x3f
__SP_H__ = 0x3e
__SP_L__ = 0x3d
__CCP__  = 0x34
__tmp_reg__ = 0
__zero_reg__ = 1
	.global __do_copy_data
	.global __do_clear_bss
	.section	.text.__vector_16,"ax",@progbits
.global	__vector_16
	.type	__vector_16, @function
__vector_16:
	push __zero_reg__
	push r0
	in r0,__SREG__
	push r0
	clr __zero_reg__
	push r18
	push r24
	push r25
	push r30
	push r31
/* prologue: Signal */
/* frame size = 0 */
	lds r18,col.1098
	cpi r18,lo8(10)               // 1
	brsh .L6                      // 2    --> Sprung zu .L6
	cpi r18,lo8(4)
	brlo .L12
	subi r18,lo8(-(-4))
	sts col.1098,r18
	in r25,37-32
	mov r30,r18
	ldi r31,lo8(0)
	subi r30,lo8(-(dataportb))
	sbci r31,hi8(-(dataportb))
	ld r24,Z
	and r25,r24
	out 37-32,r25
.L2:
	mov r24,r18
	subi r24,lo8(-(1))
	sts col.1098,r24
	cpi r24,lo8(18)
	brne .L8
	sts col.1098,__zero_reg__
.L8:
/* epilogue start */
	pop r31
	pop r30
	pop r25
	pop r24
	pop r18
	pop r0
	out __SREG__,r0
	pop r0
	pop __zero_reg__
	reti
.L6:
	cpi r18,lo8(18)                  // 1
	brsh .L2                         // 1   kein Sprung
	subi r18,lo8(-(-10))             // 1
	sts col.1098,r18                 // 2
	in r25,34-32                     // 1
	mov r30,r18                      // 1
	ldi r31,lo8(0)                   // 1
	subi r30,lo8(-(dataporta))       // 1
	sbci r31,hi8(-(dataporta))       // 1
	ld r24,Z                         // 1
	and r25,r24                      // 1
	out 34-32,r25                    // 1
	rjmp .L2                         // 2
.L12:
	in r24,43-32
	mov r30,r18
	ldi r31,lo8(0)
	subi r30,lo8(-(dataportd))
	sbci r31,hi8(-(dataportd))
	ld r25,Z
	and r24,r25
	out 43-32,r24
	rjmp .L2
	.size	__vector_16, .-__vector_16
.global	dataporta
	.data
	.type	dataporta, @object
	.size	dataporta, 8
dataporta:
	.byte	-2
	.byte	-3
	.byte	-5
	.byte	-9
	.byte	-17
	.byte	-33
	.byte	-65
	.byte	127
.global	dataportb
	.type	dataportb, @object
	.size	dataportb, 6
dataportb:
	.byte	-5
	.byte	-9
	.byte	-17
	.byte	-33
	.byte	-65
	.byte	127
.global	dataportd
	.type	dataportd, @object
	.size	dataportd, 4
dataportd:
	.byte	-17
	.byte	-33
	.byte	-65
	.byte	127
	.lcomm col.1098,1

====================== 18 Zyklen =================================


############# KEINE SPRÜNGE 1 ##################

#include <avr/io.h>
#include <avr/interrupt.h>

const uint8_t dataporta[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
const uint8_t dataportb[] = { 0x00, 0x00, 0x00, 0x00, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
const uint8_t dataportd[] = { 0x10, 0x20, 0x40, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };

ISR (TIMER0_COMPA_vect)
{
  static uint8_t col = 0;

  PORTD &= ~dataportd[col];
  PORTB &= ~dataportb[col];
  PORTA &= ~dataporta[col];

  col += 1;
  if (col == 18)
    col = 0;
}

------------------------------------------------------------


	.file	"no-jump.c"
__SREG__ = 0x3f
__SP_H__ = 0x3e
__SP_L__ = 0x3d
__CCP__  = 0x34
__tmp_reg__ = 0
__zero_reg__ = 1
	.global __do_copy_data
	.global __do_clear_bss
	.section	.text.__vector_16,"ax",@progbits
.global	__vector_16
	.type	__vector_16, @function
__vector_16:
	push __zero_reg__
	push r0
	in r0,__SREG__
	push r0
	clr __zero_reg__
	push r18
	push r24
	push r25
	push r26
	push r27
	push r30
	push r31
/* prologue: Signal */
/* frame size = 0 */
	in r18,43-32                      // 1
	lds r25,col.1098                  //     (nicht gezählt, gehe von col in Register aus)
	mov r26,r25                       // 1
	ldi r27,lo8(0)                    // 1
	movw r30,r26                      // 1
	subi r30,lo8(-(dataportd))        // 1
	sbci r31,hi8(-(dataportd))        // 1
	ld r24,Z                          // 1
	com r24                           // 1
	and r24,r18                       // 1
	out 43-32,r24                     // 1
	in r18,37-32                      // 1
	movw r30,r26                      // 1
	subi r30,lo8(-(dataportb))        // 1
	sbci r31,hi8(-(dataportb))        // 1
	ld r24,Z                          // 1
	com r24                           // 1
	and r24,r18                       // 1
	out 37-32,r24                     // 1
	in r18,34-32                      // 1
	subi r26,lo8(-(dataporta))        // 1
	sbci r27,hi8(-(dataporta))        // 1
	ld r24,X                          // 1
	com r24                           // 1
	and r24,r18                       // 1
	out 34-32,r24                     // 1
	subi r25,lo8(-(1))
	sts col.1098,r25
	cpi r25,lo8(18)
	brne .L3
	sts col.1098,__zero_reg__
.L3:
/* epilogue start */
	pop r31
	pop r30
	pop r27
	pop r26
	pop r25
	pop r24
	pop r18
	pop r0
	out __SREG__,r0
	pop r0
	pop __zero_reg__
	reti
	.size	__vector_16, .-__vector_16
.global	dataporta
	.data
	.type	dataporta, @object
	.size	dataporta, 18
dataporta:
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	1
	.byte	2
	.byte	4
	.byte	8
	.byte	16
	.byte	32
	.byte	64
	.byte	-128
.global	dataportb
	.type	dataportb, @object
	.size	dataportb, 18
dataportb:
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	4
	.byte	8
	.byte	16
	.byte	32
	.byte	64
	.byte	-128
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	0
.global	dataportd
	.type	dataportd, @object
	.size	dataportd, 18
dataportd:
	.byte	16
	.byte	32
	.byte	64
	.byte	-128
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.byte	0
	.lcomm col.1098,1

====================== 25 Zyklen =================================

############# KEINE SPRÜNGE 2 ##################


#include <avr/io.h>
#include <avr/interrupt.h>

const uint8_t dataports[] = { 0xef, 0xff, 0xff, 0xdf, 0xff, 0xff, 0xbf, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xf7, 0xff,
                              0xff, 0xef, 0xff, 0xff, 0xdf, 0xff, 0xff, 0xbf, 0xff, 0xff, 0x7f, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xfd,
                              0xff, 0xff, 0xfb, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xef, 0xff, 0xff, 0xdf, 0xff, 0xff, 0xbf, 0xff, 0xff, 0x7f, };

ISR (TIMER0_COMPA_vect)
{
  static uint8_t col = 0;

  PORTD &= dataports[3*col];
  PORTB &= dataports[3*col+1];
  PORTA  = dataports[3*col+2];

  col += 1;
  if (col == 18)
    col = 0;
}

------------------------------------------------------------

	.file	"no-jump2.c"
__SREG__ = 0x3f
__SP_H__ = 0x3e
__SP_L__ = 0x3d
__CCP__  = 0x34
__tmp_reg__ = 0
__zero_reg__ = 1
	.global __do_copy_data
	.global __do_clear_bss
	.section	.text.__vector_16,"ax",@progbits
.global	__vector_16
	.type	__vector_16, @function
__vector_16:
	push __zero_reg__
	push r0
	in r0,__SREG__
	push r0
	clr __zero_reg__
	push r18
	push r24
	push r25
	push r30
	push r31
/* prologue: Signal */
/* frame size = 0 */
	in r25,43-32                     // 1
	lds r18,col.1096                 //    (nicht gezählt, gehe von col in register aus)
	ldi r30,lo8(3)                   // 1
	mul r18,r30                      // 2
	movw r30,r0                      // 1
	clr r1                           // 1
	subi r30,lo8(-(dataports))       // 1
	sbci r31,hi8(-(dataports))       // 1
	ld r24,Z                         // 1
	and r25,r24                      // 1
	out 43-32,r25                    // 1
	in r24,37-32                     // 1
	ldd r25,Z+1                      // 2
	and r24,r25                      // 1
	out 37-32,r24                    // 1
	ldd r24,Z+2                      // 2
	out 34-32,r24                    // 1
	subi r18,lo8(-(1))
	sts col.1096,r18
	cpi r18,lo8(18)
	brne .L3
	sts col.1096,__zero_reg__
.L3:
/* epilogue start */
	pop r31
	pop r30
	pop r25
	pop r24
	pop r18
	pop r0
	out __SREG__,r0
	pop r0
	pop __zero_reg__
	reti
	.size	__vector_16, .-__vector_16
.global	dataports
	.data
	.type	dataports, @object
	.size	dataports, 54
dataports:
	.byte	-17
	.byte	-1
	.byte	-1
	.byte	-33
	.byte	-1
	.byte	-1
	.byte	-65
	.byte	-1
	.byte	-1
	.byte	127
	.byte	-1
	.byte	-1
	.byte	-1
	.byte	-5
	.byte	-1
	.byte	-1
	.byte	-9
	.byte	-1
	.byte	-1
	.byte	-17
	.byte	-1
	.byte	-1
	.byte	-33
	.byte	-1
	.byte	-1
	.byte	-65
	.byte	-1
	.byte	-1
	.byte	127
	.byte	-1
	.byte	-1
	.byte	-1
	.byte	-2
	.byte	-1
	.byte	-1
	.byte	-3
	.byte	-1
	.byte	-1
	.byte	-5
	.byte	-1
	.byte	-1
	.byte	-9
	.byte	-1
	.byte	-1
	.byte	-17
	.byte	-1
	.byte	-1
	.byte	-33
	.byte	-1
	.byte	-1
	.byte	-65
	.byte	-1
	.byte	-1
	.byte	127
	.lcomm col.1096,1

====================== 19 Zyklen =================================