entity Prob2 is port ( --CLOCK : in std_logic; --RST : out STD_LOGIC; --RST_IC : out STD_LOGIC ; SEG_OUT : out STD_LOGIC_VECTOR(7 downto 0); AN_OUT : out STD_LOGIC_VECTOR (3 downto 0); SW : in UNSIGNED (7 downto 0); --DQ : inout STD_LOGIC); end Prob2; architecture PModTMP of Prob2 is signal freq_clk : integer := 10000; -- counter für 100kHz IC-Takt signal freq_MESS_2 : integer := 400000; signal J : integer; signal I : integer; signal TEMP : integer; signal TEMP_100 : integer; -- UNSIGNED (7 downto 0); signal TEMP_10 : integer; -- UNSIGNED (7 downto 0); signal X : integer; signal CLOCK_IC : std_logic; signal CLOCK_MESS : STD_LOGIC; signal CLOCK_AUSGABE : STD_LOGIC; signal SEG_100 : STD_LOGIC_VECTOR (7 downto 0); signal SEG_10 : STD_LOGIC_VECTOR (7 downto 0); signal SEG_1 : STD_LOGIC_VECTOR (7 downto 0); signal SEG_VORZ : STD_LOGIC_VECTOR (7 downto 0); signal DATA : UNSIGNED (7 downto 0); --signal DATA_UNSIGNED : unsigned (7 downto 0); begin TAKTGEN: process (CLOCK) -- Takt für Kommunikation mit IC begin if (CLOCK'event and CLOCK = '1') then if (CLOCK_MESS = '1') then if J = freq_clk then CLOCK_IC <= not CLOCK_IC; J <= 0; else J <= J + 1; end if; else CLOCK_IC <= '1'; J <= 0; end if; end if; end process; ------------------------------------------------------------------------------------------------------- process (CLOCK) -- Reset für IC. Kommunikation mit DS1626 nur bei Reset möglich begin if (CLOCK'event and CLOCK = '1') then if I = freq_MESS_2 then CLOCK_MESS <= not CLOCK_MESS; I <= 0; else I <= I + 1; end if; end if; end process; -------------------------------------------------------------------------------------------------------- process (CLOCK) begin if (CLOCK'event and CLOCK = '1') then if (SW(7) = '0') then DATA <= SW; TEMP <= to_integer(DATA); SEG_VORZ <= "00000000"; else DATA <= not SW; TEMP <= to_integer(DATA); -- Zweierkomplement TEMP <= TEMP + 1; SEG_VORZ <= "00000010"; -- Minuszeichen end if; TEMP_100 <= TEMP / 100; case TEMP_100 is when 0 => SEG_100 <= "11111100"; --Hunderterstelle ermitteln when 1 => SEG_100 <= "01100000"; TEMP <= TEMP - 100; when others => SEG_100 <= "00000000"; end case; TEMP_10 <= TEMP / 10; case TEMP_10 is when 0 => SEG_10 <= "01111110"; -- Zehnerstelle ermitteln when 1 => SEG_10 <= "00001100"; TEMP <= TEMP - 10; when 2 => SEG_10 <= "10110110"; TEMP <= TEMP - 20; when 3 => SEG_10 <= "10011110"; TEMP <= TEMP - 30; when 4 => SEG_10 <= "11001100"; TEMP <= TEMP - 40; when 5 => SEG_10 <= "11011010"; TEMP <= TEMP - 50; when 6 => SEG_10 <= "11111010"; TEMP <= TEMP - 60; when 7 => SEG_10 <= "00001110"; TEMP <= TEMP - 70; when 8 => SEG_10 <= "11111110"; TEMP <= TEMP - 80; when 9 => SEG_10 <= "11001110"; TEMP <= TEMP - 90; when others => SEG_10 <= "00000000"; end case; case TEMP is -- 1er Stelle when 0 => SEG_1 <= "01111110"; when 1 => SEG_1 <= "00001100"; when 2 => SEG_1 <= "10110110"; when 3 => SEG_1 <= "10011110"; when 4 => SEG_1 <= "11001100"; when 5 => SEG_1 <= "11011010"; when 6 => SEG_1 <= "11111010"; when 7 => SEG_1 <= "00001110"; when 8 => SEG_1 <= "11111110"; when 9 => SEG_1 <= "11001110"; when others => SEG_1 <= "00000000"; end case; end if; end process; process (CLOCK) begin -- Ausgabe der Ziffern if (CLOCK'event and CLOCK = '1') then if (CLOCK_AUSGABE = '1') then case X is when 0 => SEG_OUT <= SEG_1; AN_OUT <= "0001"; X <= X + 1; when 1 => SEG_OUT <= SEG_10; AN_OUT <= "0010"; X <= X + 1; when 2 => SEG_OUT <= SEG_100; AN_OUT <= "0100"; X <= X + 1; when 3 => SEG_OUT <= SEG_VORZ; AN_OUT <= "1000"; X <= 0; when others => AN_OUT <= "0000"; X <= 0; end case; end if; end if; end process; end PModTMP;