MODULE Latch

TITLE 'Erweiterung mit Latch'

declarations

	X0,X1,X2,X3	PIN 2,3,4,5;				"Eingänge des GAL Bausteins deklariert
	X4		PIN 6;					"Latch Enable Pin
	A,B,C,D,E,F,G	PIN 15,16,17,18,19,13,14 istype 'reg,buffer';	"Ausgänge des GAL Bausteins deklariert

	input = [X3,X2,X1,X0];					"[MSB,_,_,LSB]
	output = [A,B,C,D,E,F,G];

equations

	A = X1&X2 # !X0&!X2 # X3&!X2&!X1 # X1&!X3 # X0&X2&!X3;	"Logische Gleichungen für die einzelnen
	B = !X0&!X1&!X3 # X0&X1&!X3 # !X2&!X3 # !X0&!X2 # X0&X3&!X1;			"Segmente der 7-Segmentanzeige
	C = !X1&!X3 # !X3&X2 # X0&!X2 # X3&!X2 # X0&!X1;
	D = X3&!X1 # !X2&!X3&!X0 # X1&!X0&X2 # X1&X0&!X2 # !X1&X0&X2;
	E = X1&!X0 # !X0&!X2 # X1&X3 # X3&X2;
	F = !X2&X3 # !X0&X1&X2 # !X0&!X1&!X2 # !X1&X2&!X3 # X1&X3&X2;
	G = X3 # !X1&X2 # X1&!X2 # !X0&X2;

	output := X0;
	output := X1;
	output := X2;
	output := X3;

	output.lh = X4;		

TEST_VECTORS   ([input] -> [ A, B, C, D, E, F, G ])		"Notwendige Segmente zur Zahlendarstellung für 
		[ 0 ]	-> [ 1, 1, 1, 1, 1, 1, 0 ];		"die im BCD-Code anliegenden Eingangsvariablen
		[ 1 ]	-> [ 0, 1, 1, 0, 0, 0, 0 ];
		[ 2 ]	-> [ 1, 1, 0, 1, 1, 0, 1 ];
		[ 3 ]	-> [ 1, 1, 1, 1, 0, 0, 1 ];
		[ 4 ]	-> [ 0, 1, 1, 0, 0, 1, 1 ];
		[ 5 ]	-> [ 1, 0, 1, 1, 0, 1, 1 ];
		[ 6 ]	-> [ 1, 0, 1, 1, 1, 1, 1 ];
		[ 7 ]	-> [ 1, 1, 1, 0, 0, 0, 0 ];
		[ 8 ]	-> [ 1, 1, 1, 1, 1, 1, 1 ];
		[ 9 ]	-> [ 1, 1, 1, 1, 0, 1, 1 ];
		[ 10 ]	-> [ 1, 1, 1, 0, 1, 1, 1 ];
		[ 11 ] 	-> [ 0, 0, 1, 1, 1, 1, 1 ];
		[ 12 ] 	-> [ 0, 0, 0, 1, 1, 0, 1 ];
		[ 13 ] 	-> [ 0, 1, 1, 1, 1, 0, 1 ];
		[ 14 ]	-> [ 1, 0, 0, 1, 1, 1, 1 ];
		[ 15 ]	-> [ 1, 0, 0, 0, 1, 1, 1 ];		

END