Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:13.3 (WebPack) - O.76xd Target Family: Spartan3E
OS Platform: NT Target Device: xc3s1200e
Project ID (random number) 70285ae3158b4c6a8747d6778bcb7002.4C710B9390D24028BC1EA3C0AA0DE3BC.13 Target Package: fg320
Registration ID 208478444_0_0_332 Target Speed: -4
Date Generated 2011-11-23T20:36:36 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 32-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Atom(TM) CPU N550 @ 1.50GHz CPU Speed 1496 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Adders/Subtractors=2
  • 13-bit adder=2
Registers=22
  • Flip-Flops=22
MiscellaneousStatistics
  • AGG_BONDED_IO=11
  • AGG_IO=11
  • AGG_SLICE=46
  • NUM_4_INPUT_LUT=74
  • NUM_BONDED_IBUF=2
  • NUM_BONDED_IOB=9
  • NUM_BUFGMUX=1
  • NUM_CYMUX=24
  • NUM_LUT_RT=14
  • NUM_RPM=8
  • NUM_SLICEL=46
  • NUM_SLICE_FF=22
  • NUM_XOR=26
NetStatistics
  • NumNets_Active=97
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_CLKPIN=19
  • NumNodesOfType_Active_CNTRLPIN=1
  • NumNodesOfType_Active_DOUBLE=90
  • NumNodesOfType_Active_DUMMY=214
  • NumNodesOfType_Active_DUMMYESC=2
  • NumNodesOfType_Active_GLOBAL=8
  • NumNodesOfType_Active_HFULLHEX=1
  • NumNodesOfType_Active_HLONG=1
  • NumNodesOfType_Active_HUNIHEX=1
  • NumNodesOfType_Active_INPUT=250
  • NumNodesOfType_Active_IOBOUTPUT=2
  • NumNodesOfType_Active_OMUX=87
  • NumNodesOfType_Active_OUTPUT=84
  • NumNodesOfType_Active_PREBXBY=59
  • NumNodesOfType_Active_VFULLHEX=3
  • NumNodesOfType_Active_VLONG=1
  • NumNodesOfType_Active_VUNIHEX=6
  • NumNodesOfType_Gnd_DOUBLE=1
  • NumNodesOfType_Gnd_INPUT=2
  • NumNodesOfType_Gnd_OMUX=1
  • NumNodesOfType_Gnd_OUTPUT=1
  • NumNodesOfType_Gnd_PREBXBY=3
SiteStatistics
  • IBUF-DIFFMI=1
  • IOB-DIFFM=4
  • IOB-DIFFS=5
  • SLICEL-SLICEM=21
SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IBUF=2
  • IBUF_INBUF=2
  • IBUF_PAD=2
  • IOB=9
  • IOB_OUTBUF=9
  • IOB_PAD=9
  • SLICEL=46
  • SLICEL_C1VDD=2
  • SLICEL_CYMUXF=12
  • SLICEL_CYMUXG=12
  • SLICEL_F=37
  • SLICEL_F5MUX=9
  • SLICEL_FFX=8
  • SLICEL_FFY=14
  • SLICEL_G=37
  • SLICEL_GNDF=10
  • SLICEL_GNDG=12
  • SLICEL_XORF=14
  • SLICEL_XORG=12
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:2]
IOB
  • O1=[O1_INV:0] [O1:9]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:9]
IOB_PAD
  • DRIVEATTRBOX=[12:9]
  • IOATTRBOX=[LVCMOS25:9]
  • SLEW=[SLOW:9]
SLICEL
  • BX=[BX_INV:0] [BX:11]
  • BY=[BY:5] [BY_INV:1]
  • CE=[CE:1] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:12]
  • CLK=[CLK:15] [CLK_INV:4]
SLICEL_CYMUXF
  • 0=[0:12] [0_INV:0]
  • 1=[1_INV:0] [1:12]
SLICEL_CYMUXG
  • 0=[0:12] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:9] [S0_INV:0]
SLICEL_FFX
  • CK=[CK:8] [CK_INV:0]
  • D=[D:8] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:8]
  • FFX_SR_ATTR=[SRLOW:8]
  • LATCH_OR_FF=[FF:8]
  • SYNC_ATTR=[ASYNC:8]
SLICEL_FFY
  • CE=[CE:1] [CE_INV:0]
  • CK=[CK:10] [CK_INV:4]
  • D=[D:13] [D_INV:1]
  • FFY_INIT_ATTR=[INIT0:14]
  • FFY_SR_ATTR=[SRLOW:14]
  • LATCH_OR_FF=[FF:14]
  • SYNC_ATTR=[ASYNC:14]
SLICEL_XORF
  • 1=[1_INV:0] [1:14]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IBUF
  • I=2
  • PAD=2
IBUF_INBUF
  • IN=2
  • OUT=2
IBUF_PAD
  • PAD=2
IOB
  • O1=9
  • PAD=9
IOB_OUTBUF
  • IN=9
  • OUT=9
IOB_PAD
  • PAD=9
SLICEL
  • BX=11
  • BY=6
  • CE=1
  • CIN=12
  • CLK=19
  • COUT=12
  • F1=37
  • F2=29
  • F3=29
  • F4=18
  • G1=37
  • G2=27
  • G3=25
  • G4=11
  • X=29
  • XQ=8
  • Y=20
  • YQ=14
SLICEL_C1VDD
  • 1=2
SLICEL_CYMUXF
  • 0=12
  • 1=12
  • OUT=12
  • S0=12
SLICEL_CYMUXG
  • 0=12
  • 1=12
  • OUT=12
  • S0=12
SLICEL_F
  • A1=37
  • A2=29
  • A3=29
  • A4=18
  • D=37
SLICEL_F5MUX
  • F=9
  • G=9
  • OUT=9
  • S0=9
SLICEL_FFX
  • CK=8
  • D=8
  • Q=8
SLICEL_FFY
  • CE=1
  • CK=14
  • D=14
  • Q=14
SLICEL_G
  • A1=37
  • A2=27
  • A3=25
  • A4=11
  • D=37
SLICEL_GNDF
  • 0=10
SLICEL_GNDG
  • 0=12
SLICEL_XORF
  • 0=14
  • 1=14
  • O=14
SLICEL_XORG
  • 0=12
  • 1=12
  • O=12
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s1200e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1200e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s1200e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1200e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s1200e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1200e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s1200e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1200e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s1200e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1200e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s1200e-fg320-4 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s1200e-fg320-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • fuse
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
bitgen 30 30 0 0 0 0 0
map 40 37 0 0 0 0 0
netgen 4 2 0 0 0 0 0
ngdbuild 48 48 0 0 0 0 0
par 37 30 7 0 0 0 0
trce 31 31 0 0 0 0 0
xst 60 60 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/spartan3e/libs_le_and2.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_OverwriteSym=true
PROP_PropSpecInProjFile=Store all values PROP_SelectedInstanceHierarchicalPath=/SCHcounter_CLK_SCHcounter_CLK_sch_tb
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=Schematic PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2011-11-21T04:45:50
PROP_intWbtProjectID=4C710B9390D24028BC1EA3C0AA0DE3BC PROP_intWbtProjectIteration=13
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_selectedSimRootSourceNode_behav=work.SCHcounter_CLK_SCHcounter_CLK_sch_tb PROP_AutoTop=false
PROP_DevFamily=Spartan3E PROP_DevDevice=xc3s1200e
PROP_DevFamilyPMName=spartan3e PROP_DevPackage=fg320
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-4
PROP_PreferredLanguage=Verilog FILE_SCHEMATIC=4
FILE_VHDL=2
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_AND2=4 NGDBUILD_NUM_AND2B1=8 NGDBUILD_NUM_AND3=1 NGDBUILD_NUM_AND3B1=8
NGDBUILD_NUM_AND3B2=8 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=13 NGDBUILD_NUM_FDC=8
NGDBUILD_NUM_FDE=1 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=1 NGDBUILD_NUM_INV=22
NGDBUILD_NUM_LUT1=12 NGDBUILD_NUM_LUT2_L=2 NGDBUILD_NUM_LUT3=21 NGDBUILD_NUM_LUT3_D=1
NGDBUILD_NUM_LUT3_L=2 NGDBUILD_NUM_LUT4=26 NGDBUILD_NUM_LUT4_L=1 NGDBUILD_NUM_MUXCY=24
NGDBUILD_NUM_MUXF5=9 NGDBUILD_NUM_OBUF=9 NGDBUILD_NUM_OR3=8 NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=26
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_AND2=4 NGDBUILD_NUM_AND2B1=8 NGDBUILD_NUM_AND3=1 NGDBUILD_NUM_AND3B1=8
NGDBUILD_NUM_AND3B2=8 NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=13 NGDBUILD_NUM_FDC=8
NGDBUILD_NUM_FDE=1 NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=1 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=22 NGDBUILD_NUM_LUT1=12 NGDBUILD_NUM_LUT2_L=2 NGDBUILD_NUM_LUT3=21
NGDBUILD_NUM_LUT3_D=1 NGDBUILD_NUM_LUT3_L=2 NGDBUILD_NUM_LUT4=26 NGDBUILD_NUM_LUT4_L=1
NGDBUILD_NUM_MUXCY=24 NGDBUILD_NUM_MUXF5=9 NGDBUILD_NUM_OBUF=9 NGDBUILD_NUM_OR3=8
NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=26
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s1200e-4-fg320 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5
 
ISim Statistics
Xilinx HDL Libraries Used=unisims_ver, ieee
Fuse Resource Usage=2698 ms, 123408 KB
Total Signals=401
Total Nets=140
Total Blocks=84
Total Processes=171
Total Simulation Time=602148790 ps
Simulation Resource Usage=300.505 sec, 466784 KB
Simulation Mode=gui
Hardware CoSim=0