SCHcounter_BTN Project Status
Project File: SCHcounter.xise Parser Errors: No Errors
Module Name: SCHcounter_BTN Implementation State: Programming File Not Generated
Target Device: xc3s1200e-4fg320
  • Errors:
No Errors
Product Version:ISE 13.3
  • Warnings:
16 Warnings (16 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 22 17,344 1%  
Number of 4 input LUTs 60 17,344 1%  
Number of occupied Slices 46 8,672 1%  
    Number of Slices containing only related logic 46 46 100%  
    Number of Slices containing unrelated logic 0 46 0%  
Total Number of 4 input LUTs 74 17,344 1%  
    Number used as logic 60      
    Number used as a route-thru 14      
Number of bonded IOBs 11 250 4%  
Number of BUFGMUXs 1 24 4%  
Number of RPM macros 8      
Average Fanout of Non-Clock Nets 3.00      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMi 23. Nov 20:30:39 2011015 Warnings (15 new)1 Info (0 new)
Translation ReportCurrentMi 23. Nov 20:31:28 2011000
Map ReportCurrentMi 23. Nov 20:32:20 2011002 Infos (0 new)
Place and Route ReportCurrentMi 23. Nov 20:34:36 201101 Warning (1 new)2 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentMi 23. Nov 20:35:24 2011005 Infos (0 new)
Bitgen ReportCurrentMi 23. Nov 20:36:16 2011000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentSo 27. Nov 17:02:40 2011
WebTalk ReportCurrentMi 23. Nov 20:36:36 2011
WebTalk Log FileCurrentMi 23. Nov 20:36:59 2011

Date Generated: 11/27/2011 - 20:20:22