SCHcounter_CLK Project Status (11/23/2011 - 20:37:02)
Project File: SCHcounter.xise Parser Errors: No Errors
Module Name: SCHcounter_CLK Implementation State: Programming File Generated
Target Device: xc3s1200e-4fg320
  • Errors:
 
Product Version:ISE 13.3
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 64 17,344 1%  
Number of 4 input LUTs 24 17,344 1%  
Number of occupied Slices 64 8,672 1%  
    Number of Slices containing only related logic 64 64 100%  
    Number of Slices containing unrelated logic 0 64 0%  
Total Number of 4 input LUTs 24 17,344 1%  
Number of bonded IOBs 10 250 4%  
Number of BUFGMUXs 1 24 4%  
Number of RPM macros 64      
Average Fanout of Non-Clock Nets 2.26      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMi 23. Nov 20:16:05 2011   
Translation ReportCurrentMi 23. Nov 20:16:56 2011   
Map ReportCurrentMi 23. Nov 20:17:59 2011   
Place and Route ReportCurrentMi 23. Nov 20:20:25 2011   
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportCurrentMi 23. Nov 20:21:31 2011   
Bitgen ReportCurrentMi 23. Nov 20:22:24 2011   
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateMo 21. Nov 09:40:37 2011
WebTalk ReportCurrentMi 23. Nov 20:36:36 2011
WebTalk Log FileCurrentMi 23. Nov 20:36:59 2011

Date Generated: 11/23/2011 - 20:37:03