Project Statistics |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_OverwriteSym=true |
PROP_PropSpecInProjFile=Store all values |
PROP_SelectedInstanceHierarchicalPath=/SCHcounter_CLK_SCHcounter_CLK_sch_tb |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=Schematic |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2011-11-21T04:45:50 |
PROP_intWbtProjectID=4C710B9390D24028BC1EA3C0AA0DE3BC |
PROP_intWbtProjectIteration=13 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_selectedSimRootSourceNode_behav=work.SCHcounter_CLK_SCHcounter_CLK_sch_tb |
PROP_AutoTop=false |
PROP_DevFamily=Spartan3E |
PROP_DevDevice=xc3s1200e |
PROP_DevFamilyPMName=spartan3e |
PROP_DevPackage=fg320 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-4 |
PROP_PreferredLanguage=Verilog |
FILE_SCHEMATIC=4 |
FILE_VHDL=2 |