Release 13.2 - xst O.61xd (nt)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 2.00 secs
Total CPU time to Xst completion: 1.28 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 2.00 secs
Total CPU time to Xst completion: 1.28 secs
 
--> Reading design: microblaze_own_IP_III_top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "microblaze_own_IP_III_top.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "microblaze_own_IP_III_top"
Output Format                      : NGC
Target Device                      : xc3s500e-4-fg320

---- Source Options
Top Module Name                    : microblaze_own_IP_III_top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : Yes
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : Yes
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Multiplier Style                   : Auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 24
Register Duplication               : YES
Slice Packing                      : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Yes
Use Synchronous Set                : Yes
Use Synchronous Reset              : Yes
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
Verilog 2001                       : YES
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/Projekte/uBlaze/microblaze_own_IP_III/microblaze_own_IP_III/hdl/microblaze_own_IP_III.vhd" in Library work.
Entity <microblaze_own_IP_III> compiled.
Entity <microblaze_own_IP_III> (Architecture <STRUCTURE>) compiled.
Compiling vhdl file "D:/Projekte/uBlaze/microblaze_own_IP_III/microblaze_own_IP_III/microblaze_own_IP_III_top.vhd" in Library work.
Entity <microblaze_own_IP_III_top> compiled.
Entity <microblaze_own_IP_III_top> (Architecture <STRUCTURE>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <microblaze_own_IP_III_top> in library <work> (architecture <STRUCTURE>).


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <microblaze_own_IP_III_top> in library <work> (Architecture <STRUCTURE>).
Entity <microblaze_own_IP_III_top> analyzed. Unit <microblaze_own_IP_III_top> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <microblaze_own_IP_III_top>.
    Related source file is "D:/Projekte/uBlaze/microblaze_own_IP_III/microblaze_own_IP_III/microblaze_own_IP_III_top.vhd".
Unit <microblaze_own_IP_III_top> synthesized.


=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Reading core <microblaze_own_IP_III.ngc>.
Reading core <microblaze_0_wrapper.ngc>.
Reading core <mb_plb_wrapper.ngc>.
Reading core <ilmb_wrapper.ngc>.
Reading core <dlmb_wrapper.ngc>.
Reading core <dlmb_cntlr_wrapper.ngc>.
Reading core <ilmb_cntlr_wrapper.ngc>.
Reading core <lmb_bram_wrapper.ngc>.
Reading core <rs232_dce_wrapper.ngc>.
Reading core <dip_switches_4bit_wrapper.ngc>.
Reading core <buttons_4bit_wrapper.ngc>.
Reading core <ddr_sdram_wrapper.ngc>.
Reading core <clock_generator_0_wrapper.ngc>.
Reading core <mdm_0_wrapper.ngc>.
Reading core <proc_sys_reset_0_wrapper.ngc>.
Reading core <pwm_lights_0_wrapper.ngc>.
Loading core <microblaze_0_wrapper> for timing and area information for instance <microblaze_0>.
Loading core <mb_plb_wrapper> for timing and area information for instance <mb_plb>.
Loading core <ilmb_wrapper> for timing and area information for instance <ilmb>.
Loading core <dlmb_wrapper> for timing and area information for instance <dlmb>.
Loading core <dlmb_cntlr_wrapper> for timing and area information for instance <dlmb_cntlr>.
Loading core <ilmb_cntlr_wrapper> for timing and area information for instance <ilmb_cntlr>.
Loading core <lmb_bram_wrapper> for timing and area information for instance <lmb_bram>.
Loading core <rs232_dce_wrapper> for timing and area information for instance <RS232_DCE>.
Loading core <dip_switches_4bit_wrapper> for timing and area information for instance <DIP_Switches_4Bit>.
Loading core <buttons_4bit_wrapper> for timing and area information for instance <Buttons_4Bit>.
Loading core <ddr_sdram_wrapper> for timing and area information for instance <DDR_SDRAM>.
Loading core <clock_generator_0_wrapper> for timing and area information for instance <clock_generator_0>.
Loading core <mdm_0_wrapper> for timing and area information for instance <mdm_0>.
Loading core <proc_sys_reset_0_wrapper> for timing and area information for instance <proc_sys_reset_0>.
Loading core <pwm_lights_0_wrapper> for timing and area information for instance <pwm_lights_0>.
Loading core <microblaze_own_IP_III> for timing and area information for instance <microblaze_own_IP_III_i>.

=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <microblaze_own_IP_III_top> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block microblaze_own_IP_III_top, actual ratio is 59.
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_MPLB_RST[1].I_MPLB_RST> in Unit <mb_plb> is equivalent to the following 8 FFs/Latches : <mb_plb/GEN_MPLB_RST[0].I_MPLB_RST> <mb_plb/GEN_SPLB_RST[5].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[4].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[3].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[2].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[1].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[0].I_SPLB_RST> <mb_plb/I_PLB_RST> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1> in Unit <mb_plb> is equivalent to the following 3 FFs/Latches : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1_1> <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1_2> <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1_3> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0> in Unit <mb_plb> is equivalent to the following 3 FFs/Latches : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0_1> <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0_2> <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0_3> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd3> in Unit <mb_plb> is equivalent to the following FF/Latch : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd3_1> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/addr_cs_FSM_FFd3> in Unit <DDR_SDRAM> is equivalent to the following FF/Latch : <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/addr_cs_FSM_FFd3_1> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1> in Unit <DDR_SDRAM> is equivalent to the following 13 FFs/Latches : <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_1> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_2> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_3> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_4> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_5>
   <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_6> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_7> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_8> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_9> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_10> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_11> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_12>
   <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_13> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0> in Unit <DDR_SDRAM> is equivalent to the following 13 FFs/Latches : <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_1> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_2> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_3> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_4> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_5> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_6> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_7> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_8> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_9> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_10> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_11>
   <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_12> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_13> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_write/dqs_rst_180_r1> in Unit <DDR_SDRAM> is equivalent to the following FF/Latch : <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_write/dqs_rst_180_r1_1> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_1> in Unit <DDR_SDRAM> is equivalent to the following 9 FFs/Latches : <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_1_1> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_1_2> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_1_3> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_1_4> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_1_5> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_1_6> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_1_7> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_1_8> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_1_9> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/addr_cs_FSM_FFd1> in Unit <DDR_SDRAM> is equivalent to the following FF/Latch : <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/addr_cs_FSM_FFd1_1> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_write/dq_oe_90_r1> in Unit <DDR_SDRAM> is equivalent to the following 2 FFs/Latches : <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_write/dq_oe_90_r1_1> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_write/dq_oe_90_r1_2> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3> in Unit <DDR_SDRAM> is equivalent to the following 10 FFs/Latches : <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3_1> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3_2> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3_3> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3_4> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3_5> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3_6> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3_7> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3_8> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3_9> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3_10> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/mpmc_core_0/InitDone_i2_0> in Unit <DDR_SDRAM> is equivalent to the following FF/Latch : <DDR_SDRAM/mpmc_core_0/InitDone> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2> in Unit <DDR_SDRAM> is equivalent to the following 11 FFs/Latches : <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_1> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_2> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_3> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_4> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_5> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_6> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_7> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_8> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_9> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_10> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_11> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_READ_MODULE/sig_sl_rdack_i> in Unit <DDR_SDRAM> is equivalent to the following FF/Latch : <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_READ_MODULE/sig_sl_rdack> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/sc2wr_sample_cycle_i> in Unit <DDR_SDRAM> is equivalent to the following 2 FFs/Latches : <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/sc2rd_sample_cycle_i> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/sc2ad_sample_cycle_i> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_write/dqs_oe_180_r1> in Unit <DDR_SDRAM> is equivalent to the following FF/Latch : <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_write/dqs_oe_180_r1_1> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/Rst_tocore_5> in Unit <DDR_SDRAM> is equivalent to the following 5 FFs/Latches : <DDR_SDRAM/Rst_tocore_4> <DDR_SDRAM/Rst_tocore_1> <DDR_SDRAM/Rst_tocore_0> <DDR_SDRAM/Rst_topim_0> <DDR_SDRAM/Rst_tocore_tmp> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_MPLB_RST[1].I_MPLB_RST> in Unit <mb_plb> is equivalent to the following 8 FFs/Latches : <mb_plb/GEN_MPLB_RST[0].I_MPLB_RST> <mb_plb/GEN_SPLB_RST[5].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[4].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[3].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[2].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[1].I_SPLB_RST> <mb_plb/GEN_SPLB_RST[0].I_SPLB_RST> <mb_plb/I_PLB_RST> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1> in Unit <mb_plb> is equivalent to the following 3 FFs/Latches : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1_1> <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1_2> <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_1_3> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0> in Unit <mb_plb> is equivalent to the following 3 FFs/Latches : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0_1> <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0_2> <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARB_ENCODER/arbAddrSelReg_i_0_3> 
INFO:Xst:2260 - The FF/Latch <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd3> in Unit <mb_plb> is equivalent to the following FF/Latch : <mb_plb/GEN_SHARED.I_PLB_ARBITER_LOGIC/I_ARBCONTROL_SM/arbctrl_sm_cs_FSM_FFd3_1> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/addr_cs_FSM_FFd3> in Unit <DDR_SDRAM> is equivalent to the following FF/Latch : <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/addr_cs_FSM_FFd3_1> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1> in Unit <DDR_SDRAM> is equivalent to the following 13 FFs/Latches : <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_1> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_2> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_3> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_4> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_5>
   <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_6> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_7> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_8> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_9> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_10> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_11> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_12>
   <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/plb_rst_pipe_1_13> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0> in Unit <DDR_SDRAM> is equivalent to the following 13 FFs/Latches : <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_1> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_2> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_3> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_4> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_5> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_6> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_7> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_8> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_9> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_10> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_11>
   <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_12> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0_13> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_write/dqs_rst_180_r1> in Unit <DDR_SDRAM> is equivalent to the following FF/Latch : <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_write/dqs_rst_180_r1_1> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_1> in Unit <DDR_SDRAM> is equivalent to the following 9 FFs/Latches : <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_1_1> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_1_2> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_1_3> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_1_4> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_1_5> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_1_6> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_1_7> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_1_8> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_1_9> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/addr_cs_FSM_FFd1> in Unit <DDR_SDRAM> is equivalent to the following FF/Latch : <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/addr_cs_FSM_FFd1_1> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_write/dq_oe_90_r1> in Unit <DDR_SDRAM> is equivalent to the following 2 FFs/Latches : <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_write/dq_oe_90_r1_1> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_write/dq_oe_90_r1_2> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3> in Unit <DDR_SDRAM> is equivalent to the following 10 FFs/Latches : <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3_1> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3_2> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3_3> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3_4> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3_5> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3_6> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3_7> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3_8> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3_9> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_3_10> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/mpmc_core_0/InitDone_i2_0> in Unit <DDR_SDRAM> is equivalent to the following FF/Latch : <DDR_SDRAM/mpmc_core_0/InitDone> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2> in Unit <DDR_SDRAM> is equivalent to the following 11 FFs/Latches : <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_1> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_2> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_3> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_4> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_5> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_6> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_7> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_8> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_9> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_10> <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_2_11> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_READ_MODULE/sig_sl_rdack_i> in Unit <DDR_SDRAM> is equivalent to the following FF/Latch : <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_READ_MODULE/sig_sl_rdack> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/sc2wr_sample_cycle_i> in Unit <DDR_SDRAM> is equivalent to the following 2 FFs/Latches : <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/sc2rd_sample_cycle_i> <DDR_SDRAM/PLB_0_INST.plbv46_pim_0/comp_plbv46_pim/GENERATE_SINGLES_PLBV46_PIM.PIM_ADDRESS_DECODER/CLOCK_TO_N_SAMPLE_CIRCUIT/sc2ad_sample_cycle_i> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_write/dqs_oe_180_r1> in Unit <DDR_SDRAM> is equivalent to the following FF/Latch : <DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_write/dqs_oe_180_r1_1> 
INFO:Xst:2260 - The FF/Latch <DDR_SDRAM/Rst_tocore_5> in Unit <DDR_SDRAM> is equivalent to the following 5 FFs/Latches : <DDR_SDRAM/Rst_tocore_4> <DDR_SDRAM/Rst_tocore_1> <DDR_SDRAM/Rst_tocore_0> <DDR_SDRAM/Rst_topim_0> <DDR_SDRAM/Rst_tocore_tmp> 

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : microblaze_own_IP_III_top.ngr
Top Level Output File Name         : microblaze_own_IP_III_top
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : No

Design Statistics
# IOs                              : 63

Cell Usage :
# BELS                             : 4235
#      BUF                         : 4
#      GND                         : 16
#      INV                         : 100
#      LUT1                        : 104
#      LUT2                        : 368
#      LUT2_D                      : 14
#      LUT2_L                      : 13
#      LUT3                        : 935
#      LUT3_D                      : 56
#      LUT3_L                      : 19
#      LUT4                        : 1545
#      LUT4_D                      : 31
#      LUT4_L                      : 52
#      MULT_AND                    : 34
#      MUXCY                       : 249
#      MUXCY_L                     : 136
#      MUXF5                       : 317
#      MUXF6                       : 6
#      MUXF7                       : 2
#      MUXF8                       : 1
#      VCC                         : 10
#      XORCY                       : 223
# FlipFlops/Latches                : 3641
#      FD                          : 669
#      FD_1                        : 10
#      FDC                         : 20
#      FDC_1                       : 5
#      FDCE                        : 46
#      FDE                         : 300
#      FDE_1                       : 8
#      FDP                         : 13
#      FDR                         : 1496
#      FDR_1                       : 17
#      FDRE                        : 742
#      FDRE_1                      : 1
#      FDRS                        : 71
#      FDRS_1                      : 2
#      FDRSE                       : 51
#      FDS                         : 94
#      FDS_1                       : 4
#      FDSE                        : 71
#      ODDR2                       : 21
# RAMS                             : 173
#      RAM16X1D                    : 160
#      RAMB16_S18_S36              : 4
#      RAMB16_S36                  : 1
#      RAMB16_S4_S4                : 8
# Shift Registers                  : 149
#      SRL16                       : 26
#      SRL16E                      : 115
#      SRLC16E                     : 8
# Clock Buffers                    : 7
#      BUFG                        : 7
# IO Buffers                       : 80
#      IBUF                        : 27
#      IBUFG                       : 1
#      IOBUF                       : 2
#      OBUF                        : 33
#      OBUFDS                      : 1
#      OBUFT                       : 16
# DCMs                             : 2
#      DCM_SP                      : 2
# MULTs                            : 3
#      MULT18X18SIO                : 3
# Others                           : 1
#      BSCAN_SPARTAN3              : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s500efg320-4 

 Number of Slices:                     2755  out of   4656    59%  
 Number of Slice Flip Flops:           3641  out of   9312    39%  
 Number of 4 input LUTs:               3706  out of   9312    39%  
    Number used as logic:              3237
    Number used as Shift registers:     149
    Number used as RAMs:                320
 Number of IOs:                          63
 Number of bonded IOBs:                  63  out of    232    27%  
 Number of BRAMs:                        13  out of     20    65%  
 Number of MULT18X18SIOs:                 3  out of     20    15%  
 Number of GCLKs:                         7  out of     24    29%  
 Number of DCMs:                          2  out of      4    50%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
Clock Signal                                                                                                                                                                                                                                                                        | Clock buffer(FF name)                                                                                                                                           | Load  |
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
fpga_0_clk_1_sys_clk_pin                                                                                                                                                                                                                                                            | clock_generator_0/DCM1_INST/Using_Virtex.DCM_INST:CLK0                                                                                                          | 2541  |
microblaze_own_IP_III_i/mdm_0/mdm_0/drck_i                                                                                                                                                                                                                                          | BUFG                                                                                                                                                            | 208   |
microblaze_own_IP_III_i/mdm_0/bscan_update1                                                                                                                                                                                                                                         | BUFG                                                                                                                                                            | 42    |
fpga_0_clk_1_sys_clk_pin                                                                                                                                                                                                                                                            | clock_generator_0/DCM1_INST/Using_Virtex.DCM_INST:CLK2X+clock_generator_0/DCM0_INST/Using_Virtex.DCM_INST:CLK0                                                  | 900   |
fpga_0_clk_1_sys_clk_pin                                                                                                                                                                                                                                                            | clock_generator_0/DCM1_INST/Using_Virtex.DCM_INST:CLK2X+clock_generator_0/DCM0_INST/Using_Virtex.DCM_INST:CLK90                                                 | 244   |
microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/dqs_delayed_col0<0>(microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]..u_dqs_delay_col1/gen_delay.one:O)| NONE(*)(microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_0_wr_en/delay_ff)  | 13    |
microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/dqs_delayed_col1<0>(microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[0]..u_dqs_delay_col0/gen_delay.one:O)| NONE(*)(microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_1_wr_en/delay_ff_1)| 13    |
microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/dqs_delayed_col0<1>(microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]..u_dqs_delay_col1/gen_delay.one:O)| NONE(*)(microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_0_wr_en/delay_ff)  | 13    |
microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/dqs_delayed_col1<1>(microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_dqs[1]..u_dqs_delay_col0/gen_delay.one:O)| NONE(*)(microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_1_wr_en/delay_ff_1)| 13    |
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
(*) These 4 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
Control Signal                                                                                                                                                                                                                                                                    | Buffer(FF name)                                                                                                                                                        | Load  |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
microblaze_own_IP_III_i/mdm_0/mdm_0/MDM_Core_I1/Config_Reg_Acst_inv(microblaze_own_IP_III_i/mdm_0/mdm_0/MDM_Core_I1/Config_Reg_Acst_inv1_INV_0:O)                                                                                                                                 | NONE(microblaze_own_IP_III_i/mdm_0/mdm_0/MDM_Core_I1/Config_Reg_0)                                                                                                     | 23    |
microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read/rd_addr_rst_reg(microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read/rd_addr_rst_reg:Q)                              | NONE(microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read/gen_rd_addr[0].fifo0_rd_addr_inst/gen_addr[0].u_addr_bit)| 16    |
microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/infrastructure/sys_rst_reg(microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/infrastructure/sys_rst_reg:Q)                                                | NONE(microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[0].u_addr_bit)  | 16    |
microblaze_own_IP_III_i/mdm_0/mdm_0/MDM_Core_I1/SEL_inv(microblaze_own_IP_III_i/mdm_0/mdm_0/MDM_Core_I1/SEL_inv1_INV_0:O)                                                                                                                                                         | NONE(microblaze_own_IP_III_i/mdm_0/mdm_0/MDM_Core_I1/PORT_Selector_0)                                                                                                  | 12    |
fpga_0_rst_1_sys_rst_pin                                                                                                                                                                                                                                                          | IBUF                                                                                                                                                                   | 4     |
microblaze_own_IP_III_i/clock_generator_0/clock_generator_0/DCM0_INST/reset(microblaze_own_IP_III_i/clock_generator_0/clock_generator_0/DCM0_INST/reset1_INV_0:O)                                                                                                                 | NONE(microblaze_own_IP_III_i/clock_generator_0/clock_generator_0/DCM0_INST/rst_delay_0)                                                                                | 4     |
microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/Command_Reg_Rst(microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/Command_Reg_Rst:Q)    | NONE(microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/command_reg_0)                              | 2     |
microblaze_own_IP_III_i/mdm_0/bscan_update1(microblaze_own_IP_III_i/mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:UPDATE)                                                                                                                                                             | BUFG(microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/running_clock)                              | 1     |
microblaze_own_IP_III_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/data_cmd_inv(microblaze_own_IP_III_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/data_cmd_inv1_INV_0:O)                                                                                                                 | NONE(microblaze_own_IP_III_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/execute)                                                                                           | 1     |
microblaze_own_IP_III_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/local_sel_n3(microblaze_own_IP_III_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/Insert_Delays[4].LUT_Delay:O)                                                                                                          | NONE(microblaze_own_IP_III_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I)                                                                                             | 1     |
microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/continue_from_brk(microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/continue_from_brk:Q)| NONE(microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/continue_from_brk_TClk)                     | 1     |
microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/force_stop_cmd(microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/force_stop_cmd1:O)     | NONE(microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/force_stop_TClk)                            | 1     |
microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/normal_stop_cmd(microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/normal_stop_cmd1:O)   | NONE(microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/normal_stop_TClk)                           | 1     |
microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/start_single_step(microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/start_single_step:Q)| NONE(microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/single_Step_TClk)                           | 1     |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 15.926ns (Maximum Frequency: 62.790MHz)
   Minimum input arrival time before clock: 4.704ns
   Maximum output required time after clock: 12.163ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'fpga_0_clk_1_sys_clk_pin'
  Clock period: 14.471ns (frequency: 69.105MHz)
  Total number of paths / destination ports: 157984 / 9295
-------------------------------------------------------------------------
Delay:               7.235ns (Levels of Logic = 4)
  Source:            microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_state_r_FSM_FFd2 (FF)
  Destination:       microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0 (FF)
  Source Clock:      fpga_0_clk_1_sys_clk_pin rising 2.0X
  Destination Clock: fpga_0_clk_1_sys_clk_pin rising 2.0X

  Data Path: microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_state_r_FSM_FFd2 to microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRS:C->Q            16   0.591   1.069  DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_state_r_FSM_FFd2 (DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_state_r_FSM_FFd2)
     LUT4_D:I2->LO         1   0.704   0.135  DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_state_r_FSM_Out51 (N361)
     LUT4:I2->O           26   0.704   1.264  DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_and0001 (DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_and0001)
     LUT4:I3->O           15   0.704   1.052  DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_or0000 (DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_or0000)
     LUT3:I2->O           14   0.704   0.000  DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_mux0000<3>11 (DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_mux0000<3>1)
     FDRS:D                    0.308          DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/phy_init/init_cnt_r_0
    ----------------------------------------
    Total                      7.235ns (3.715ns logic, 3.520ns route)
                                       (51.3% logic, 48.7% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'microblaze_own_IP_III_i/mdm_0/mdm_0/drck_i'
  Clock period: 12.228ns (frequency: 81.780MHz)
  Total number of paths / destination ports: 311 / 251
-------------------------------------------------------------------------
Delay:               6.114ns (Levels of Logic = 5)
  Source:            microblaze_own_IP_III_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE (FF)
  Destination:       microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/shift_count_7 (FF)
  Source Clock:      microblaze_own_IP_III_i/mdm_0/mdm_0/drck_i falling
  Destination Clock: microblaze_own_IP_III_i/mdm_0/mdm_0/drck_i rising

  Data Path: microblaze_own_IP_III_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/SYNC_FDRE to microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/shift_count_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE_1:C->Q           1   0.591   0.499  JTAG_CONTROL_I/SYNC_FDRE (JTAG_CONTROL_I/sync)
     LUT3:I1->O            1   0.704   0.424  JTAG_CONTROL_I/shifting_Data_SW0 (N34)
     LUT4:I3->O            9   0.704   0.820  JTAG_CONTROL_I/shifting_Data (Dbg_Shift_7)
     end scope: 'mdm_0/MDM_Core_I1'
     end scope: 'mdm_0'
     begin scope: 'microblaze_0'
     INV:I->O              8   0.704   0.757  microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/Shift_inv1_INV_0 (microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/Shift_inv)
     FDR:R                     0.911          microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/shift_count_0
    ----------------------------------------
    Total                      6.114ns (3.614ns logic, 2.500ns route)
                                       (59.1% logic, 40.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'microblaze_own_IP_III_i/mdm_0/bscan_update1'
  Clock period: 15.926ns (frequency: 62.790MHz)
  Total number of paths / destination ports: 329 / 50
-------------------------------------------------------------------------
Delay:               7.963ns (Levels of Logic = 6)
  Source:            microblaze_own_IP_III_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I (FF)
  Destination:       microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/control_reg_0 (FF)
  Source Clock:      microblaze_own_IP_III_i/mdm_0/bscan_update1 falling
  Destination Clock: microblaze_own_IP_III_i/mdm_0/bscan_update1 rising

  Data Path: microblaze_own_IP_III_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I to microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/control_reg_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q           14   0.591   1.175  JTAG_CONTROL_I/FDC_I (JTAG_CONTROL_I/data_cmd)
     LUT2:I0->O            2   0.704   0.622  JTAG_CONTROL_I/Dbg_Reg_En_I<2>1 (Dbg_Reg_En_0<2>)
     end scope: 'mdm_0/MDM_Core_I1'
     end scope: 'mdm_0'
     begin scope: 'microblaze_0'
     LUT4:I0->O            4   0.704   0.762  microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/Command_Reg_En_cmp_eq000011 (microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/N6)
     LUT3:I0->O            2   0.704   0.622  microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/Control_Reg_En_cmp_eq000011 (microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/N25)
     LUT3:I0->O            9   0.704   0.820  microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/Control_Reg_En_cmp_eq00001 (microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/Control_Reg_En)
     FDCE:CE                   0.555          microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/force_stop_TClk
    ----------------------------------------
    Total                      7.963ns (3.962ns logic, 4.001ns route)
                                       (49.8% logic, 50.2% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/dqs_delayed_col1<1>'
  Clock period: 6.620ns (frequency: 151.057MHz)
  Total number of paths / destination ports: 39 / 28
-------------------------------------------------------------------------
Delay:               3.310ns (Levels of Logic = 1)
  Source:            microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_1_wr_en/delay_ff_1 (FF)
  Destination:       microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_1_wr_addr/gen_addr[3].u_addr_bit (FF)
  Source Clock:      microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/dqs_delayed_col1<1> rising
  Destination Clock: microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/dqs_delayed_col1<1> falling

  Data Path: microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_1_wr_en/delay_ff_1 to microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_1_wr_addr/gen_addr[3].u_addr_bit
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.591   0.499  DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_1_wr_en/delay_ff_1 (DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_1_wr_en/din_delay)
     LUT2:I1->O           12   0.704   0.961  DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_1_wr_en/dout1 (DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/fifo_1_wr_en<1>)
     FDCE:CE                   0.555          DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_1_wr_addr/gen_addr[0].u_addr_bit
    ----------------------------------------
    Total                      3.310ns (1.850ns logic, 1.460ns route)
                                       (55.9% logic, 44.1% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/dqs_delayed_col0<1>'
  Clock period: 6.842ns (frequency: 146.156MHz)
  Total number of paths / destination ports: 43 / 32
-------------------------------------------------------------------------
Delay:               3.421ns (Levels of Logic = 1)
  Source:            microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_0_wr_en/delay_ff (FF)
  Destination:       microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_0_wr_addr/gen_addr[3].u_addr_bit (FF)
  Source Clock:      microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/dqs_delayed_col0<1> falling
  Destination Clock: microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/dqs_delayed_col0<1> rising

  Data Path: microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_0_wr_en/delay_ff to microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_0_wr_addr/gen_addr[3].u_addr_bit
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   0.591   0.610  DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_0_wr_en/delay_ff (DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_0_wr_en/din_delay)
     LUT2:I1->O           12   0.704   0.961  DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[1].u_fifo_0_wr_en/dout1 (DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/fifo_0_wr_en<1>)
     FDCE:CE                   0.555          DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[1].u_fifo_0_wr_addr/gen_addr[0].u_addr_bit
    ----------------------------------------
    Total                      3.421ns (1.850ns logic, 1.571ns route)
                                       (54.1% logic, 45.9% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/dqs_delayed_col1<0>'
  Clock period: 6.620ns (frequency: 151.057MHz)
  Total number of paths / destination ports: 39 / 28
-------------------------------------------------------------------------
Delay:               3.310ns (Levels of Logic = 1)
  Source:            microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_1_wr_en/delay_ff_1 (FF)
  Destination:       microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_1_wr_addr/gen_addr[3].u_addr_bit (FF)
  Source Clock:      microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/dqs_delayed_col1<0> rising
  Destination Clock: microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/dqs_delayed_col1<0> falling

  Data Path: microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_1_wr_en/delay_ff_1 to microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_1_wr_addr/gen_addr[3].u_addr_bit
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.591   0.499  DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_1_wr_en/delay_ff_1 (DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_1_wr_en/din_delay)
     LUT2:I1->O           12   0.704   0.961  DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_1_wr_en/dout1 (DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/fifo_1_wr_en<0>)
     FDCE:CE                   0.555          DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_1_wr_addr/gen_addr[0].u_addr_bit
    ----------------------------------------
    Total                      3.310ns (1.850ns logic, 1.460ns route)
                                       (55.9% logic, 44.1% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/dqs_delayed_col0<0>'
  Clock period: 6.842ns (frequency: 146.156MHz)
  Total number of paths / destination ports: 43 / 32
-------------------------------------------------------------------------
Delay:               3.421ns (Levels of Logic = 1)
  Source:            microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_0_wr_en/delay_ff (FF)
  Destination:       microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[3].u_addr_bit (FF)
  Source Clock:      microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/dqs_delayed_col0<0> falling
  Destination Clock: microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/dqs_delayed_col0<0> rising

  Data Path: microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_0_wr_en/delay_ff to microblaze_own_IP_III_i/DDR_SDRAM/DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[3].u_addr_bit
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   0.591   0.610  DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_0_wr_en/delay_ff (DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_0_wr_en/din_delay)
     LUT2:I1->O           12   0.704   0.961  DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read_controller/gen_wr[0].u_fifo_0_wr_en/dout1 (DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/fifo_0_wr_en<0>)
     FDCE:CE                   0.555          DDR_SDRAM/mpmc_core_0/gen_s3_ddr_phy.mpmc_phy_if_0/data_path/data_read/gen_wr_addr[0].u_fifo_0_wr_addr/gen_addr[0].u_addr_bit
    ----------------------------------------
    Total                      3.421ns (1.850ns logic, 1.571ns route)
                                       (54.1% logic, 45.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'microblaze_own_IP_III_i/mdm_0/mdm_0/drck_i'
  Total number of paths / destination ports: 122 / 98
-------------------------------------------------------------------------
Offset:              4.704ns (Levels of Logic = 4)
  Source:            microblaze_own_IP_III_i/mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:SHIFT (PAD)
  Destination:       microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/shift_count_7 (FF)
  Destination Clock: microblaze_own_IP_III_i/mdm_0/mdm_0/drck_i rising

  Data Path: microblaze_own_IP_III_i/mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:SHIFT to microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/shift_count_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    BSCAN_SPARTAN3:SHIFT    5   0.000   0.000  mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I (bscan_shift)
     begin scope: 'mdm_0/MDM_Core_I1'
     LUT4:I0->O            9   0.704   0.820  JTAG_CONTROL_I/shifting_Data (Dbg_Shift_7)
     end scope: 'mdm_0/MDM_Core_I1'
     end scope: 'mdm_0'
     begin scope: 'microblaze_0'
     INV:I->O              8   0.704   0.757  microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/Shift_inv1_INV_0 (microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/Shift_inv)
     FDR:R                     0.911          microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/shift_count_0
    ----------------------------------------
    Total                      4.704ns (3.127ns logic, 1.577ns route)
                                       (66.5% logic, 33.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'fpga_0_clk_1_sys_clk_pin'
  Total number of paths / destination ports: 10 / 10
-------------------------------------------------------------------------
Offset:              2.762ns (Levels of Logic = 2)
  Source:            fpga_0_rst_1_sys_rst_pin (PAD)
  Destination:       microblaze_own_IP_III_i/proc_sys_reset_0/proc_sys_reset_0/EXT_LPF/exr_d1 (FF)
  Destination Clock: fpga_0_clk_1_sys_clk_pin rising

  Data Path: fpga_0_rst_1_sys_rst_pin to microblaze_own_IP_III_i/proc_sys_reset_0/proc_sys_reset_0/EXT_LPF/exr_d1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             5   1.218   0.633  fpga_0_rst_1_sys_rst_pin_IBUF (fpga_0_rst_1_sys_rst_pin_IBUF)
     begin scope: 'microblaze_own_IP_III_i'
     begin scope: 'proc_sys_reset_0'
     FDS:S                     0.911          proc_sys_reset_0/EXT_LPF/exr_d1
    ----------------------------------------
    Total                      2.762ns (2.129ns logic, 0.633ns route)
                                       (77.1% logic, 22.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'microblaze_own_IP_III_i/mdm_0/bscan_update1'
  Total number of paths / destination ports: 20 / 20
-------------------------------------------------------------------------
Offset:              4.085ns (Levels of Logic = 3)
  Source:            microblaze_own_IP_III_i/mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:SEL2 (PAD)
  Destination:       microblaze_own_IP_III_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/command_0 (FF)
  Destination Clock: microblaze_own_IP_III_i/mdm_0/bscan_update1 falling

  Data Path: microblaze_own_IP_III_i/mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:SEL2 to microblaze_own_IP_III_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/command_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
    BSCAN_SPARTAN3:SEL2    2   0.000   0.000  mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I (mdm_0/sel)
     begin scope: 'mdm_0/MDM_Core_I1'
     LUT3:I0->O            7   0.704   0.743  Ext_JTAG_SEL11 (N2)
     LUT3:I2->O            8   0.704   0.757  Old_MDM_SEL1 (Old_MDM_SEL)
     FDE_1:CE                  0.555          JTAG_CONTROL_I/command_7
    ----------------------------------------
    Total                      4.085ns (2.585ns logic, 1.500ns route)
                                       (63.3% logic, 36.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'fpga_0_clk_1_sys_clk_pin'
  Total number of paths / destination ports: 1496 / 48
-------------------------------------------------------------------------
Offset:              12.163ns (Levels of Logic = 9)
  Source:            microblaze_own_IP_III_i/pwm_lights_0/pwm_lights_0/USER_LOGIC_I/count_24 (FF)
  Destination:       pwm_lights_0_LEDs_pin<0> (PAD)
  Source Clock:      fpga_0_clk_1_sys_clk_pin rising

  Data Path: microblaze_own_IP_III_i/pwm_lights_0/pwm_lights_0/USER_LOGIC_I/count_24 to pwm_lights_0_LEDs_pin<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              14   0.591   1.175  pwm_lights_0/USER_LOGIC_I/count_24 (pwm_lights_0/USER_LOGIC_I/count<24>)
     LUT2:I0->O            2   0.704   0.451  pwm_lights_0/USER_LOGIC_I/PWM_value<6>54 (pwm_lights_0/USER_LOGIC_I/PWM_value<6>54)
     LUT4:I3->O            1   0.704   0.424  pwm_lights_0/USER_LOGIC_I/PWM_value<6>94_SW0 (N16)
     LUT4:I3->O            1   0.704   0.595  pwm_lights_0/USER_LOGIC_I/PWM_value<6>94 (pwm_lights_0/USER_LOGIC_I/PWM_value<6>)
     LUT2:I0->O            1   0.704   0.000  pwm_lights_0/USER_LOGIC_I/Mcompar_LEDs_cmp_ge0000_lut<6> (pwm_lights_0/USER_LOGIC_I/Mcompar_LEDs_cmp_ge0000_lut<6>)
     MUXCY:S->O            1   0.464   0.000  pwm_lights_0/USER_LOGIC_I/Mcompar_LEDs_cmp_ge0000_cy<6> (pwm_lights_0/USER_LOGIC_I/Mcompar_LEDs_cmp_ge0000_cy<6>)
     MUXCY:CI->O           1   0.459   0.455  pwm_lights_0/USER_LOGIC_I/Mcompar_LEDs_cmp_ge0000_cy<7> (pwm_lights_0/USER_LOGIC_I/LEDs_cmp_ge0000)
     LUT3:I2->O            8   0.704   0.757  pwm_lights_0/USER_LOGIC_I/LEDs<1>1 (LEDs<7>)
     end scope: 'pwm_lights_0'
     end scope: 'microblaze_own_IP_III_i'
     OBUF:I->O                 3.272          pwm_lights_0_LEDs_pin_0_OBUF (pwm_lights_0_LEDs_pin<0>)
    ----------------------------------------
    Total                     12.163ns (8.306ns logic, 3.857ns route)
                                       (68.3% logic, 31.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'microblaze_own_IP_III_i/mdm_0/mdm_0/drck_i'
  Total number of paths / destination ports: 126 / 1
-------------------------------------------------------------------------
Offset:              11.543ns (Levels of Logic = 10)
  Source:            microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/Use_SRL16.The_Cache_Addresses[3].SRL16E_Cache_I (FF)
  Destination:       microblaze_own_IP_III_i/mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:TDO2 (PAD)
  Source Clock:      microblaze_own_IP_III_i/mdm_0/mdm_0/drck_i rising

  Data Path: microblaze_own_IP_III_i/microblaze_0/microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/Use_SRL16.The_Cache_Addresses[3].SRL16E_Cache_I to microblaze_own_IP_III_i/mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:TDO2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     SRL16E:CLK->Q         1   3.706   0.499  microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/Use_SRL16.The_Cache_Addresses[3].SRL16E_Cache_I (microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/tdo_config_word1<4>)
     LUT3:I1->O            1   0.704   0.455  microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/TDO23 (microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/TDO23)
     LUT4:I2->O            1   0.704   0.000  microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/TDO73_F (N323)
     MUXF5:I0->O           1   0.321   0.499  microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/TDO73 (microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/TDO73)
     LUT4:I1->O            1   0.704   0.000  microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/TDO324_SW01 (microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/TDO324_SW0)
     MUXF5:I1->O           1   0.321   0.424  microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/TDO324_SW0_f5 (N247)
     LUT4:I3->O            1   0.704   0.499  microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/TDO324 (DBG_TDO)
     end scope: 'microblaze_0'
     begin scope: 'mdm_0'
     begin scope: 'mdm_0/MDM_Core_I1'
     LUT4:I1->O            1   0.704   0.595  TDO_i81 (TDO_i81)
     LUT4:I0->O            0   0.704   0.000  TDO_i217 (TDO)
     end scope: 'mdm_0/MDM_Core_I1'
    BSCAN_SPARTAN3:TDO2        0.000          mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I
    ----------------------------------------
    Total                     11.543ns (8.572ns logic, 2.971ns route)
                                       (74.3% logic, 25.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'microblaze_own_IP_III_i/mdm_0/bscan_update1'
  Total number of paths / destination ports: 56 / 1
-------------------------------------------------------------------------
Offset:              9.076ns (Levels of Logic = 11)
  Source:            microblaze_own_IP_III_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I (FF)
  Destination:       microblaze_own_IP_III_i/mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:TDO2 (PAD)
  Source Clock:      microblaze_own_IP_III_i/mdm_0/bscan_update1 falling

  Data Path: microblaze_own_IP_III_i/mdm_0/mdm_0/MDM_Core_I1/JTAG_CONTROL_I/FDC_I to microblaze_own_IP_III_i/mdm_0/mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I:TDO2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q           14   0.591   1.175  JTAG_CONTROL_I/FDC_I (JTAG_CONTROL_I/data_cmd)
     LUT2:I0->O            8   0.704   0.792  JTAG_CONTROL_I/Dbg_Reg_En_I<7>1 (Dbg_Reg_En_0<7>)
     end scope: 'mdm_0/MDM_Core_I1'
     end scope: 'mdm_0'
     begin scope: 'microblaze_0'
     LUT4:I2->O            1   0.704   0.455  microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/TDO264 (microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/TDO264)
     LUT4:I2->O            1   0.704   0.000  microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/TDO324_SW01 (microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/TDO324_SW0)
     MUXF5:I1->O           1   0.321   0.424  microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/TDO324_SW0_f5 (N247)
     LUT4:I3->O            1   0.704   0.499  microblaze_0/MicroBlaze_Core_I/Area.Implement_Debug_Logic.Master_Core.Debug_Area/TDO324 (DBG_TDO)
     end scope: 'microblaze_0'
     begin scope: 'mdm_0'
     begin scope: 'mdm_0/MDM_Core_I1'
     LUT4:I1->O            1   0.704   0.595  TDO_i81 (TDO_i81)
     LUT4:I0->O            0   0.704   0.000  TDO_i217 (TDO)
     end scope: 'mdm_0/MDM_Core_I1'
    BSCAN_SPARTAN3:TDO2        0.000          mdm_0/Use_Spartan3.BSCAN_SPARTAN3_I
    ----------------------------------------
    Total                      9.076ns (5.136ns logic, 3.940ns route)
                                       (56.6% logic, 43.4% route)

=========================================================================


Total REAL time to Xst completion: 31.00 secs
Total CPU time to Xst completion: 30.19 secs
 
--> 

Total memory usage is 213908 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :   37 (   0 filtered)