Release 13.2 par O.61xd (nt) Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. ETPCLENOVO:: Thu Dec 08 14:23:18 2011 par -w -intstyle ise -ol high -t 1 microblaze_own_IP_III_top_map.ncd microblaze_own_IP_III_top.ncd microblaze_own_IP_III_top.pcf Constraints file: microblaze_own_IP_III_top.pcf. Loading device for application Rf_Device from file '3s500e.nph' in environment C:\Programme\Xilinx\13.2\ISE_DS\ISE\. "microblaze_own_IP_III_top" is an NCD, version 3.2, device xc3s500e, package fg320, speed -4 vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv INFO:Security:54 - 'xc3s500e' is a WebPack part. WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases. ---------------------------------------------------------------------- Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts) Device speed data version: "PRODUCTION 1.27 2011-06-20". Design Summary Report: Number of External IOBs 63 out of 232 27% Number of External Input IOBs 11 Number of External Input IBUFs 11 Number of LOCed External Input IBUFs 11 out of 11 100% Number of External Output IOBs 33 Number of External Output DIFFMs 1 Number of LOCed External Output DIFFMs 1 out of 1 100% Number of External Output DIFFSs 1 Number of LOCed External Output DIFFSs 1 out of 1 100% Number of External Output IOBs 31 Number of LOCed External Output IOBs 24 out of 31 77% Number of External Bidir IOBs 19 Number of External Bidir IOBs 19 Number of LOCed External Bidir IOBs 19 out of 19 100% Number of BSCANs 1 out of 1 100% Number of BUFGMUXs 5 out of 24 20% Number of DCMs 2 out of 4 50% Number of MULT18X18SIOs 3 out of 20 15% Number of RAMB16s 13 out of 20 65% Number of Slices 2581 out of 4656 55% Number of SLICEMs 251 out of 2328 10% Number of LOCed Slices 62 out of 2581 2% Number of LOCed SLICEMs 41 out of 251 16% Overall effort level (-ol): High Placer effort level (-pl): High Placer cost table entry (-t): 1 Router effort level (-rl): High Starting initial Timing Analysis. REAL time: 5 secs Finished initial Timing Analysis. REAL time: 6 secs Starting Placer Total REAL time at the beginning of Placer: 6 secs Total CPU time at the beginning of Placer: 6 secs Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis (Checksum:f7b9877d) REAL time: 7 secs Phase 2.7 Design Feasibility Check WARNING:Place:837 - Partially locked IO Bus is found. Following components of the bus are not locked: Comp: pwm_lights_0_LEDs_pin<1> Comp: pwm_lights_0_LEDs_pin<2> Comp: pwm_lights_0_LEDs_pin<3> Comp: pwm_lights_0_LEDs_pin<4> Comp: pwm_lights_0_LEDs_pin<5> Comp: pwm_lights_0_LEDs_pin<6> Comp: pwm_lights_0_LEDs_pin<7> WARNING:Place:838 - An IO Bus with more than one IO standard is found. Components associated with this bus are as follows: Comp: pwm_lights_0_LEDs_pin<7> IOSTANDARD = LVCMOS25 Comp: pwm_lights_0_LEDs_pin<6> IOSTANDARD = LVCMOS25 Comp: pwm_lights_0_LEDs_pin<5> IOSTANDARD = LVCMOS25 Comp: pwm_lights_0_LEDs_pin<4> IOSTANDARD = LVCMOS25 Comp: pwm_lights_0_LEDs_pin<3> IOSTANDARD = LVCMOS25 Comp: pwm_lights_0_LEDs_pin<2> IOSTANDARD = LVCMOS25 Comp: pwm_lights_0_LEDs_pin<1> IOSTANDARD = LVCMOS25 Comp: pwm_lights_0_LEDs_pin<0> IOSTANDARD = LVCMOS33 INFO:Place:834 - Only a subset of IOs are locked. Out of 50 IOs, 43 are locked and 7 are not locked. The following is the list of components that are not locked. pwm_lights_0_LEDs_pin<1> NOT LOCKED pwm_lights_0_LEDs_pin<2> NOT LOCKED pwm_lights_0_LEDs_pin<3> NOT LOCKED pwm_lights_0_LEDs_pin<4> NOT LOCKED pwm_lights_0_LEDs_pin<5> NOT LOCKED pwm_lights_0_LEDs_pin<6> NOT LOCKED pwm_lights_0_LEDs_pin<7> NOT LOCKED Rest of the IOs are LOCKED ERROR:Place:207 - Due to SelectIO banking constraints, the IOBs in your design cannot be automatically placed. Each Group of a specific Standard is listed. Standard SSTL2_I (Vref=1.25 Vcco=2.50 Terminate=none) 40 IOs, 40 locked. (0-Inputs, 22-Outputs, 18-Bidirectional) Standard LVCMOS33 (Vref=NR Vcco=3.30 Terminate=none) 14 IOs, 14 locked. (11-Inputs, 2-Outputs, 1-Bidirectional) Standard LVCMOS25 (Vref=NR Vcco=2.50 Terminate=none) 7 IOs, 0 locked. (0-Inputs, 7-Outputs, 0-Bidirectional) Standard DIFF_SSTL2_I (Vref=NR Vcco=2.50 Terminate=none) 2 IOs, 2 locked. (0-Inputs, 2-Outputs, 0-Bidirectional) Bank Summary ____________ If an IOB is placed in a dedicated Vref site, it will be indicated by the word 'Vref' at the end of a summary row. IOBs can be placed in a bank's Vref sites when none of the IOBs in the bank require a Vref site. NR - means Not Required, L - means Locked IOB Bank 0 has 58 pads, 2 (3%) are utilized. +===========================+====+==============+======+======+==============+======+ | Name | IO | Select Std | Vref | Vcco | Pad | Pin | |---------------------------+----+--------------+------+------+--------------+------| | pwm_lights_0_LEDs_pin<0> | O | LVCMOS33 | | 3.30 | PAD45 | F12 | None L | fpga_0_clk_1_sys_clk_pin | I | LVCMOS33 | NR | 3.30 | PAD27 | C9 | None L +===========================+====+==============+======+======+==============+======+ Bank 1 has 58 pads, 8 (13%) are utilized. +===========================+====+==============+======+======+==============+======+ | Name | IO | Select Std | Vref | Vcco | Pad | Pin | |---------------------------+----+--------------+------+------+--------------+------| | fpga_0_DIP_Switches_4Bit_ | I | LVCMOS33 | NR | 3.30 | IPAD108 | N17 | None L | fpga_0_RS232_DCE_TX_pin | O | LVCMOS33 | | 3.30 | PAD107 | M14 | None L | fpga_0_DIP_Switches_4Bit_ | I | LVCMOS33 | NR | 3.30 | IPAD103 | L14 | None L | fpga_0_DIP_Switches_4Bit_ | I | LVCMOS33 | NR | 3.30 | IPAD98 | L13 | None L | fpga_0_rst_1_sys_rst_pin | I | LVCMOS33 | NR | 3.30 | IPAD93 | K17 | None L | fpga_0_DIP_Switches_4Bit_ | I | LVCMOS33 | NR | 3.30 | IPAD83 | H18 | None Vref L | fpga_0_Buttons_4Bit_GPIO_ | I | LVCMOS33 | NR | 3.30 | IPAD73 | H13 | None L | fpga_0_Buttons_4Bit_GPIO_ | I | LVCMOS33 | NR | 3.30 | IPAD64 | D18 | None Vref L +===========================+====+==============+======+======+==============+======+ Bank 2 has 58 pads, 4 (6%) are utilized. +===========================+====+==============+======+======+==============+======+ | Name | IO | Select Std | Vref | Vcco | Pad | Pin | |---------------------------+----+--------------+------+------+--------------+------| | fpga_0_Buttons_4Bit_GPIO_ | I | LVCMOS33 | NR | 3.30 | IPAD171 | V4 | None L | fpga_0_RS232_DCE_RX_pin | I | LVCMOS33 | NR | 3.30 | IPAD158 | R7 | None L | fpga_0_DDR_SDRAM_ddr_dqs_ | IO | LVCMOS33 | NR | 3.30 | PAD128 | P13 | None L | fpga_0_Buttons_4Bit_GPIO_ | I | LVCMOS33 | NR | 3.30 | IPAD119 | V16 | None L +===========================+====+==============+======+======+==============+======+ Bank 3 has 58 pads, 42 (72%) are utilized. +===========================+====+==============+======+======+==============+======+ | Name | IO | Select Std | Vref | Vcco | Pad | Pin | |---------------------------+----+--------------+------+------+--------------+------| | fpga_0_DDR_SDRAM_DDR_RAS_ | O | SSTL2_I | | 2.50 | PAD232 | C1 | None L | fpga_0_DDR_SDRAM_DDR_CAS_ | O | SSTL2_I | | 2.50 | PAD231 | C2 | None L | fpga_0_DDR_SDRAM_DDR_WE_n | O | SSTL2_I | | 2.50 | PAD230 | D1 | None L | fpga_0_DDR_SDRAM_DDR_DQ_p | IO | SSTL2_I | 1.25 | 2.50 | PAD227 | E2 | None L | fpga_0_DDR_SDRAM_DDR_DQ_p | IO | SSTL2_I | 1.25 | 2.50 | PAD226 | E1 | None L | fpga_0_DDR_SDRAM_DDR_Addr | O | SSTL2_I | | 2.50 | PAD225 | F4 | None L | fpga_0_DDR_SDRAM_DDR_DQ_p | IO | SSTL2_I | 1.25 | 2.50 | PAD223 | F1 | None L | fpga_0_DDR_SDRAM_DDR_DQ_p | IO | SSTL2_I | 1.25 | 2.50 | PAD222 | F2 | None L | fpga_0_DDR_SDRAM_DDR_DQS_ | IO | SSTL2_I | 1.25 | 2.50 | PAD221 | G3 | None L | fpga_0_DDR_SDRAM_DDR_DQ_p | IO | SSTL2_I | 1.25 | 2.50 | PAD218 | G6 | None L | fpga_0_DDR_SDRAM_DDR_DQ_p | IO | SSTL2_I | 1.25 | 2.50 | PAD217 | G5 | None L | fpga_0_DDR_SDRAM_DDR_DQ_p | IO | SSTL2_I | 1.25 | 2.50 | PAD216 | H6 | None L | fpga_0_DDR_SDRAM_DDR_DQ_p | IO | SSTL2_I | 1.25 | 2.50 | PAD215 | H5 | None L | fpga_0_DDR_SDRAM_DDR_Addr | O | SSTL2_I | | 2.50 | PAD213 | H4 | None L | fpga_0_DDR_SDRAM_DDR_Addr | O | SSTL2_I | | 2.50 | PAD212 | H3 | None L | fpga_0_DDR_SDRAM_DDR_Addr | O | SSTL2_I | | 2.50 | PAD211 | H2 | None L | fpga_0_DDR_SDRAM_DDR_Addr | O | SSTL2_I | | 2.50 | PAD210 | H1 | None L | fpga_0_DDR_SDRAM_DDR_Clk_ | O | DIFF_SSTL2_I | | 2.50 | PAD208 | J5 | None L | fpga_0_DDR_SDRAM_DDR_Clk_ | O | DIFF_SSTL2_I | | 2.50 | PAD207 | J4 | None L | fpga_0_DDR_SDRAM_DDR_DM_p | O | SSTL2_I | | 2.50 | PAD206 | J1 | None L | fpga_0_DDR_SDRAM_DDR_DM_p | O | SSTL2_I | | 2.50 | PAD205 | J2 | None L | fpga_0_DDR_SDRAM_DDR_CE_p | O | SSTL2_I | | 2.50 | PAD203 | K3 | None L | fpga_0_DDR_SDRAM_DDR_CS_n | O | SSTL2_I | | 2.50 | PAD202 | K4 | None L | fpga_0_DDR_SDRAM_DDR_Bank | O | SSTL2_I | | 2.50 | PAD201 | K6 | None L | fpga_0_DDR_SDRAM_DDR_Bank | O | SSTL2_I | | 2.50 | PAD200 | K5 | None L | fpga_0_DDR_SDRAM_DDR_DQ_p | IO | SSTL2_I | 1.25 | 2.50 | PAD198 | L1 | None L | fpga_0_DDR_SDRAM_DDR_DQ_p | IO | SSTL2_I | 1.25 | 2.50 | PAD197 | L2 | None L | fpga_0_DDR_SDRAM_DDR_DQ_p | IO | SSTL2_I | 1.25 | 2.50 | PAD196 | L3 | None L | fpga_0_DDR_SDRAM_DDR_DQ_p | IO | SSTL2_I | 1.25 | 2.50 | PAD195 | L4 | None L | fpga_0_DDR_SDRAM_DDR_DQS_ | IO | SSTL2_I | 1.25 | 2.50 | PAD193 | L6 | None L | fpga_0_DDR_SDRAM_DDR_DQ_p | IO | SSTL2_I | 1.25 | 2.50 | PAD191 | M4 | None L | fpga_0_DDR_SDRAM_DDR_DQ_p | IO | SSTL2_I | 1.25 | 2.50 | PAD190 | M3 | None L | fpga_0_DDR_SDRAM_DDR_DQ_p | IO | SSTL2_I | 1.25 | 2.50 | PAD188 | M5 | None L | fpga_0_DDR_SDRAM_DDR_DQ_p | IO | SSTL2_I | 1.25 | 2.50 | PAD187 | M6 | None L | fpga_0_DDR_SDRAM_DDR_Addr | O | SSTL2_I | | 2.50 | PAD186 | N4 | None L | fpga_0_DDR_SDRAM_DDR_Addr | O | SSTL2_I | | 2.50 | PAD185 | N5 | None L | fpga_0_DDR_SDRAM_DDR_Addr | O | SSTL2_I | | 2.50 | PAD183 | P2 | None L | fpga_0_DDR_SDRAM_DDR_Addr | O | SSTL2_I | | 2.50 | PAD182 | P1 | None L | fpga_0_DDR_SDRAM_DDR_Addr | O | SSTL2_I | | 2.50 | PAD179 | R3 | None L | fpga_0_DDR_SDRAM_DDR_Addr | O | SSTL2_I | | 2.50 | PAD178 | R2 | None L | fpga_0_DDR_SDRAM_DDR_Addr | O | SSTL2_I | | 2.50 | PAD177 | T2 | None L | fpga_0_DDR_SDRAM_DDR_Addr | O | SSTL2_I | | 2.50 | PAD176 | T1 | None L +===========================+====+==============+======+======+==============+======+ Phase 2.7 Design Feasibility Check (Checksum:f7b9877d) REAL time: 7 secs Total REAL time to Placer completion: 7 secs Total CPU time to Placer completion: 7 secs Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ |microblaze_own_IP_II | | | | | | | I_i/clk_50_0000MHz* | Global| No | 1155 | 0.000 | | +---------------------+--------------+------+------+------------+-------------+ |microblaze_own_IP_II | | | | | | |I_i/clk_100_0000MHzD | | | | | | | CM0* | Global| No | 505 | 0.000 | | +---------------------+--------------+------+------+------------+-------------+ |microblaze_own_IP_II | | | | | | |I_i/mdm_0/Dbg_Clk_1* | | | | | | | | Global| No | 113 | 0.000 | | +---------------------+--------------+------+------+------------+-------------+ |microblaze_own_IP_II | | | | | | |I_i/clk_100_0000MHz9 | | | | | | | 0DCM0* | Global| No | 143 | 0.000 | | +---------------------+--------------+------+------+------------+-------------+ |microblaze_own_IP_II | | | | | | |I_i/clock_generator_ | | | | | | |0/clock_generator_0/ | | | | | | | SIG_DCM1_CLK2X_BUF* | Global| No | 4 | 0.000 | | +---------------------+--------------+------+------+------------+-------------+ |fpga_0_clk_1_sys_clk | | | | | | | _pin_IBUFG* | Local| | 4 | 0.000 | | +---------------------+--------------+------+------+------------+-------------+ |microblaze_own_IP_II | | | | | | |I_i/mdm_0/Dbg_Update | | | | | | | _1* | Local| | 27 | 0.000 | | +---------------------+--------------+------+------+------------+-------------+ |microblaze_own_IP_II | | | | | | |I_i/DDR_SDRAM/DDR_SD | | | | | | |RAM/mpmc_core_0/gen_ | | | | | | |s3_ddr_phy.mpmc_phy_ | | | | | | |if_0/data_path/dqs_d | | | | | | | elayed_col1<0>* | Local| | 11 | 0.336 | | +---------------------+--------------+------+------+------------+-------------+ |microblaze_own_IP_II | | | | | | |I_i/DDR_SDRAM/DDR_SD | | | | | | |RAM/mpmc_core_0/gen_ | | | | | | |s3_ddr_phy.mpmc_phy_ | | | | | | |if_0/data_path/dqs_d | | | | | | | elayed_col0<1>* | Local| | 11 | 0.476 | | +---------------------+--------------+------+------+------------+-------------+ |microblaze_own_IP_II | | | | | | |I_i/DDR_SDRAM/DDR_SD | | | | | | |RAM/mpmc_core_0/gen_ | | | | | | |s3_ddr_phy.mpmc_phy_ | | | | | | |if_0/data_path/dqs_d | | | | | | | elayed_col1<1>* | Local| | 11 | 0.476 | | +---------------------+--------------+------+------+------------+-------------+ |microblaze_own_IP_II | | | | | | |I_i/DDR_SDRAM/DDR_SD | | | | | | |RAM/mpmc_core_0/gen_ | | | | | | |s3_ddr_phy.mpmc_phy_ | | | | | | |if_0/data_path/dqs_d | | | | | | | elayed_col0<0>* | Local| | 11 | 0.336 | | +---------------------+--------------+------+------+------------+-------------+ * Some of the Clock networks are NOT completely routed * Net Skew is the difference between the minimum and maximum routing only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. * The fanout is the number of component pins not the individual BEL loads, for example SLICE loads not FF loads. Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Generating Pad Report. 4905 signals are not completely routed. See the microblaze_own_IP_III_top.unroutes file for a list of all unrouted signals. WARNING:Par:100 - Design is not completely routed. There are 4905 signals that are not completely routed in this design. See the "microblaze_own_IP_III_top.unroutes" file for a list of all unrouted signals. Check for other warnings in your PAR report that might indicate why these nets are unroutable. These nets can also be evaluated in FPGA Editor by selecting "Unrouted Nets" in the List Window. Total REAL time to PAR completion: 12 secs Total CPU time to PAR completion: 12 secs Peak Memory Usage: 195 MB Placement: Completed - errors found. Routing: Completed - errors found. Timing: Completed - No errors found. Number of error messages: 1 Number of warning messages: 4 Number of info messages: 1 Writing design to file microblaze_own_IP_III_top.ncd PAR done!