Acronym |
Brief Description |
CLK |
Clock |
DG |
DataGATE |
DGE |
DataGATE Enable |
GCK0 |
Global Clock 0 |
GCK1 |
Global Clock 1 |
GCK2 |
Global Clock 2 |
GND |
Ground |
GSR |
Global Set/Reset |
GTS0 |
Global Output Enable 0 |
GTS1 |
Global Output Enable 1 |
GTS2 |
Global Output Enable 2 |
GTS3 |
Global Output Enable 3 |
HSTL |
High speed Tranciever Logic |
I/O |
Input/Output |
INIT |
Initial state |
ISP |
In system programmable |
JTAG |
Joint Test Action Group |
KPR |
Unused I/O with weak keeper |
NC |
No Connects |
PGND |
Programmable ground pin |
PROHIBITED |
User reserved pin |
R |
Reset |
S |
Set |
-S |
Schmitt |
TCK |
Test clock |
TDI |
Test data input |
TDO |
Test data output |
TIE |
Unused I/O floating |
TMS |
Test mode select |
VAUX |
JTAG Power Supply Voltage |
LVCMOS15 |
Low Voltage CMOS 1.5 Volts |
LVCMOS18 |
Low Voltage CMOS 1.8 Volts |
LVCMOS25 |
Low Voltage CMOS 2.5 Volts |
LVCMOS33 |
Low Voltage CMOS 2.5 to 3.3 Volts |
LVTTL |
Low Voltage TTL 3.3 Volts |
SCHMITT15IN |
Schmitt Trigger 1.5 Volt input |
SSTL |
Stub Switched Tranceiver Logic |
VCCIO |
Input/Output Supply Voltage |
VCCIO-1.5 |
Power external I/O |
VCCIO-1.8 |
Power external I/O |
VCCIO-2.5 |
Power external I/O |
VCCIO-3.3 |
Power external I/O |
VCC |
Power internal |
VREF-[iostd] |
Reference voltage for indicated I/O standard |
*VREF-[iostd] |
Reference voltage pin selected by software |
WPU |
Weak Pull Up |
WPD |
Weak Pull Down |