Logic

Signal Name Total Pterms Total Inputs Function Block Macrocell Slew Rate Bank Pin Number Pin Type Pin Use Reg Use I/O Std I/O Style Reg Init State
CNT<9> 2 10 FB1 MC1       (b) (b) TDFF/S     SET
CNT<8> 2 9 FB1 MC2       (b) (b) TDFF/S     SET
CNT<15> 2 16 FB1 MC3   2 143 I/O/GSR GSR TDFF/S   KPR SET
CNT<14> 2 15 FB1 MC4   2 142 I/O (b) TDFF/S     SET
CNT<7> 2 8 FB1 MC5       (b) (b) TDFF/S     SET
CNT<13> 2 14 FB1 MC6   2 140 I/O (b) TDFF/S     SET
CNT<6> 2 7 FB1 MC7       (b) (b) TDFF/S     SET
CNT<5> 2 6 FB1 MC8       (b) (b) TDFF/S     SET
CNT<4> 2 5 FB1 MC9       (b) (b) TDFF/S     SET
CNT<3> 2 4 FB1 MC10       (b) (b) TDFF/S     SET
CNT<2> 2 3 FB1 MC11       (b) (b) TDFF/S     SET
CNT<12> 2 13 FB1 MC12   2 139 I/O (b) TDFF/S     SET
CNT<11> 2 12 FB1 MC13   2 138 I/O (b) TDFF/S     SET
CNT<10> 2 11 FB1 MC14   2 137 I/O (b) TDFF/S     SET
CNT<1> 2 2 FB1 MC15       (b) (b) TDFF/S     SET
CNT<0> 1 1 FB1 MC16       (b) (b) TDFF/S     SET
Dbg_4<1> 2 5 FB10 MC1   2 111 I/O IR DDEFF   KPR  
Dbg_4<0> 2 5 FB10 MC2   2 110 I/O IR DDEFF   KPR  
Dbg_4<3> 2 5 FB10 MC3   2 107 I/O IR DDEFF   KPR  
Dbg_4<2> 2 5 FB10 MC4   2 106 I/O IR DDEFF   KPR  
Dbg_3<0> 2 5 FB10 MC5   2 105 I/O IR DDEFF   KPR  
Dig<0> 1 2 FB11 MC13 FAST 2 126 I/O O   LVCMOS18    
Dig<1> 1 2 FB11 MC14 FAST 2 128 I/O O   LVCMOS18    
Dig<2> 1 2 FB11 MC15 FAST 2 129 I/O O   LVCMOS18    
Dig<3> 1 2 FB11 MC16 FAST 2 130 I/O O   LVCMOS18    
LEDs<0> 1 1 FB14 MC4 FAST 1 69 I/O O   LVCMOS18    
LEDs<1> 1 1 FB14 MC6 FAST 1 68 I/O O   LVCMOS18    
LEDs<2> 3 6 FB14 MC13 FAST 1 66 I/O O DDFF LVCMOS18   RESET
LEDs<3> 3 6 FB14 MC14 FAST 1 64 I/O O DDFF LVCMOS18   RESET
Seg<6> 9 13 FB14 MC16 FAST 1 61 I/O O   LVCMOS18    
Seg<2> 7 13 FB16 MC5 FAST 1 60 I/O O   LVCMOS18    
Seg<3> 7 15 FB16 MC11 FAST 1 58 I/O O   LVCMOS18    
Seg<4> 6 12 FB16 MC12 FAST 1 57 I/O O   LVCMOS18    
Seg<0> 6 12 FB16 MC13 FAST 1 56 I/O O   LVCMOS18    
Seg<5> 9 14 FB16 MC15 FAST 1 54 I/O O   LVCMOS18    
Seg<1> 8 14 FB16 MC16 FAST 1 53 I/O O   LVCMOS18    
N_PZ_255 1 3 FB2 MC7       (b) (b)        
Dbg_1<0> 5 6 FB2 MC8       (b) (b) TDFF     RESET
Dbg_1<1> 3 5 FB2 MC9       (b) (b) DDFF     RESET
Dbg_1<2> 3 4 FB2 MC10       (b) (b) DDFF     RESET
N_PZ_279 3 13 FB2 MC11       (b) (b)        
N_PZ_256 3 13 FB2 MC16       (b) (b)        
RD 3 6 FB4 MC3 FAST 2 13 I/O O DDFF/S LVCMOS18   SET
Dbg_3<3> 2 5 FB4 MC6   2 16 I/O IR DDEFF   KPR  
Dbg_3<2> 2 5 FB4 MC12   2 17 I/O IR DDEFF   KPR  
Dbg_3<1> 2 5 FB4 MC14   2 18 I/O IR DDEFF   KPR  
WR 0 0 FB8 MC1 FAST 1 44 I/O O   LVCMOS18    
OE 3 6 FB8 MC3 FAST 1 46 I/O O DDFF/S LVCMOS18   SET