Timing Report

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Design Name Main
Device, Speed (SpeedFile Version) XC2C256, -7 (14.0 Advance Product Specification)
Date Created Fri Mar 02 11:35:59 2012
Created By Timing Report Generator: version O.76xd
Copyright Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 14.200 ns.
Max. Clock Frequency (fSYSTEM) 70.423 MHz.
Limited by Dual-Edge Triggered Register Cycle Time for CLK
Clock to Setup (tCYC) 7.100 ns.
Pad to Pad Delay (tPD) 7.000 ns.
Setup to Clock at the Pad (tSU) 3.300 ns.
Clock Pad to Output Pad Delay (tCO) 11.300 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
AUTO_TS_F2F 0.0 7.1 161 161
AUTO_TS_P2P 0.0 11.3 17 17
AUTO_TS_P2F 0.0 6.0 23 23
AUTO_TS_F2P 0.0 8.6 103 103


Constraint: TS1000

Description: PERIOD:PERIOD_CLK:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
Dbg_1<2>.Q to FIFOReadStatus_FSM_FFd5.D 0.000 7.100 -7.100
Dbg_1<2>.Q to LEDs<2>.D 0.000 7.100 -7.100
Dbg_1<2>.Q to LEDs<3>.D 0.000 7.100 -7.100


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CLK to Seg<0> 0.000 11.300 -11.300
CLK to Seg<1> 0.000 11.300 -11.300
CLK to Seg<2> 0.000 11.300 -11.300


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
RXF to Dbg_1<0>.D 0.000 6.000 -6.000
RXF to Dbg_1<1>.D 0.000 6.000 -6.000
RXF to FIFOReadStatus_FSM_FFd2.D 0.000 6.000 -6.000


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CNT<14>.Q to Seg<0> 0.000 8.600 -8.600
CNT<14>.Q to Seg<1> 0.000 8.600 -8.600
CNT<14>.Q to Seg<2> 0.000 8.600 -8.600



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
CLK 70.423 Limited by Dual-Edge Triggered Register Cycle Time for CLK

Setup/Hold Times for Clocks

Setup/Hold Times for Clock CLK
Source Pad Setup to clk (edge) Hold to clk (edge)
FIFO_Data<0> 3.000 0.000
FIFO_Data<1> 3.000 0.000
FIFO_Data<2> 3.000 0.000
FIFO_Data<3> 3.000 0.000
FIFO_Data<4> 3.000 0.000
FIFO_Data<5> 3.000 0.000
FIFO_Data<6> 3.000 0.000
FIFO_Data<7> 3.000 0.000
RXF 3.300 0.000


Clock to Pad Timing

Clock CLK to Pad
Destination Pad Clock (edge) to Pad
Seg<0> 11.300
Seg<1> 11.300
Seg<2> 11.300
Seg<3> 11.300
Seg<4> 11.300
Seg<5> 11.300
Seg<6> 11.300
Dig<0> 10.800
Dig<1> 10.800
Dig<2> 10.800
Dig<3> 10.800
LEDs<2> 6.000
LEDs<3> 6.000
OE 6.000
RD 6.000


Clock to Setup Times for Clocks

Clock to Setup for clock CLK
Source Destination Delay
Dbg_1<2>.Q FIFOReadStatus_FSM_FFd5.D 7.100
Dbg_1<2>.Q LEDs<2>.D 7.100
Dbg_1<2>.Q LEDs<3>.D 7.100
Dbg_1<2>.Q OE.D 7.100
Dbg_1<2>.Q RD.D 7.100
FIFOReadStatus_FSM_FFd2.Q Dbg_1<0>.D 7.100
FIFOReadStatus_FSM_FFd2.Q Dbg_1<1>.D 7.100
FIFOReadStatus_FSM_FFd2.Q FIFOReadStatus_FSM_FFd2.D 7.100
FIFOReadStatus_FSM_FFd2.Q LEDs<2>.D 7.100
FIFOReadStatus_FSM_FFd2.Q LEDs<3>.D 7.100
FIFOReadStatus_FSM_FFd2.Q OE.D 7.100
FIFOReadStatus_FSM_FFd2.Q RD.D 7.100
FIFOReadStatus_FSM_FFd3.Q Dbg_1<0>.D 7.100
FIFOReadStatus_FSM_FFd3.Q Dbg_1<1>.D 7.100
FIFOReadStatus_FSM_FFd3.Q FIFOReadStatus_FSM_FFd2.D 7.100
FIFOReadStatus_FSM_FFd3.Q LEDs<2>.D 7.100
FIFOReadStatus_FSM_FFd3.Q OE.D 7.100
FIFOReadStatus_FSM_FFd4.Q Dbg_1<1>.D 7.100
FIFOReadStatus_FSM_FFd4.Q LEDs<3>.D 7.100
FIFOReadStatus_FSM_FFd4.Q RD.D 7.100
FIFOReadStatus_FSM_FFd5.Q Dbg_1<0>.D 7.100
FIFOReadStatus_FSM_FFd5.Q FIFOReadStatus_FSM_FFd5.D 7.100
FIFOReadStatus_FSM_FFd5.Q LEDs<2>.D 7.100
FIFOReadStatus_FSM_FFd5.Q LEDs<3>.D 7.100
FIFOReadStatus_FSM_FFd5.Q OE.D 7.100
FIFOReadStatus_FSM_FFd5.Q RD.D 7.100
OE.Q LEDs<2>.D 7.100
OE.Q OE.D 7.100
RD.Q LEDs<3>.D 7.100
RD.Q RD.D 7.100
FIFOReadStatus_FSM_FFd2.Q Dbg_3<0>.CE 6.900
FIFOReadStatus_FSM_FFd2.Q Dbg_3<1>.CE 6.900
FIFOReadStatus_FSM_FFd2.Q Dbg_3<2>.CE 6.900
FIFOReadStatus_FSM_FFd2.Q Dbg_3<3>.CE 6.900
FIFOReadStatus_FSM_FFd2.Q Dbg_4<0>.CE 6.900
FIFOReadStatus_FSM_FFd2.Q Dbg_4<1>.CE 6.900
FIFOReadStatus_FSM_FFd2.Q Dbg_4<2>.CE 6.900
FIFOReadStatus_FSM_FFd2.Q Dbg_4<3>.CE 6.900
CNT<0>.Q CNT<10>.D 6.600
CNT<0>.Q CNT<11>.D 6.600
CNT<0>.Q CNT<12>.D 6.600
CNT<0>.Q CNT<13>.D 6.600
CNT<0>.Q CNT<14>.D 6.600
CNT<0>.Q CNT<15>.D 6.600
CNT<0>.Q CNT<1>.D 6.600
CNT<0>.Q CNT<2>.D 6.600
CNT<0>.Q CNT<3>.D 6.600
CNT<0>.Q CNT<4>.D 6.600
CNT<0>.Q CNT<5>.D 6.600
CNT<0>.Q CNT<6>.D 6.600
CNT<0>.Q CNT<7>.D 6.600
CNT<0>.Q CNT<8>.D 6.600
CNT<0>.Q CNT<9>.D 6.600
CNT<10>.Q CNT<11>.D 6.600
CNT<10>.Q CNT<12>.D 6.600
CNT<10>.Q CNT<13>.D 6.600
CNT<10>.Q CNT<14>.D 6.600
CNT<10>.Q CNT<15>.D 6.600
CNT<11>.Q CNT<12>.D 6.600
CNT<11>.Q CNT<13>.D 6.600
CNT<11>.Q CNT<14>.D 6.600
CNT<11>.Q CNT<15>.D 6.600
CNT<12>.Q CNT<13>.D 6.600
CNT<12>.Q CNT<14>.D 6.600
CNT<12>.Q CNT<15>.D 6.600
CNT<13>.Q CNT<14>.D 6.600
CNT<13>.Q CNT<15>.D 6.600
CNT<14>.Q CNT<15>.D 6.600
CNT<1>.Q CNT<10>.D 6.600
CNT<1>.Q CNT<11>.D 6.600
CNT<1>.Q CNT<12>.D 6.600
CNT<1>.Q CNT<13>.D 6.600
CNT<1>.Q CNT<14>.D 6.600
CNT<1>.Q CNT<15>.D 6.600
CNT<1>.Q CNT<2>.D 6.600
CNT<1>.Q CNT<3>.D 6.600
CNT<1>.Q CNT<4>.D 6.600
CNT<1>.Q CNT<5>.D 6.600
CNT<1>.Q CNT<6>.D 6.600
CNT<1>.Q CNT<7>.D 6.600
CNT<1>.Q CNT<8>.D 6.600
CNT<1>.Q CNT<9>.D 6.600
CNT<2>.Q CNT<10>.D 6.600
CNT<2>.Q CNT<11>.D 6.600
CNT<2>.Q CNT<12>.D 6.600
CNT<2>.Q CNT<13>.D 6.600
CNT<2>.Q CNT<14>.D 6.600
CNT<2>.Q CNT<15>.D 6.600
CNT<2>.Q CNT<3>.D 6.600
CNT<2>.Q CNT<4>.D 6.600
CNT<2>.Q CNT<5>.D 6.600
CNT<2>.Q CNT<6>.D 6.600
CNT<2>.Q CNT<7>.D 6.600
CNT<2>.Q CNT<8>.D 6.600
CNT<2>.Q CNT<9>.D 6.600
CNT<3>.Q CNT<10>.D 6.600
CNT<3>.Q CNT<11>.D 6.600
CNT<3>.Q CNT<12>.D 6.600
CNT<3>.Q CNT<13>.D 6.600
CNT<3>.Q CNT<14>.D 6.600
CNT<3>.Q CNT<15>.D 6.600
CNT<3>.Q CNT<4>.D 6.600
CNT<3>.Q CNT<5>.D 6.600
CNT<3>.Q CNT<6>.D 6.600
CNT<3>.Q CNT<7>.D 6.600
CNT<3>.Q CNT<8>.D 6.600
CNT<3>.Q CNT<9>.D 6.600
CNT<4>.Q CNT<10>.D 6.600
CNT<4>.Q CNT<11>.D 6.600
CNT<4>.Q CNT<12>.D 6.600
CNT<4>.Q CNT<13>.D 6.600
CNT<4>.Q CNT<14>.D 6.600
CNT<4>.Q CNT<15>.D 6.600
CNT<4>.Q CNT<5>.D 6.600
CNT<4>.Q CNT<6>.D 6.600
CNT<4>.Q CNT<7>.D 6.600
CNT<4>.Q CNT<8>.D 6.600
CNT<4>.Q CNT<9>.D 6.600
CNT<5>.Q CNT<10>.D 6.600
CNT<5>.Q CNT<11>.D 6.600
CNT<5>.Q CNT<12>.D 6.600
CNT<5>.Q CNT<13>.D 6.600
CNT<5>.Q CNT<14>.D 6.600
CNT<5>.Q CNT<15>.D 6.600
CNT<5>.Q CNT<6>.D 6.600
CNT<5>.Q CNT<7>.D 6.600
CNT<5>.Q CNT<8>.D 6.600
CNT<5>.Q CNT<9>.D 6.600
CNT<6>.Q CNT<10>.D 6.600
CNT<6>.Q CNT<11>.D 6.600
CNT<6>.Q CNT<12>.D 6.600
CNT<6>.Q CNT<13>.D 6.600
CNT<6>.Q CNT<14>.D 6.600
CNT<6>.Q CNT<15>.D 6.600
CNT<6>.Q CNT<7>.D 6.600
CNT<6>.Q CNT<8>.D 6.600
CNT<6>.Q CNT<9>.D 6.600
CNT<7>.Q CNT<10>.D 6.600
CNT<7>.Q CNT<11>.D 6.600
CNT<7>.Q CNT<12>.D 6.600
CNT<7>.Q CNT<13>.D 6.600
CNT<7>.Q CNT<14>.D 6.600
CNT<7>.Q CNT<15>.D 6.600
CNT<7>.Q CNT<8>.D 6.600
CNT<7>.Q CNT<9>.D 6.600
CNT<8>.Q CNT<10>.D 6.600
CNT<8>.Q CNT<11>.D 6.600
CNT<8>.Q CNT<12>.D 6.600
CNT<8>.Q CNT<13>.D 6.600
CNT<8>.Q CNT<14>.D 6.600
CNT<8>.Q CNT<15>.D 6.600
CNT<8>.Q CNT<9>.D 6.600
CNT<9>.Q CNT<10>.D 6.600
CNT<9>.Q CNT<11>.D 6.600
CNT<9>.Q CNT<12>.D 6.600
CNT<9>.Q CNT<13>.D 6.600
CNT<9>.Q CNT<14>.D 6.600
CNT<9>.Q CNT<15>.D 6.600
FIFOReadStatus_FSM_FFd2.Q Dbg_1<2>.D 6.600
FIFOReadStatus_FSM_FFd4.Q FIFOReadStatus_FSM_FFd3.D 6.600
FIFOReadStatus_FSM_FFd5.Q FIFOReadStatus_FSM_FFd4.D 6.600


Pad to Pad List

Source Pad Destination Pad Delay
RXF LEDs<1> 7.000
TXE LEDs<0> 7.000



Number of paths analyzed: 304
Number of Timing errors: 304
Analysis Completed: Fri Mar 02 11:35:59 2012