Filter Project Status (05/30/2012 - 14:52:28)
Project File: Filter.xise Parser Errors: No Errors
Module Name: Filter Implementation State: Synthesized (Failed)
Target Device: xc3s400-4fg456
  • Errors:
 
Product Version:ISE 13.1
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 333 7,168 4%  
Number of 4 input LUTs 231 7,168 3%  
Number of occupied Slices 234 3,584 6%  
    Number of Slices containing only related logic 234 234 100%  
    Number of Slices containing unrelated logic 0 234 0%  
Total Number of 4 input LUTs 276 7,168 3%  
    Number used as logic 135      
    Number used as a route-thru 45      
    Number used as Shift registers 96      
Number of bonded IOBs 31 264 11%  
Number of MULT18X18s 1 16 6%  
Number of BUFGMUXs 1 8 12%  
Average Fanout of Non-Clock Nets 2.14      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMi 30. Mai 14:28:06 2012   
Translation ReportCurrentMi 30. Mai 14:28:09 2012029 Warnings (0 new)0
Map ReportCurrentMi 30. Mai 14:28:12 2012004 Infos (0 new)
Place and Route ReportCurrentMi 30. Mai 14:28:30 2012003 Infos (0 new)
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing ReportCurrentMi 30. Mai 14:28:33 2012005 Infos (0 new)
Bitgen ReportCurrentMi 30. Mai 14:28:45 2012001 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateMi 30. Mai 14:51:33 2012
WebTalk ReportOut of DateMi 30. Mai 14:28:45 2012
WebTalk Log FileOut of DateMi 30. Mai 14:28:49 2012

Date Generated: 05/30/2012 - 14:52:28