Project Statistics |
PROP_Enable_Message_Filtering=false |
PROP_FitterReportFormat=HTML |
PROP_LastAppliedGoal=Balanced |
PROP_LastAppliedStrategy=Xilinx Default (unlocked) |
PROP_ManualCompileOrderImp=false |
PROP_PropSpecInProjFile=Store non-default values only |
PROP_SelectedInstanceHierarchicalPath=/Filter/FIR1 |
PROP_Simulator=ISim (VHDL/Verilog) |
PROP_SynthTopFile=changed |
PROP_Top_Level_Module_Type=HDL |
PROP_UseSmartGuide=false |
PROP_UserConstraintEditorPreference=Text Editor |
PROP_intProjectCreationTimestamp=2012-05-30T14:13:14 |
PROP_intWbtProjectID=6DB7B94D27BA4AED9F0BAE2D7C334FC8 |
PROP_intWbtProjectIteration=2 |
PROP_intWorkingDirLocWRTProjDir=Same |
PROP_intWorkingDirUsed=No |
PROP_selectedSimRootSourceNode_behav=work.fir_compiler_v5_0 |
PROP_AutoTop=true |
PROP_DevFamily=Spartan3 |
PROP_DevDevice=xc3s400 |
PROP_DevFamilyPMName=spartan3 |
PROP_DevPackage=fg456 |
PROP_Synthesis_Tool=XST (VHDL/Verilog) |
PROP_DevSpeed=-4 |
PROP_PreferredLanguage=VHDL |
FILE_NGC=1 |
FILE_VHDL=1 |