Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:13.1 (WebPack) - O.40d Target Family: Spartan3
OS Platform: NT Target Device: xc3s400
Project ID (random number) b155235a3c634e1c84dd88ca68d75c35.6DB7B94D27BA4AED9F0BAE2D7C334FC8.2 Target Package: fg456
Registration ID 205938264_0_0_812 Target Speed: -4
Date Generated 2012-05-30T14:28:45 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 32-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM)2 Duo CPU E8400 @ 3.00GHz CPU Speed 2997 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=31
  • AGG_IO=31
  • AGG_SLICE=234
  • NUM_4_INPUT_LUT=276
  • NUM_BONDED_IOB=31
  • NUM_BUFGMUX=1
  • NUM_CYMUX=134
  • NUM_LUT_RT=45
  • NUM_MULT18X18=1
  • NUM_MULTAND=36
  • NUM_SHIFT=96
  • NUM_SLICEL=171
  • NUM_SLICEM=63
  • NUM_SLICE_FF=333
  • NUM_XOR=115
  • Xilinx Core fir_compiler_v5_0, Xilinx CORE Generator 13.1=1
NetStatistics
  • NumNets_Active=478
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMDUMMY=36
  • NumNodesOfType_Active_CLKPIN=220
  • NumNodesOfType_Active_CNTRLPIN=42
  • NumNodesOfType_Active_DOUBLE=865
  • NumNodesOfType_Active_DUMMY=573
  • NumNodesOfType_Active_DUMMYESC=17
  • NumNodesOfType_Active_GLOBAL=55
  • NumNodesOfType_Active_HFULLHEX=2
  • NumNodesOfType_Active_HUNIHEX=19
  • NumNodesOfType_Active_INPUT=886
  • NumNodesOfType_Active_IOBOUTPUT=17
  • NumNodesOfType_Active_OMUX=485
  • NumNodesOfType_Active_OUTPUT=430
  • NumNodesOfType_Active_PREBXBY=202
  • NumNodesOfType_Active_VFULLHEX=36
  • NumNodesOfType_Active_VLONG=6
  • NumNodesOfType_Active_VUNIHEX=53
  • NumNodesOfType_Vcc_CNTRLPIN=37
  • NumNodesOfType_Vcc_DUMMY=36
  • NumNodesOfType_Vcc_INPUT=41
  • NumNodesOfType_Vcc_PREBXBY=5
  • NumNodesOfType_Vcc_VCCOUT=34
SiteStatistics
  • IOB-DIFFM=15
  • IOB-DIFFS=13
  • SLICEL-SLICEM=88
SiteSummary
  • BUFGMUX=1
  • BUFGMUX_GCLKMUX=1
  • BUFGMUX_GCLK_BUFFER=1
  • IOB=31
  • IOB_INBUF=17
  • IOB_OUTBUF=14
  • IOB_PAD=31
  • MULT18X18=1
  • MULT18X18_BLACKBOX=1
  • SLICEL=171
  • SLICEL_C1VDD=3
  • SLICEL_C2VDD=1
  • SLICEL_CYMUXF=73
  • SLICEL_CYMUXG=61
  • SLICEL_F=92
  • SLICEL_FAND=18
  • SLICEL_FFX=88
  • SLICEL_FFY=148
  • SLICEL_G=88
  • SLICEL_GAND=18
  • SLICEL_GNDF=27
  • SLICEL_GNDG=26
  • SLICEL_VDDG=1
  • SLICEL_XORF=58
  • SLICEL_XORG=57
  • SLICEM=63
  • SLICEM_F=33
  • SLICEM_FFX=34
  • SLICEM_FFY=63
  • SLICEM_G=63
  • SLICEM_WSGEN=63
 
Configuration Data
BUFGMUX
  • S=[S_INV:1] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:1]
  • S=[S_INV:1] [S:0]
IOB
  • O1=[O1_INV:0] [O1:14]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:14]
IOB_PAD
  • DRIVEATTRBOX=[12:14]
  • IOATTRBOX=[LVCMOS25:31]
  • SLEW=[SLOW:14]
MULT18X18
  • CE=[CE:1] [CE_INV:0]
  • CLK=[CLK:1] [CLK_INV:0]
  • RST=[RST:1] [RST_INV:0]
MULT18X18_BLACKBOX
  • CE=[CE:1] [CE_INV:0]
  • CLK=[CLK:1] [CLK_INV:0]
  • RST=[RST:1] [RST_INV:0]
SLICEL
  • BX=[BX_INV:0] [BX:41]
  • BY=[BY:76] [BY_INV:0]
  • CE=[CE:1] [CE_INV:0]
  • CIN=[CIN_INV:0] [CIN:61]
  • CLK=[CLK:156] [CLK_INV:0]
  • SR=[SR:1] [SR_INV:1]
SLICEL_CYMUXF
  • 0=[0:73] [0_INV:0]
  • 1=[1_INV:0] [1:73]
SLICEL_CYMUXG
  • 0=[0:60] [0_INV:0]
SLICEL_FFX
  • CK=[CK:88] [CK_INV:0]
  • D=[D:88] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:88]
  • FFX_SR_ATTR=[SRLOW:88]
  • LATCH_OR_FF=[FF:88]
  • SYNC_ATTR=[ASYNC:18] [SYNC:70]
SLICEL_FFY
  • CE=[CE:1] [CE_INV:0]
  • CK=[CK:148] [CK_INV:0]
  • D=[D:148] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:143] [INIT1:5]
  • FFY_SR_ATTR=[SRLOW:148]
  • LATCH_OR_FF=[FF:148]
  • SR=[SR:1] [SR_INV:1]
  • SYNC_ATTR=[ASYNC:58] [SYNC:90]
SLICEL_XORF
  • 1=[1_INV:0] [1:58]
SLICEM
  • BX=[BX_INV:0] [BX:34]
  • BY=[BY:63] [BY_INV:0]
  • CE=[CE:11] [CE_INV:0]
  • CLK=[CLK:63] [CLK_INV:0]
  • SR=[SR:63] [SR_INV:0]
SLICEM_F
  • DI=[DI:33] [DI_INV:0]
  • F_ATTR=[SHIFT_REG:33]
  • LUT_OR_MEM=[RAM:33]
SLICEM_FFX
  • CE=[CE:5] [CE_INV:0]
  • CK=[CK:34] [CK_INV:0]
  • D=[D:34] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:34]
  • FFX_SR_ATTR=[SRLOW:34]
  • LATCH_OR_FF=[FF:34]
  • SYNC_ATTR=[ASYNC:34]
SLICEM_FFY
  • CE=[CE:11] [CE_INV:0]
  • CK=[CK:63] [CK_INV:0]
  • D=[D:63] [D_INV:0]
  • FFY_INIT_ATTR=[INIT0:63]
  • FFY_SR_ATTR=[SRLOW:63]
  • LATCH_OR_FF=[FF:63]
  • SYNC_ATTR=[ASYNC:63]
SLICEM_G
  • DI=[DI:63] [DI_INV:0]
  • G_ATTR=[SHIFT_REG:63]
  • LUT_OR_MEM=[RAM:63]
SLICEM_WSGEN
  • CK=[CK:63] [CK_INV:0]
  • SYNC_ATTR=[ASYNC:63]
  • WE=[WE_INV:0] [WE:63]
 
Pin Data
BUFGMUX
  • I0=1
  • O=1
  • S=1
BUFGMUX_GCLKMUX
  • I0=1
  • OUT=1
  • S=1
BUFGMUX_GCLK_BUFFER
  • IN=1
  • OUT=1
IOB
  • I=17
  • O1=14
  • PAD=31
IOB_INBUF
  • IN=17
  • OUT=17
IOB_OUTBUF
  • IN=14
  • OUT=14
IOB_PAD
  • PAD=31
MULT18X18
  • A0=1
  • A1=1
  • A10=1
  • A11=1
  • A12=1
  • A13=1
  • A14=1
  • A15=1
  • A16=1
  • A17=1
  • A2=1
  • A3=1
  • A4=1
  • A5=1
  • A6=1
  • A7=1
  • A8=1
  • A9=1
  • B0=1
  • B1=1
  • B10=1
  • B11=1
  • B12=1
  • B13=1
  • B14=1
  • B15=1
  • B16=1
  • B17=1
  • B2=1
  • B3=1
  • B4=1
  • B5=1
  • B6=1
  • B7=1
  • B8=1
  • B9=1
  • CE=1
  • CLK=1
  • P0=1
  • P1=1
  • P10=1
  • P11=1
  • P12=1
  • P13=1
  • P14=1
  • P15=1
  • P16=1
  • P17=1
  • P18=1
  • P19=1
  • P2=1
  • P20=1
  • P21=1
  • P22=1
  • P23=1
  • P24=1
  • P25=1
  • P26=1
  • P27=1
  • P28=1
  • P29=1
  • P3=1
  • P30=1
  • P31=1
  • P32=1
  • P4=1
  • P5=1
  • P6=1
  • P7=1
  • P8=1
  • P9=1
  • RST=1
MULT18X18_BLACKBOX
  • A0=1
  • A1=1
  • A10=1
  • A11=1
  • A12=1
  • A13=1
  • A14=1
  • A15=1
  • A16=1
  • A17=1
  • A2=1
  • A3=1
  • A4=1
  • A5=1
  • A6=1
  • A7=1
  • A8=1
  • A9=1
  • B0=1
  • B1=1
  • B10=1
  • B11=1
  • B12=1
  • B13=1
  • B14=1
  • B15=1
  • B16=1
  • B17=1
  • B2=1
  • B3=1
  • B4=1
  • B5=1
  • B6=1
  • B7=1
  • B8=1
  • B9=1
  • CE=1
  • CLK=1
  • P0=1
  • P1=1
  • P10=1
  • P11=1
  • P12=1
  • P13=1
  • P14=1
  • P15=1
  • P16=1
  • P17=1
  • P18=1
  • P19=1
  • P2=1
  • P20=1
  • P21=1
  • P22=1
  • P23=1
  • P24=1
  • P25=1
  • P26=1
  • P27=1
  • P28=1
  • P29=1
  • P3=1
  • P30=1
  • P31=1
  • P32=1
  • P4=1
  • P5=1
  • P6=1
  • P7=1
  • P8=1
  • P9=1
  • RST=1
SLICEL
  • BX=41
  • BY=76
  • CE=1
  • CIN=61
  • CLK=156
  • COUT=61
  • F1=85
  • F2=66
  • F3=54
  • F4=28
  • G1=82
  • G2=56
  • G3=49
  • G4=24
  • SR=2
  • XB=1
  • XQ=88
  • Y=1
  • YQ=148
SLICEL_C1VDD
  • 1=3
SLICEL_C2VDD
  • 1=1
SLICEL_CYMUXF
  • 0=73
  • 1=73
  • OUT=73
  • S0=73
SLICEL_CYMUXG
  • 0=60
  • 1=61
  • OUT=61
  • S0=61
SLICEL_F
  • A1=85
  • A2=66
  • A3=54
  • A4=28
  • D=92
SLICEL_FAND
  • 0=18
  • 1=18
  • O=18
SLICEL_FFX
  • CK=88
  • D=88
  • Q=88
SLICEL_FFY
  • CE=1
  • CK=148
  • D=148
  • Q=148
  • SR=2
SLICEL_G
  • A1=82
  • A2=56
  • A3=49
  • A4=24
  • D=88
SLICEL_GAND
  • 0=18
  • 1=18
  • O=18
SLICEL_GNDF
  • 0=27
SLICEL_GNDG
  • 0=26
SLICEL_VDDG
  • 1=1
SLICEL_XORF
  • 0=58
  • 1=58
  • O=58
SLICEL_XORG
  • 0=57
  • 1=57
  • O=57
SLICEM
  • BX=34
  • BY=63
  • CE=11
  • CLK=63
  • F1=33
  • F2=33
  • F3=33
  • F4=33
  • G1=63
  • G2=63
  • G3=63
  • G4=63
  • SR=63
  • XQ=34
  • YQ=63
SLICEM_F
  • A1=33
  • A2=33
  • A3=33
  • A4=33
  • D=33
  • DI=33
  • WS=33
SLICEM_FFX
  • CE=5
  • CK=34
  • D=34
  • Q=34
SLICEM_FFY
  • CE=11
  • CK=63
  • D=63
  • Q=63
SLICEM_G
  • A1=63
  • A2=63
  • A3=63
  • A4=63
  • D=63
  • DI=63
  • WS=63
SLICEM_WSGEN
  • CK=63
  • WE=63
  • WSF=33
  • WSG=63
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -i -p xc3s400-fg456-4 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s400-fg456-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -sd <dname> -nt timestamp -i -p xc3s400-fg456-4 <ise_file> <fname>.ngd
  • map -intstyle ise -p xc3s400-fg456-4 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 4 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
_impact 32 25 0 0 0 0 0
bitgen 43 43 0 0 0 0 0
compxlib 3 3 0 0 0 0 0
edif2ngd 15 15 0 0 0 0 0
map 107 105 0 0 0 0 0
netgen 3 3 0 0 0 0 0
ngc2edif 17 17 0 0 0 0 0
ngcbuild 15 15 0 0 0 0 0
ngdbuild 127 127 0 0 0 0 0
obngc 15 15 0 0 0 0 0
par 105 104 1 0 0 0 0
trce 104 104 0 0 0 0 0
xps 1 1 0 0 0 0 0
xst 315 311 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/cgn_c_overview.htm ( 1 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store non-default values only
PROP_SelectedInstanceHierarchicalPath=/Filter/FIR1 PROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changed PROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=false PROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2012-05-30T14:13:14 PROP_intWbtProjectID=6DB7B94D27BA4AED9F0BAE2D7C334FC8
PROP_intWbtProjectIteration=2 PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=No PROP_selectedSimRootSourceNode_behav=work.fir_compiler_v5_0
PROP_AutoTop=true PROP_DevFamily=Spartan3
PROP_DevDevice=xc3s400 PROP_DevFamilyPMName=spartan3
PROP_DevPackage=fg456 PROP_Synthesis_Tool=XST (VHDL/Verilog)
PROP_DevSpeed=-4 PROP_PreferredLanguage=VHDL
FILE_NGC=1 FILE_VHDL=1
 
Core Statistics
Core Type=fir_compiler_v5_0
accum_width=37 allow_approx=0 c_has_ce=0 c_has_data_valid=0
c_has_nd=0 c_has_sclr=0 c_latency=26 c_mem_init_file=fname.mif
c_optimization=0 chan_in_adv=0 chan_sel_width=1 clock_freq=250000000
coef_memtype=0 coef_reload=0 coef_type=0 coef_width=16
col_config=1 col_mode=0 col_pipe_len=4 data_memtype=0
data_type=0 data_width=16 datapath_memtype=0 decim_rate=1
filter_arch=1 filter_sel_width=1 filter_type=0 interp_rate=1
ipbuff_memtype=0 neg_symmetry=0 num_channels=1 num_filts=1
num_paths=1 num_taps=21 odd_symmetry=1 opbuff_memtype=0
output_reg=1 output_width=14 rate_change_type=0 round_mode=1
sample_freq=1000 sclr_deterministic=0 symmetry=1 zero_packing_factor=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=95 NGDBUILD_NUM_FDE=79 NGDBUILD_NUM_FDR=2
NGDBUILD_NUM_FDRE=47 NGDBUILD_NUM_FDRSE=139 NGDBUILD_NUM_FDSE=2 NGDBUILD_NUM_GND=1
NGDBUILD_NUM_IBUF=16 NGDBUILD_NUM_INV=1 NGDBUILD_NUM_LUT1=45 NGDBUILD_NUM_LUT2=57
NGDBUILD_NUM_LUT3=51 NGDBUILD_NUM_LUT4=52 NGDBUILD_NUM_MULT18X18S=1 NGDBUILD_NUM_MUXCY=22
NGDBUILD_NUM_MUXCY_D=7 NGDBUILD_NUM_MUXCY_L=121 NGDBUILD_NUM_OBUF=14 NGDBUILD_NUM_SRL16=19
NGDBUILD_NUM_SRLC16E=77 NGDBUILD_NUM_VCC=1 NGDBUILD_NUM_XORCY=131
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_FD=95 NGDBUILD_NUM_FDE=79 NGDBUILD_NUM_FDR=2
NGDBUILD_NUM_FDRE=47 NGDBUILD_NUM_FDRSE=139 NGDBUILD_NUM_FDSE=2 NGDBUILD_NUM_GND=2
NGDBUILD_NUM_IBUF=16 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=1 NGDBUILD_NUM_LUT1=45
NGDBUILD_NUM_LUT2=57 NGDBUILD_NUM_LUT3=51 NGDBUILD_NUM_LUT4=52 NGDBUILD_NUM_MULT18X18S=1
NGDBUILD_NUM_MUXCY=22 NGDBUILD_NUM_MUXCY_D=7 NGDBUILD_NUM_MUXCY_L=121 NGDBUILD_NUM_OBUF=14
NGDBUILD_NUM_SRLC16E=96 NGDBUILD_NUM_VCC=2 NGDBUILD_NUM_XORCY=131