Filter Project Status (05/30/2012 - 14:52:28) | |||
Project File: | Filter.xise | Parser Errors: | No Errors |
Module Name: | Filter_Testbench | Implementation State: | Synthesized (Failed) |
Target Device: | xc3s400-4fg456 |
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X 2 Errors (2 new) |
Product Version: | ISE 13.1 |
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No Warnings |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Mi 30. Mai 14:52:28 2012 | X 2 Errors (2 new) | 0 | 0 | |
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Mi 30. Mai 14:51:33 2012 | |
WebTalk Report | Out of Date | Mi 30. Mai 14:28:45 2012 | |
WebTalk Log File | Out of Date | Mi 30. Mai 14:28:49 2012 |