Filter Project Status (05/30/2012 - 14:52:28)
Project File: Filter.xise Parser Errors: No Errors
Module Name: Filter_Testbench Implementation State: Synthesized (Failed)
Target Device: xc3s400-4fg456
  • Errors:
X 2 Errors (2 new)
Product Version:ISE 13.1
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMi 30. Mai 14:52:28 2012X 2 Errors (2 new)00
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateMi 30. Mai 14:51:33 2012
WebTalk ReportOut of DateMi 30. Mai 14:28:45 2012
WebTalk Log FileOut of DateMi 30. Mai 14:28:49 2012

Date Generated: 05/30/2012 - 14:52:29