-------------------------------------------------------------------------------- Release 13.4 Trace (nt64) Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. C:\Xilinx\13.4\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 1 -n 3 -fastpaths -xml Top_Modul_DDR2_Cameralink.twx Top_Modul_DDR2_Cameralink.ncd -o Top_Modul_DDR2_Cameralink.twr Top_Modul_DDR2_Cameralink.pcf -ucf Top_Modul.ucf -ucf Top_Modul_DDR2_Cameralink.ucf -ucf TopModule_CameraLinkFull.ucf Design file: Top_Modul_DDR2_Cameralink.ncd Physical constraint file: Top_Modul_DDR2_Cameralink.pcf Device,package,speed: xc5vfx70t,ff1136,-1 (PRODUCTION 1.73 2012-01-07, STEPPING level 0) Report level: verbose report Environment Variable Effect -------------------- ------ NONE No environment variables were set -------------------------------------------------------------------------------- WARNING:Timing:3223 - Timing constraint TS_MC_PHY_INIT_DATA_SEL_90 = MAXDELAY FROM TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO TIMEGRP "RAMS" TS_SYS_CLK * 4; ignored during timing analysis. INFO:Timing:3386 - Intersecting Constraints found and resolved. For more information, see the TSI report. Please consult the Xilinx Command Line Tools User Guide for information on generating a TSI report. INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. ================================================================================ Timing constraint: NET "DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/en_dqs_sync" MAXDELAY = 0.85 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 0.805ns. -------------------------------------------------------------------------------- Slack: 0.045ns DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/en_dqs_sync Report: 0.805ns delay meets 0.850ns timing constraint by 0.045ns From To Delay(ns) IODELAY_X0Y96.DATAOUT ILOGIC_X0Y96.SR 0.805 IODELAY_X0Y96.DATAOUT ILOGIC_X0Y96.DDLY 0.000 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<0>" MAXDELAY = 0.6 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 0.529ns. -------------------------------------------------------------------------------- Slack: 0.071ns DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<0> Report: 0.529ns delay meets 0.600ns timing constraint by 0.071ns From To Delay(ns) SLICE_X0Y48.DQ IODELAY_X0Y96.DATAIN 0.529 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/en_dqs_sync" MAXDELAY = 0.85 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 0.805ns. -------------------------------------------------------------------------------- Slack: 0.045ns DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/en_dqs_sync Report: 0.805ns delay meets 0.850ns timing constraint by 0.045ns From To Delay(ns) IODELAY_X0Y58.DATAOUT ILOGIC_X0Y58.SR 0.805 IODELAY_X0Y58.DATAOUT ILOGIC_X0Y58.DDLY 0.000 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<1>" MAXDELAY = 0.6 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 0.529ns. -------------------------------------------------------------------------------- Slack: 0.071ns DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<1> Report: 0.529ns delay meets 0.600ns timing constraint by 0.071ns From To Delay(ns) SLICE_X0Y29.DQ IODELAY_X0Y58.DATAIN 0.529 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/en_dqs_sync" MAXDELAY = 0.85 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 0.803ns. -------------------------------------------------------------------------------- Slack: 0.047ns DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/en_dqs_sync Report: 0.803ns delay meets 0.850ns timing constraint by 0.047ns From To Delay(ns) IODELAY_X0Y62.DATAOUT ILOGIC_X0Y62.SR 0.803 IODELAY_X0Y62.DATAOUT ILOGIC_X0Y62.DDLY 0.000 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<2>" MAXDELAY = 0.6 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 0.529ns. -------------------------------------------------------------------------------- Slack: 0.071ns DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<2> Report: 0.529ns delay meets 0.600ns timing constraint by 0.071ns From To Delay(ns) SLICE_X0Y31.DQ IODELAY_X0Y62.DATAIN 0.529 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/en_dqs_sync" MAXDELAY = 0.85 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 0.803ns. -------------------------------------------------------------------------------- Slack: 0.047ns DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[3].u_iob_dqs/en_dqs_sync Report: 0.803ns delay meets 0.850ns timing constraint by 0.047ns From To Delay(ns) IODELAY_X0Y100.DATAOUT ILOGIC_X0Y100.SR 0.803 IODELAY_X0Y100.DATAOUT ILOGIC_X0Y100.DDLY 0.000 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<3>" MAXDELAY = 0.6 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 0.529ns. -------------------------------------------------------------------------------- Slack: 0.071ns DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<3> Report: 0.529ns delay meets 0.600ns timing constraint by 0.071ns From To Delay(ns) SLICE_X0Y50.DQ IODELAY_X0Y100.DATAIN 0.529 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/en_dqs_sync" MAXDELAY = 0.85 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 0.803ns. -------------------------------------------------------------------------------- Slack: 0.047ns DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/en_dqs_sync Report: 0.803ns delay meets 0.850ns timing constraint by 0.047ns From To Delay(ns) IODELAY_X0Y102.DATAOUT ILOGIC_X0Y102.SR 0.803 IODELAY_X0Y102.DATAOUT ILOGIC_X0Y102.DDLY 0.000 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<4>" MAXDELAY = 0.6 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 0.532ns. -------------------------------------------------------------------------------- Slack: 0.068ns DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<4> Report: 0.532ns delay meets 0.600ns timing constraint by 0.068ns From To Delay(ns) SLICE_X0Y51.DQ IODELAY_X0Y102.DATAIN 0.532 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/en_dqs_sync" MAXDELAY = 0.85 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 0.805ns. -------------------------------------------------------------------------------- Slack: 0.045ns DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/en_dqs_sync Report: 0.805ns delay meets 0.850ns timing constraint by 0.045ns From To Delay(ns) IODELAY_X0Y256.DATAOUT ILOGIC_X0Y256.SR 0.805 IODELAY_X0Y256.DATAOUT ILOGIC_X0Y256.DDLY 0.000 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<5>" MAXDELAY = 0.6 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 0.529ns. -------------------------------------------------------------------------------- Slack: 0.071ns DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<5> Report: 0.529ns delay meets 0.600ns timing constraint by 0.071ns From To Delay(ns) SLICE_X0Y128.DQ IODELAY_X0Y256.DATAIN 0.529 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/en_dqs_sync" MAXDELAY = 0.85 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 0.803ns. -------------------------------------------------------------------------------- Slack: 0.047ns DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/en_dqs_sync Report: 0.803ns delay meets 0.850ns timing constraint by 0.047ns From To Delay(ns) IODELAY_X0Y260.DATAOUT ILOGIC_X0Y260.SR 0.803 IODELAY_X0Y260.DATAOUT ILOGIC_X0Y260.DDLY 0.000 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<6>" MAXDELAY = 0.6 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 0.529ns. -------------------------------------------------------------------------------- Slack: 0.071ns DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<6> Report: 0.529ns delay meets 0.600ns timing constraint by 0.071ns From To Delay(ns) SLICE_X0Y130.DQ IODELAY_X0Y260.DATAIN 0.529 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/en_dqs_sync" MAXDELAY = 0.85 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 0.803ns. -------------------------------------------------------------------------------- Slack: 0.047ns DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/en_dqs_sync Report: 0.803ns delay meets 0.850ns timing constraint by 0.047ns From To Delay(ns) IODELAY_X0Y262.DATAOUT ILOGIC_X0Y262.SR 0.803 IODELAY_X0Y262.DATAOUT ILOGIC_X0Y262.DDLY 0.000 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: NET "DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<7>" MAXDELAY = 0.6 ns; 1 net analyzed, 0 failing nets detected. 0 timing errors detected. Maximum net delay is 0.529ns. -------------------------------------------------------------------------------- Slack: 0.071ns DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<7> Report: 0.529ns delay meets 0.600ns timing constraint by 0.071ns From To Delay(ns) SLICE_X0Y131.DQ IODELAY_X0Y262.DATAIN 0.529 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_SYS_CLK = PERIOD TIMEGRP "SYS_CLK" 3.75 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 component switching limit errors) Minimum period is 2.334ns. -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_SYS_CLK = PERIOD TIMEGRP "SYS_CLK" 3.75 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 1.416ns (period - (min low pulse limit / (low pulse / period))) Period: 3.750ns Low pulse: 1.875ns Low pulse limit: 1.167ns (Tdcmpw_CLKIN_250_300) Physical resource: DDR2_RAM_CORE/u_ddr2_infrastructure/gen_pll_adv.u_pll_adv/CLKIN1 Logical resource: DDR2_RAM_CORE/u_ddr2_infrastructure/gen_pll_adv.u_pll_adv/CLKIN1 Location pin: PLL_ADV_X0Y0.CLKIN1 Clock network: i_sys_clk_266 -------------------------------------------------------------------------------- Slack: 1.416ns (period - (min high pulse limit / (high pulse / period))) Period: 3.750ns High pulse: 1.875ns High pulse limit: 1.167ns (Tdcmpw_CLKIN_250_300) Physical resource: DDR2_RAM_CORE/u_ddr2_infrastructure/gen_pll_adv.u_pll_adv/CLKIN1 Logical resource: DDR2_RAM_CORE/u_ddr2_infrastructure/gen_pll_adv.u_pll_adv/CLKIN1 Location pin: PLL_ADV_X0Y0.CLKIN1 Clock network: i_sys_clk_266 -------------------------------------------------------------------------------- Slack: 2.084ns (period - min period limit) Period: 3.750ns Min period limit: 1.666ns (600.240MHz) (Tpllper_CLKOUT) Physical resource: DDR2_RAM_CORE/u_ddr2_infrastructure/gen_pll_adv.u_pll_adv/CLKOUT0 Logical resource: DDR2_RAM_CORE/u_ddr2_infrastructure/gen_pll_adv.u_pll_adv/CLKOUT0 Location pin: PLL_ADV_X0Y0.CLKOUT0 Clock network: DDR2_RAM_CORE/u_ddr2_infrastructure/clk0_bufg_in -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_SYS_CLK_200 = PERIOD TIMEGRP "SYS_CLK_200" 5 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 24 paths analyzed, 24 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 2.892ns. -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_24 (SLICE_X15Y65.BX), 1 path -------------------------------------------------------------------------------- Slack (setup path): 2.108ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_23 (FF) Destination: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_24 (FF) Requirement: 5.000ns Data Path Delay: 2.919ns (Levels of Logic = 0) Clock Path Skew: 0.062ns (1.292 - 1.230) Source Clock: DDR2_RAM_CORE/clk200 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clk200 rising at 5.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_23 to DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_24 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X48Y64.DQ Tcko 0.471 DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r<23> DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_23 SLICE_X15Y65.BX net (fanout=1) 2.459 DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r<23> SLICE_X15Y65.CLK Tdick -0.011 DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r<24> DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_24 ------------------------------------------------- --------------------------- Total 2.919ns (0.460ns logic, 2.459ns route) (15.8% logic, 84.2% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_20 (SLICE_X48Y64.AX), 1 path -------------------------------------------------------------------------------- Slack (setup path): 3.387ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_19 (FF) Destination: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_20 (FF) Requirement: 5.000ns Data Path Delay: 1.446ns (Levels of Logic = 0) Clock Path Skew: -0.132ns (0.457 - 0.589) Source Clock: DDR2_RAM_CORE/clk200 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clk200 rising at 5.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_19 to DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_20 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X60Y62.DQ Tcko 0.471 DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r<19> DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_19 SLICE_X48Y64.AX net (fanout=1) 0.987 DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r<19> SLICE_X48Y64.CLK Tdick -0.012 DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r<23> DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_20 ------------------------------------------------- --------------------------- Total 1.446ns (0.459ns logic, 0.987ns route) (31.7% logic, 68.3% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_22 (SLICE_X48Y64.CX), 1 path -------------------------------------------------------------------------------- Slack (setup path): 3.685ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_21 (FF) Destination: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_22 (FF) Requirement: 5.000ns Data Path Delay: 1.280ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: DDR2_RAM_CORE/clk200 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clk200 rising at 5.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_21 to DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_22 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X48Y64.BQ Tcko 0.471 DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r<23> DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_21 SLICE_X48Y64.CX net (fanout=1) 0.814 DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r<21> SLICE_X48Y64.CLK Tdick -0.005 DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r<23> DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_22 ------------------------------------------------- --------------------------- Total 1.280ns (0.466ns logic, 0.814ns route) (36.4% logic, 63.6% route) -------------------------------------------------------------------------------- Hold Paths: TS_SYS_CLK_200 = PERIOD TIMEGRP "SYS_CLK_200" 5 ns HIGH 50%; -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_9 (SLICE_X59Y64.BX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.465ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_8 (FF) Destination: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_9 (FF) Requirement: 0.000ns Data Path Delay: 0.465ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: DDR2_RAM_CORE/clk200 rising at 5.000ns Destination Clock: DDR2_RAM_CORE/clk200 rising at 5.000ns Clock Uncertainty: 0.000ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_8 to DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_9 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X59Y64.AQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r<11> DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_8 SLICE_X59Y64.BX net (fanout=1) 0.282 DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r<8> SLICE_X59Y64.CLK Tckdi (-Th) 0.231 DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r<11> DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_9 ------------------------------------------------- --------------------------- Total 0.465ns (0.183ns logic, 0.282ns route) (39.4% logic, 60.6% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_1 (SLICE_X59Y65.BX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.465ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_0 (FF) Destination: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_1 (FF) Requirement: 0.000ns Data Path Delay: 0.465ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: DDR2_RAM_CORE/clk200 rising at 5.000ns Destination Clock: DDR2_RAM_CORE/clk200 rising at 5.000ns Clock Uncertainty: 0.000ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_0 to DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X59Y65.AQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r<3> DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_0 SLICE_X59Y65.BX net (fanout=1) 0.282 DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r<0> SLICE_X59Y65.CLK Tckdi (-Th) 0.231 DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r<3> DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_1 ------------------------------------------------- --------------------------- Total 0.465ns (0.183ns logic, 0.282ns route) (39.4% logic, 60.6% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_13 (SLICE_X65Y62.BX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.465ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_12 (FF) Destination: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_13 (FF) Requirement: 0.000ns Data Path Delay: 0.465ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: DDR2_RAM_CORE/clk200 rising at 5.000ns Destination Clock: DDR2_RAM_CORE/clk200 rising at 5.000ns Clock Uncertainty: 0.000ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_12 to DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_13 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X65Y62.AQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r<15> DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_12 SLICE_X65Y62.BX net (fanout=1) 0.282 DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r<12> SLICE_X65Y62.CLK Tckdi (-Th) 0.231 DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r<15> DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_13 ------------------------------------------------- --------------------------- Total 0.465ns (0.183ns logic, 0.282ns route) (39.4% logic, 60.6% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_SYS_CLK_200 = PERIOD TIMEGRP "SYS_CLK_200" 5 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 3.334ns (period - min period limit) Period: 5.000ns Min period limit: 1.666ns (600.240MHz) (Tbgper_I) Physical resource: DDR2_RAM_CORE/u_ddr2_infrastructure/NOCLK200_CHECK_BUFG.CLK_200_BUFG/I0 Logical resource: DDR2_RAM_CORE/u_ddr2_infrastructure/NOCLK200_CHECK_BUFG.CLK_200_BUFG/I0 Location pin: BUFGCTRL_X0Y26.I0 Clock network: DDR2_RAM_CORE/u_ddr2_infrastructure/clk200_ibufg -------------------------------------------------------------------------------- Slack: 3.946ns (period - (min low pulse limit / (low pulse / period))) Period: 5.000ns Low pulse: 2.500ns Low pulse limit: 0.527ns (Trpw) Physical resource: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r<24>/SR Logical resource: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_24/SR Location pin: SLICE_X15Y65.SR Clock network: DDR2_RAM_CORE/u_ddr2_infrastructure/locked_inv -------------------------------------------------------------------------------- Slack: 3.946ns (period - (min high pulse limit / (high pulse / period))) Period: 5.000ns High pulse: 2.500ns High pulse limit: 0.527ns (Trpw) Physical resource: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r<24>/SR Logical resource: DDR2_RAM_CORE/u_ddr2_infrastructure/rst200_sync_r_24/SR Location pin: SLICE_X15Y65.SR Clock network: DDR2_RAM_CORE/u_ddr2_infrastructure/locked_inv -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_MC_RD_DATA_SEL = MAXDELAY FROM TIMEGRP "TNM_RD_DATA_SEL" TO TIMEGRP "FFS" TS_SYS_CLK * 4; For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612). 384 paths analyzed, 384 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 4.652ns. -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_rise_1x_r_33 (SLICE_X11Y75.BX), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 10.348ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[4].u_ff_rd_data_sel (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_rise_1x_r_33 (FF) Requirement: 15.000ns Data Path Delay: 4.476ns (Levels of Logic = 1) Clock Path Skew: -0.104ns (1.306 - 1.410) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clkdiv0 rising at 7.500ns Clock Uncertainty: 0.072ns Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[4].u_ff_rd_data_sel to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_rise_1x_r_33 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X11Y97.AQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/rd_data_sel<7> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[4].u_ff_rd_data_sel SLICE_X8Y57.B1 net (fanout=16) 2.613 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/rd_data_sel<4> SLICE_X8Y57.B Tilo 0.094 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise<35> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[33].u_iob_dq/rd_data_rise1 SLICE_X11Y75.BX net (fanout=2) 1.330 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/rd_data_rise<33> SLICE_X11Y75.CLK Tdick -0.011 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_rise_1x_r<35> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_rise_1x_r_33 ------------------------------------------------- --------------------------- Total 4.476ns (0.533ns logic, 3.943ns route) (11.9% logic, 88.1% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_fall_1x_r_19 (SLICE_X16Y50.DX), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 10.380ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[2].u_ff_rd_data_sel (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_fall_1x_r_19 (FF) Requirement: 15.000ns Data Path Delay: 4.580ns (Levels of Logic = 1) Clock Path Skew: 0.032ns (0.589 - 0.557) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clkdiv0 rising at 7.500ns Clock Uncertainty: 0.072ns Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[2].u_ff_rd_data_sel to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_fall_1x_r_19 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X34Y57.CQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/rd_data_sel<3> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[2].u_ff_rd_data_sel SLICE_X12Y38.D3 net (fanout=16) 2.642 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/rd_data_sel<2> SLICE_X12Y38.D Tilo 0.094 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall<19> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[19].u_iob_dq/rd_data_fall1 SLICE_X16Y50.DX net (fanout=2) 1.399 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/rd_data_fall<19> SLICE_X16Y50.CLK Tdick -0.005 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_fall_1x_r<19> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_fall_1x_r_19 ------------------------------------------------- --------------------------- Total 4.580ns (0.539ns logic, 4.041ns route) (11.8% logic, 88.2% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_fall_1x_r_21 (SLICE_X18Y50.BX), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 10.404ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[2].u_ff_rd_data_sel (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_fall_1x_r_21 (FF) Requirement: 15.000ns Data Path Delay: 4.575ns (Levels of Logic = 1) Clock Path Skew: 0.051ns (0.608 - 0.557) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clkdiv0 rising at 7.500ns Clock Uncertainty: 0.072ns Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[2].u_ff_rd_data_sel to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_fall_1x_r_21 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X34Y57.CQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/rd_data_sel<3> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[2].u_ff_rd_data_sel SLICE_X12Y37.B3 net (fanout=16) 2.980 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/rd_data_sel<2> SLICE_X12Y37.B Tilo 0.094 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall<23> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[21].u_iob_dq/rd_data_fall1 SLICE_X18Y50.BX net (fanout=2) 1.062 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/rd_data_fall<21> SLICE_X18Y50.CLK Tdick -0.011 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_fall_1x_r<23> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_fall_1x_r_21 ------------------------------------------------- --------------------------- Total 4.575ns (0.533ns logic, 4.042ns route) (11.7% logic, 88.3% route) -------------------------------------------------------------------------------- Hold Paths: TS_MC_RD_DATA_SEL = MAXDELAY FROM TIMEGRP "TNM_RD_DATA_SEL" TO TIMEGRP "FFS" TS_SYS_CLK * 4; -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall_41 (SLICE_X9Y109.B4), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.891ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[5].u_ff_rd_data_sel (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall_41 (FF) Requirement: 0.000ns Data Path Delay: 1.417ns (Levels of Logic = 1) Positive Clock Path Skew: 0.334ns (3.750 - 3.416) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 0.000ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[5].u_ff_rd_data_sel to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall_41 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X11Y97.BQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/rd_data_sel<7> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[5].u_ff_rd_data_sel SLICE_X9Y109.B4 net (fanout=16) 1.193 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/rd_data_sel<5> SLICE_X9Y109.CLK Tah (-Th) 0.190 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall<43> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/fall_data_41_mux00001 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall_41 ------------------------------------------------- --------------------------- Total 1.417ns (0.224ns logic, 1.193ns route) (15.8% logic, 84.2% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall_58 (SLICE_X7Y120.C3), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.913ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[7].u_ff_rd_data_sel (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall_58 (FF) Requirement: 0.000ns Data Path Delay: 1.565ns (Levels of Logic = 1) Positive Clock Path Skew: 0.460ns (3.876 - 3.416) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 0.000ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[7].u_ff_rd_data_sel to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall_58 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X11Y97.DQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/rd_data_sel<7> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[7].u_ff_rd_data_sel SLICE_X7Y120.C3 net (fanout=16) 1.353 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/rd_data_sel<7> SLICE_X7Y120.CLK Tah (-Th) 0.202 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall<59> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/fall_data_58_mux00001 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall_58 ------------------------------------------------- --------------------------- Total 1.565ns (0.212ns logic, 1.353ns route) (13.5% logic, 86.5% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall_59 (SLICE_X7Y120.D3), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.916ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[7].u_ff_rd_data_sel (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall_59 (FF) Requirement: 0.000ns Data Path Delay: 1.568ns (Levels of Logic = 1) Positive Clock Path Skew: 0.460ns (3.876 - 3.416) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 0.000ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[7].u_ff_rd_data_sel to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall_59 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X11Y97.DQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/rd_data_sel<7> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rd_data_sel[7].u_ff_rd_data_sel SLICE_X7Y120.D3 net (fanout=16) 1.357 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/rd_data_sel<7> SLICE_X7Y120.CLK Tah (-Th) 0.203 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall<59> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/fall_data_59_mux00001 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall_59 ------------------------------------------------- --------------------------- Total 1.568ns (0.211ns logic, 1.357ns route) (13.5% logic, 86.5% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "FFS" TS_SYS_CLK * 4; For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612). 128 paths analyzed, 128 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 3.412ns. -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise_39 (SLICE_X9Y64.D1), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 11.588ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[4].u_ff_rden_sel_mux (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise_39 (FF) Requirement: 15.000ns Data Path Delay: 3.265ns (Levels of Logic = 1) Clock Path Skew: -0.082ns (1.319 - 1.401) Source Clock: u_clk0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.065ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.108ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[4].u_ff_rden_sel_mux to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise_39 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X13Y95.AQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rden_sel_mux<7> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[4].u_ff_rden_sel_mux SLICE_X9Y64.D1 net (fanout=16) 2.776 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rden_sel_mux<4> SLICE_X9Y64.CLK Tas 0.039 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise<39> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rise_data_39_mux00001 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise_39 ------------------------------------------------- --------------------------- Total 3.265ns (0.489ns logic, 2.776ns route) (15.0% logic, 85.0% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise_38 (SLICE_X9Y64.C1), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 11.590ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[4].u_ff_rden_sel_mux (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise_38 (FF) Requirement: 15.000ns Data Path Delay: 3.263ns (Levels of Logic = 1) Clock Path Skew: -0.082ns (1.319 - 1.401) Source Clock: u_clk0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.065ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.108ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[4].u_ff_rden_sel_mux to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise_38 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X13Y95.AQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rden_sel_mux<7> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[4].u_ff_rden_sel_mux SLICE_X9Y64.C1 net (fanout=16) 2.773 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rden_sel_mux<4> SLICE_X9Y64.CLK Tas 0.040 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise<39> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rise_data_38_mux00001 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise_38 ------------------------------------------------- --------------------------- Total 3.263ns (0.490ns logic, 2.773ns route) (15.0% logic, 85.0% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall_37 (SLICE_X9Y62.B1), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 11.603ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[4].u_ff_rden_sel_mux (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall_37 (FF) Requirement: 15.000ns Data Path Delay: 3.255ns (Levels of Logic = 1) Clock Path Skew: -0.077ns (1.324 - 1.401) Source Clock: u_clk0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.065ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.108ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[4].u_ff_rden_sel_mux to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall_37 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X13Y95.AQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rden_sel_mux<7> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[4].u_ff_rden_sel_mux SLICE_X9Y62.B1 net (fanout=16) 2.763 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rden_sel_mux<4> SLICE_X9Y62.CLK Tas 0.042 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall<39> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/fall_data_37_mux00001 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall_37 ------------------------------------------------- --------------------------- Total 3.255ns (0.492ns logic, 2.763ns route) (15.1% logic, 84.9% route) -------------------------------------------------------------------------------- Hold Paths: TS_MC_RDEN_SEL_MUX = MAXDELAY FROM TIMEGRP "TNM_RDEN_SEL_MUX" TO TIMEGRP "FFS" TS_SYS_CLK * 4; -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall_29 (SLICE_X16Y52.B2), 1 path -------------------------------------------------------------------------------- Slack (hold path): 1.266ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[3].u_ff_rden_sel_mux (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall_29 (FF) Requirement: 0.000ns Data Path Delay: 1.366ns (Levels of Logic = 1) Positive Clock Path Skew: 0.100ns (0.642 - 0.542) Source Clock: u_clk0 rising at 3.750ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.000ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[3].u_ff_rden_sel_mux to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall_29 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X24Y50.DQ Tcko 0.433 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rden_sel_mux<3> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[3].u_ff_rden_sel_mux SLICE_X16Y52.B2 net (fanout=16) 1.137 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rden_sel_mux<3> SLICE_X16Y52.CLK Tah (-Th) 0.204 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall<31> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/fall_data_29_mux00001 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_fall_29 ------------------------------------------------- --------------------------- Total 1.366ns (0.229ns logic, 1.137ns route) (16.8% logic, 83.2% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise_28 (SLICE_X12Y54.A2), 1 path -------------------------------------------------------------------------------- Slack (hold path): 1.379ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[3].u_ff_rden_sel_mux (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise_28 (FF) Requirement: 0.000ns Data Path Delay: 1.501ns (Levels of Logic = 1) Positive Clock Path Skew: 0.122ns (0.664 - 0.542) Source Clock: u_clk0 rising at 3.750ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.000ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[3].u_ff_rden_sel_mux to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise_28 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X24Y50.DQ Tcko 0.433 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rden_sel_mux<3> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[3].u_ff_rden_sel_mux SLICE_X12Y54.A2 net (fanout=16) 1.280 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rden_sel_mux<3> SLICE_X12Y54.CLK Tah (-Th) 0.212 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise<31> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rise_data_28_mux00001 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise_28 ------------------------------------------------- --------------------------- Total 1.501ns (0.221ns logic, 1.280ns route) (14.7% logic, 85.3% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise_29 (SLICE_X12Y54.B2), 1 path -------------------------------------------------------------------------------- Slack (hold path): 1.380ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[3].u_ff_rden_sel_mux (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise_29 (FF) Requirement: 0.000ns Data Path Delay: 1.502ns (Levels of Logic = 1) Positive Clock Path Skew: 0.122ns (0.664 - 0.542) Source Clock: u_clk0 rising at 3.750ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.000ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[3].u_ff_rden_sel_mux to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise_29 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X24Y50.DQ Tcko 0.433 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rden_sel_mux<3> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[3].u_ff_rden_sel_mux SLICE_X12Y54.B2 net (fanout=16) 1.273 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rden_sel_mux<3> SLICE_X12Y54.CLK Tah (-Th) 0.204 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise<31> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rise_data_29_mux00001 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rd_data_out_rise_29 ------------------------------------------------- --------------------------- Total 1.502ns (0.229ns logic, 1.273ns route) (15.2% logic, 84.8% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_MC_PHY_INIT_DATA_SEL_0 = MAXDELAY FROM TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO TIMEGRP "FFS" TS_SYS_CLK * 4; For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612). 294 paths analyzed, 294 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 4.933ns. -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_108 (SLICE_X12Y101.SR), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 10.067ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/u_ff_phy_init_data_sel (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_108 (FF) Requirement: 15.000ns Data Path Delay: 4.542ns (Levels of Logic = 1) Clock Path Skew: -0.199ns (3.510 - 3.709) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clk90 rising at 0.937ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/u_ff_phy_init_data_sel to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_108 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X14Y98.AQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/phy_init_data_sel DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/u_ff_phy_init_data_sel SLICE_X8Y82.A6 net (fanout=154) 1.324 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/phy_init_data_sel SLICE_X8Y82.A Tilo 0.094 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/N3 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_mux0001<100>11 SLICE_X12Y101.SR net (fanout=15) 2.133 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/N3 SLICE_X12Y101.CLK Tsrck 0.541 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r<108> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_108 ------------------------------------------------- --------------------------- Total 4.542ns (1.085ns logic, 3.457ns route) (23.9% logic, 76.1% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_118 (SLICE_X10Y108.SR), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 10.168ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/u_ff_phy_init_data_sel (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_118 (FF) Requirement: 15.000ns Data Path Delay: 4.446ns (Levels of Logic = 1) Clock Path Skew: -0.194ns (3.515 - 3.709) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clk90 rising at 0.937ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/u_ff_phy_init_data_sel to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_118 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X14Y98.AQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/phy_init_data_sel DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/u_ff_phy_init_data_sel SLICE_X8Y83.A6 net (fanout=154) 1.319 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/phy_init_data_sel SLICE_X8Y83.A Tilo 0.094 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/N1 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_mux0001<101>11 SLICE_X10Y108.SR net (fanout=16) 2.036 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/N1 SLICE_X10Y108.CLK Tsrck 0.547 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r<119> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_118 ------------------------------------------------- --------------------------- Total 4.446ns (1.091ns logic, 3.355ns route) (24.5% logic, 75.5% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_119 (SLICE_X10Y108.SR), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 10.168ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/u_ff_phy_init_data_sel (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_119 (FF) Requirement: 15.000ns Data Path Delay: 4.446ns (Levels of Logic = 1) Clock Path Skew: -0.194ns (3.515 - 3.709) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clk90 rising at 0.937ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/u_ff_phy_init_data_sel to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_119 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X14Y98.AQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/phy_init_data_sel DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/u_ff_phy_init_data_sel SLICE_X8Y83.A6 net (fanout=154) 1.319 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/phy_init_data_sel SLICE_X8Y83.A Tilo 0.094 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/N1 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_mux0001<101>11 SLICE_X10Y108.SR net (fanout=16) 2.036 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/N1 SLICE_X10Y108.CLK Tsrck 0.547 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r<119> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_119 ------------------------------------------------- --------------------------- Total 4.446ns (1.091ns logic, 3.355ns route) (24.5% logic, 75.5% route) -------------------------------------------------------------------------------- Hold Paths: TS_MC_PHY_INIT_DATA_SEL_0 = MAXDELAY FROM TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO TIMEGRP "FFS" TS_SYS_CLK * 4; -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_108 (SLICE_X12Y101.A5), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.199ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/u_ff_phy_init_data_sel (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_108 (FF) Requirement: 0.000ns Data Path Delay: 0.716ns (Levels of Logic = 1) Positive Clock Path Skew: 0.325ns (3.774 - 3.449) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clk90 rising at -2.813ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/u_ff_phy_init_data_sel to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_108 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X14Y98.AQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/phy_init_data_sel DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/u_ff_phy_init_data_sel SLICE_X12Y101.A5 net (fanout=154) 0.521 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/phy_init_data_sel SLICE_X12Y101.CLK Tah (-Th) 0.219 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r<108> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_mux0001<108>11 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_108 ------------------------------------------------- --------------------------- Total 0.716ns (0.195ns logic, 0.521ns route) (27.2% logic, 72.8% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_107 (SLICE_X15Y103.C5), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.278ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/u_ff_phy_init_data_sel (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_107 (FF) Requirement: 0.000ns Data Path Delay: 0.784ns (Levels of Logic = 1) Positive Clock Path Skew: 0.314ns (3.763 - 3.449) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clk90 rising at -2.813ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/u_ff_phy_init_data_sel to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_107 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X14Y98.AQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/phy_init_data_sel DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/u_ff_phy_init_data_sel SLICE_X15Y103.C5 net (fanout=154) 0.565 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/phy_init_data_sel SLICE_X15Y103.CLK Tah (-Th) 0.195 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r<107> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_mux0001<107>11 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_107 ------------------------------------------------- --------------------------- Total 0.784ns (0.219ns logic, 0.565ns route) (27.9% logic, 72.1% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_48 (SLICE_X10Y102.A4), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.375ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/u_ff_phy_init_data_sel (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_48 (FF) Requirement: 0.000ns Data Path Delay: 0.920ns (Levels of Logic = 1) Positive Clock Path Skew: 0.353ns (3.802 - 3.449) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clk90 rising at -2.813ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/u_ff_phy_init_data_sel to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_48 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X14Y98.AQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/phy_init_data_sel DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/u_ff_phy_init_data_sel SLICE_X10Y102.A4 net (fanout=154) 0.703 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/phy_init_data_sel SLICE_X10Y102.CLK Tah (-Th) 0.197 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r<48> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_mux0001<48>11 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_48 ------------------------------------------------- --------------------------- Total 0.920ns (0.217ns logic, 0.703ns route) (23.6% logic, 76.4% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_MC_PHY_INIT_DATA_SEL_90 = MAXDELAY FROM TIMEGRP "TNM_PHY_INIT_DATA_SEL" TO TIMEGRP "RAMS" TS_SYS_CLK * 4; For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612). 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_MC_GATE_DLY = MAXDELAY FROM TIMEGRP "TNM_GATE_DLY" TO TIMEGRP "FFS" TS_SYS_CLK * 4; For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612). 40 paths analyzed, 40 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 2.067ns. -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[5].gen_gate_base_dly_gt3.u_gate_srl_ff (SLICE_X0Y89.B2), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 12.933ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[25].u_ff_gate_dly (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[5].gen_gate_base_dly_gt3.u_gate_srl_ff (FF) Requirement: 15.000ns Data Path Delay: 1.586ns (Levels of Logic = 1) Clock Path Skew: -0.289ns (3.419 - 3.708) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[25].u_ff_gate_dly to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[5].gen_gate_base_dly_gt3.u_gate_srl_ff Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X3Y85.BQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_dly_r<27> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[25].u_ff_gate_dly SLICE_X0Y89.B2 net (fanout=1) 1.133 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_dly_r<25> SLICE_X0Y89.CLK Tas 0.003 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_srl_out_r<5> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[5].u_gate_srl DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[5].gen_gate_base_dly_gt3.u_gate_srl_ff ------------------------------------------------- --------------------------- Total 1.586ns (0.453ns logic, 1.133ns route) (28.6% logic, 71.4% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[1].gen_gate_base_dly_gt3.u_gate_srl_ff (SLICE_X0Y82.A2), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 13.040ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[5].u_ff_gate_dly (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[1].gen_gate_base_dly_gt3.u_gate_srl_ff (FF) Requirement: 15.000ns Data Path Delay: 1.467ns (Levels of Logic = 1) Clock Path Skew: -0.301ns (3.446 - 3.747) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[5].u_ff_gate_dly to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[1].gen_gate_base_dly_gt3.u_gate_srl_ff Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X2Y82.BQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_dly_r<7> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[5].u_ff_gate_dly SLICE_X0Y82.A2 net (fanout=1) 1.010 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_dly_r<5> SLICE_X0Y82.CLK Tas 0.007 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_srl_out_r<1> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[1].u_gate_srl DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[1].gen_gate_base_dly_gt3.u_gate_srl_ff ------------------------------------------------- --------------------------- Total 1.467ns (0.457ns logic, 1.010ns route) (31.2% logic, 68.8% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[1].gen_gate_base_dly_gt3.u_gate_srl_ff (SLICE_X0Y82.A3), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 13.063ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[6].u_ff_gate_dly (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[1].gen_gate_base_dly_gt3.u_gate_srl_ff (FF) Requirement: 15.000ns Data Path Delay: 1.444ns (Levels of Logic = 1) Clock Path Skew: -0.301ns (3.446 - 3.747) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[6].u_ff_gate_dly to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[1].gen_gate_base_dly_gt3.u_gate_srl_ff Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X2Y82.CQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_dly_r<7> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[6].u_ff_gate_dly SLICE_X0Y82.A3 net (fanout=1) 0.987 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_dly_r<6> SLICE_X0Y82.CLK Tas 0.007 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_srl_out_r<1> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[1].u_gate_srl DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[1].gen_gate_base_dly_gt3.u_gate_srl_ff ------------------------------------------------- --------------------------- Total 1.444ns (0.457ns logic, 0.987ns route) (31.6% logic, 68.4% route) -------------------------------------------------------------------------------- Hold Paths: TS_MC_GATE_DLY = MAXDELAY FROM TIMEGRP "TNM_GATE_DLY" TO TIMEGRP "FFS" TS_SYS_CLK * 4; -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[2].gen_gate_base_dly_gt3.u_gate_srl_ff (SLICE_X4Y80.A6), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.033ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[14].u_ff_gate_dly (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[2].gen_gate_base_dly_gt3.u_gate_srl_ff (FF) Requirement: 0.000ns Data Path Delay: 0.487ns (Levels of Logic = 1) Positive Clock Path Skew: 0.262ns (3.704 - 3.442) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 0.000ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[14].u_ff_gate_dly to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[2].gen_gate_base_dly_gt3.u_gate_srl_ff Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X4Y79.CQ Tcko 0.433 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_dly_r<15> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[14].u_ff_gate_dly SLICE_X4Y80.A6 net (fanout=1) 0.273 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_dly_r<14> SLICE_X4Y80.CLK Tah (-Th) 0.219 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_srl_out_r<2> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[2].u_gate_srl DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[2].gen_gate_base_dly_gt3.u_gate_srl_ff ------------------------------------------------- --------------------------- Total 0.487ns (0.214ns logic, 0.273ns route) (43.9% logic, 56.1% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[6].gen_gate_base_dly_gt3.u_gate_srl_ff (SLICE_X0Y89.A5), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.109ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[33].u_ff_gate_dly (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[6].gen_gate_base_dly_gt3.u_gate_srl_ff (FF) Requirement: 0.000ns Data Path Delay: 0.554ns (Levels of Logic = 1) Positive Clock Path Skew: 0.253ns (3.676 - 3.423) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 0.000ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[33].u_ff_gate_dly to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[6].gen_gate_base_dly_gt3.u_gate_srl_ff Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X3Y89.BQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_dly_r<35> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[33].u_ff_gate_dly SLICE_X0Y89.A5 net (fanout=1) 0.359 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_dly_r<33> SLICE_X0Y89.CLK Tah (-Th) 0.219 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_srl_out_r<5> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[6].u_gate_srl DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[6].gen_gate_base_dly_gt3.u_gate_srl_ff ------------------------------------------------- --------------------------- Total 0.554ns (0.195ns logic, 0.359ns route) (35.2% logic, 64.8% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[2].gen_gate_base_dly_gt3.u_gate_srl_ff (SLICE_X4Y80.A5), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.113ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[13].u_ff_gate_dly (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[2].gen_gate_base_dly_gt3.u_gate_srl_ff (FF) Requirement: 0.000ns Data Path Delay: 0.567ns (Levels of Logic = 1) Positive Clock Path Skew: 0.262ns (3.704 - 3.442) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 0.000ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[13].u_ff_gate_dly to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[2].gen_gate_base_dly_gt3.u_gate_srl_ff Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X4Y79.BQ Tcko 0.433 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_dly_r<15> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[13].u_ff_gate_dly SLICE_X4Y80.A5 net (fanout=1) 0.353 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_dly_r<13> SLICE_X4Y80.CLK Tah (-Th) 0.219 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_srl_out_r<2> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[2].u_gate_srl DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[2].gen_gate_base_dly_gt3.u_gate_srl_ff ------------------------------------------------- --------------------------- Total 0.567ns (0.214ns logic, 0.353ns route) (37.7% logic, 62.3% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_MC_RDEN_DLY = MAXDELAY FROM TIMEGRP "TNM_RDEN_DLY" TO TIMEGRP "FFS" TS_SYS_CLK * 4; For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612). 5 paths analyzed, 5 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 1.917ns. -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r (SLICE_X60Y94.A2), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 13.083ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden_dly[0].u_ff_rden_dly (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r (FF) Requirement: 15.000ns Data Path Delay: 1.472ns (Levels of Logic = 1) Clock Path Skew: -0.253ns (3.336 - 3.589) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden_dly[0].u_ff_rden_dly to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X63Y94.AQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rden_dly_r<3> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden_dly[0].u_ff_rden_dly SLICE_X60Y94.A2 net (fanout=1) 1.015 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rden_dly_r<0> SLICE_X60Y94.CLK Tas 0.007 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/phy_calib_rden<0> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_rden_srl DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r ------------------------------------------------- --------------------------- Total 1.472ns (0.457ns logic, 1.015ns route) (31.0% logic, 69.0% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r (SLICE_X60Y94.A3), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 13.259ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden_dly[1].u_ff_rden_dly (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r (FF) Requirement: 15.000ns Data Path Delay: 1.296ns (Levels of Logic = 1) Clock Path Skew: -0.253ns (3.336 - 3.589) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden_dly[1].u_ff_rden_dly to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X63Y94.BQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rden_dly_r<3> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden_dly[1].u_ff_rden_dly SLICE_X60Y94.A3 net (fanout=1) 0.839 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rden_dly_r<1> SLICE_X60Y94.CLK Tas 0.007 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/phy_calib_rden<0> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_rden_srl DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r ------------------------------------------------- --------------------------- Total 1.296ns (0.457ns logic, 0.839ns route) (35.3% logic, 64.7% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r (SLICE_X60Y94.A4), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 13.407ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden_dly[2].u_ff_rden_dly (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r (FF) Requirement: 15.000ns Data Path Delay: 1.148ns (Levels of Logic = 1) Clock Path Skew: -0.253ns (3.336 - 3.589) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden_dly[2].u_ff_rden_dly to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X63Y94.CQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rden_dly_r<3> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden_dly[2].u_ff_rden_dly SLICE_X60Y94.A4 net (fanout=1) 0.691 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rden_dly_r<2> SLICE_X60Y94.CLK Tas 0.007 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/phy_calib_rden<0> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_rden_srl DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r ------------------------------------------------- --------------------------- Total 1.148ns (0.457ns logic, 0.691ns route) (39.8% logic, 60.2% route) -------------------------------------------------------------------------------- Hold Paths: TS_MC_RDEN_DLY = MAXDELAY FROM TIMEGRP "TNM_RDEN_DLY" TO TIMEGRP "FFS" TS_SYS_CLK * 4; -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r (SLICE_X60Y94.A5), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.170ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden_dly[3].u_ff_rden_dly (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r (FF) Requirement: 0.000ns Data Path Delay: 0.610ns (Levels of Logic = 1) Positive Clock Path Skew: 0.248ns (3.586 - 3.338) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 0.000ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden_dly[3].u_ff_rden_dly to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X63Y94.DQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rden_dly_r<3> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden_dly[3].u_ff_rden_dly SLICE_X60Y94.A5 net (fanout=1) 0.415 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rden_dly_r<3> SLICE_X60Y94.CLK Tah (-Th) 0.219 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/phy_calib_rden<0> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_rden_srl DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r ------------------------------------------------- --------------------------- Total 0.610ns (0.195ns logic, 0.415ns route) (32.0% logic, 68.0% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r (SLICE_X60Y94.A6), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.192ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden_dly[4].u_ff_rden_dly (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r (FF) Requirement: 0.000ns Data Path Delay: 0.639ns (Levels of Logic = 1) Positive Clock Path Skew: 0.255ns (3.586 - 3.331) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 0.000ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden_dly[4].u_ff_rden_dly to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X60Y93.AQ Tcko 0.433 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rden_dly_r<4> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden_dly[4].u_ff_rden_dly SLICE_X60Y94.A6 net (fanout=1) 0.425 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rden_dly_r<4> SLICE_X60Y94.CLK Tah (-Th) 0.219 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/phy_calib_rden<0> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_rden_srl DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r ------------------------------------------------- --------------------------- Total 0.639ns (0.214ns logic, 0.425ns route) (33.5% logic, 66.5% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r (SLICE_X60Y94.A4), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.391ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden_dly[2].u_ff_rden_dly (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r (FF) Requirement: 0.000ns Data Path Delay: 0.831ns (Levels of Logic = 1) Positive Clock Path Skew: 0.248ns (3.586 - 3.338) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 0.000ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden_dly[2].u_ff_rden_dly to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X63Y94.CQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rden_dly_r<3> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden_dly[2].u_ff_rden_dly SLICE_X60Y94.A4 net (fanout=1) 0.636 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rden_dly_r<2> SLICE_X60Y94.CLK Tah (-Th) 0.219 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/phy_calib_rden<0> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_rden_srl DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_rden[0].u_calib_rden_r ------------------------------------------------- --------------------------- Total 0.831ns (0.195ns logic, 0.636ns route) (23.5% logic, 76.5% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_MC_CAL_RDEN_DLY = MAXDELAY FROM TIMEGRP "TNM_CAL_RDEN_DLY" TO TIMEGRP "FFS" TS_SYS_CLK * 4; For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612). 5 paths analyzed, 5 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 1.844ns. -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r (SLICE_X16Y101.A2), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 13.156ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_cal_rden_dly[0].u_ff_cal_rden_dly (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r (FF) Requirement: 15.000ns Data Path Delay: 1.389ns (Levels of Logic = 1) Clock Path Skew: -0.263ns (3.496 - 3.759) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_cal_rden_dly[0].u_ff_cal_rden_dly to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X17Y101.AQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_srl_a_r<3> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_cal_rden_dly[0].u_ff_cal_rden_dly SLICE_X16Y101.A2 net (fanout=1) 0.932 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_srl_a_r<0> SLICE_X16Y101.CLK Tas 0.007 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_srl_out_r DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r ------------------------------------------------- --------------------------- Total 1.389ns (0.457ns logic, 0.932ns route) (32.9% logic, 67.1% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r (SLICE_X16Y101.A4), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 13.394ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_cal_rden_dly[2].u_ff_cal_rden_dly (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r (FF) Requirement: 15.000ns Data Path Delay: 1.151ns (Levels of Logic = 1) Clock Path Skew: -0.263ns (3.496 - 3.759) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_cal_rden_dly[2].u_ff_cal_rden_dly to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X17Y101.CQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_srl_a_r<3> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_cal_rden_dly[2].u_ff_cal_rden_dly SLICE_X16Y101.A4 net (fanout=1) 0.694 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_srl_a_r<2> SLICE_X16Y101.CLK Tas 0.007 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_srl_out_r DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r ------------------------------------------------- --------------------------- Total 1.151ns (0.457ns logic, 0.694ns route) (39.7% logic, 60.3% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r (SLICE_X16Y101.A3), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 13.483ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_cal_rden_dly[1].u_ff_cal_rden_dly (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r (FF) Requirement: 15.000ns Data Path Delay: 1.062ns (Levels of Logic = 1) Clock Path Skew: -0.263ns (3.496 - 3.759) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_cal_rden_dly[1].u_ff_cal_rden_dly to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X17Y101.BQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_srl_a_r<3> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_cal_rden_dly[1].u_ff_cal_rden_dly SLICE_X16Y101.A3 net (fanout=1) 0.605 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_srl_a_r<1> SLICE_X16Y101.CLK Tas 0.007 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_srl_out_r DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r ------------------------------------------------- --------------------------- Total 1.062ns (0.457ns logic, 0.605ns route) (43.0% logic, 57.0% route) -------------------------------------------------------------------------------- Hold Paths: TS_MC_CAL_RDEN_DLY = MAXDELAY FROM TIMEGRP "TNM_CAL_RDEN_DLY" TO TIMEGRP "FFS" TS_SYS_CLK * 4; -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r (SLICE_X16Y101.A6), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.146ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_cal_rden_dly[4].u_ff_cal_rden_dly (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r (FF) Requirement: 0.000ns Data Path Delay: 0.606ns (Levels of Logic = 1) Positive Clock Path Skew: 0.268ns (3.759 - 3.491) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 0.000ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_cal_rden_dly[4].u_ff_cal_rden_dly to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X19Y102.CQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_srl_a_r<4> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_cal_rden_dly[4].u_ff_cal_rden_dly SLICE_X16Y101.A6 net (fanout=1) 0.411 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_srl_a_r<4> SLICE_X16Y101.CLK Tah (-Th) 0.219 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_srl_out_r DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r ------------------------------------------------- --------------------------- Total 0.606ns (0.195ns logic, 0.411ns route) (32.2% logic, 67.8% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r (SLICE_X16Y101.A5), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.258ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_cal_rden_dly[3].u_ff_cal_rden_dly (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r (FF) Requirement: 0.000ns Data Path Delay: 0.713ns (Levels of Logic = 1) Positive Clock Path Skew: 0.263ns (3.759 - 3.496) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 0.000ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_cal_rden_dly[3].u_ff_cal_rden_dly to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X17Y101.DQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_srl_a_r<3> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_cal_rden_dly[3].u_ff_cal_rden_dly SLICE_X16Y101.A5 net (fanout=1) 0.518 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_srl_a_r<3> SLICE_X16Y101.CLK Tah (-Th) 0.219 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_srl_out_r DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r ------------------------------------------------- --------------------------- Total 0.713ns (0.195ns logic, 0.518ns route) (27.3% logic, 72.7% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r (SLICE_X16Y101.A3), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.297ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_cal_rden_dly[1].u_ff_cal_rden_dly (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r (FF) Requirement: 0.000ns Data Path Delay: 0.752ns (Levels of Logic = 1) Positive Clock Path Skew: 0.263ns (3.759 - 3.496) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 0.000ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_cal_rden_dly[1].u_ff_cal_rden_dly to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X17Y101.BQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_srl_a_r<3> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_cal_rden_dly[1].u_ff_cal_rden_dly SLICE_X16Y101.A3 net (fanout=1) 0.557 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_srl_a_r<1> SLICE_X16Y101.CLK Tah (-Th) 0.219 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_srl_out_r DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/u_calib_rden_srl_out_r ------------------------------------------------- --------------------------- Total 0.752ns (0.195ns logic, 0.557ns route) (25.9% logic, 74.1% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_FROM_EN_DQS_FF_TO_DQ_CE_FF = MAXDELAY FROM TIMEGRP "EN_DQS_FF" TO TIMEGRP "TNM_DQ_CE_IDDR" 3.85 ns DATAPATHONLY; For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612). 8 paths analyzed, 8 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Maximum delay is 2.693ns. -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce (ILOGIC_X0Y102.DDLY), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 1.157ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[4].u_en_dqs_ff (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce (FF) Requirement: 3.850ns Data Path Delay: 2.693ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: u_clk0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4> falling Clock Uncertainty: 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[4].u_en_dqs_ff to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce Location Delay type Delay(ns) Physical Resource Logical Resource(s) --------------------------------------------------- ------------------- SLICE_X0Y51.DQ Tcko 0.471 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<4> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[4].u_en_dqs_ff IODELAY_X0Y102.DATAIN net (fanout=1) 0.532 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<4> IODELAY_X0Y102.DATAOUT Tioddo_DATAIN 1.338 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iodelay_dq_ce DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iodelay_dq_ce ILOGIC_X0Y102.DDLY net (fanout=2) 0.000 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/en_dqs_sync ILOGIC_X0Y102.CLK Tidockd 0.352 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<4> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce --------------------------------------------------- --------------------------- Total 2.693ns (2.161ns logic, 0.532ns route) (80.2% logic, 19.8% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce (ILOGIC_X0Y58.DDLY), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 1.160ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[1].u_en_dqs_ff (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce (FF) Requirement: 3.850ns Data Path Delay: 2.690ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: u_clk0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1> falling Clock Uncertainty: 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[1].u_en_dqs_ff to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X0Y29.DQ Tcko 0.471 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<1> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[1].u_en_dqs_ff IODELAY_X0Y58.DATAIN net (fanout=1) 0.529 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<1> IODELAY_X0Y58.DATAOUTTioddo_DATAIN 1.338 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce ILOGIC_X0Y58.DDLY net (fanout=2) 0.000 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/en_dqs_sync ILOGIC_X0Y58.CLK Tidockd 0.352 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<1> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce ------------------------------------------------- --------------------------- Total 2.690ns (2.161ns logic, 0.529ns route) (80.3% logic, 19.7% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce (ILOGIC_X0Y262.DDLY), 1 path -------------------------------------------------------------------------------- Slack (setup paths): 1.160ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[7].u_en_dqs_ff (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce (FF) Requirement: 3.850ns Data Path Delay: 2.690ns (Levels of Logic = 1) Clock Path Skew: 0.000ns Source Clock: u_clk0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7> falling Clock Uncertainty: 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[7].u_en_dqs_ff to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce Location Delay type Delay(ns) Physical Resource Logical Resource(s) --------------------------------------------------- ------------------- SLICE_X0Y131.DQ Tcko 0.471 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<7> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[7].u_en_dqs_ff IODELAY_X0Y262.DATAIN net (fanout=1) 0.529 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<7> IODELAY_X0Y262.DATAOUT Tioddo_DATAIN 1.338 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce ILOGIC_X0Y262.DDLY net (fanout=2) 0.000 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/en_dqs_sync ILOGIC_X0Y262.CLK Tidockd 0.352 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<7> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce --------------------------------------------------- --------------------------- Total 2.690ns (2.161ns logic, 0.529ns route) (80.3% logic, 19.7% route) -------------------------------------------------------------------------------- Hold Paths: TS_FROM_EN_DQS_FF_TO_DQ_CE_FF = MAXDELAY FROM TIMEGRP "EN_DQS_FF" TO TIMEGRP "TNM_DQ_CE_IDDR" 3.85 ns DATAPATHONLY; -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce (ILOGIC_X0Y58.DDLY), 1 path -------------------------------------------------------------------------------- Slack (hold path): 2.763ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[1].u_en_dqs_ff (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce (FF) Requirement: 0.000ns Data Path Delay: 2.763ns (Levels of Logic = 1) Positive Clock Path Skew: 0.000ns Source Clock: u_clk0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<1> falling Clock Uncertainty: 0.000ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[1].u_en_dqs_ff to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X0Y29.DQ Tcko 0.433 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<1> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[1].u_en_dqs_ff IODELAY_X0Y58.DATAIN net (fanout=1) 0.487 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<1> IODELAY_X0Y58.DATAOUTTioddo_DATAIN 1.728 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce ILOGIC_X0Y58.DDLY net (fanout=2) 0.000 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/en_dqs_sync ILOGIC_X0Y58.CLK Tiockdd (-Th) -0.115 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<1> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iddr_dq_ce ------------------------------------------------- --------------------------- Total 2.763ns (2.276ns logic, 0.487ns route) (82.4% logic, 17.6% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce (ILOGIC_X0Y262.DDLY), 1 path -------------------------------------------------------------------------------- Slack (hold path): 2.763ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[7].u_en_dqs_ff (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce (FF) Requirement: 0.000ns Data Path Delay: 2.763ns (Levels of Logic = 1) Positive Clock Path Skew: 0.000ns Source Clock: u_clk0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<7> falling Clock Uncertainty: 0.000ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[7].u_en_dqs_ff to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce Location Delay type Delay(ns) Physical Resource Logical Resource(s) --------------------------------------------------- ------------------- SLICE_X0Y131.DQ Tcko 0.433 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<7> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[7].u_en_dqs_ff IODELAY_X0Y262.DATAIN net (fanout=1) 0.487 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<7> IODELAY_X0Y262.DATAOUT Tioddo_DATAIN 1.728 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iodelay_dq_ce ILOGIC_X0Y262.DDLY net (fanout=2) 0.000 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/en_dqs_sync ILOGIC_X0Y262.CLK Tiockdd (-Th) -0.115 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<7> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[7].u_iob_dqs/u_iddr_dq_ce --------------------------------------------------- --------------------------- Total 2.763ns (2.276ns logic, 0.487ns route) (82.4% logic, 17.6% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce (ILOGIC_X0Y62.DDLY), 1 path -------------------------------------------------------------------------------- Slack (hold path): 2.763ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[2].u_en_dqs_ff (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce (FF) Requirement: 0.000ns Data Path Delay: 2.763ns (Levels of Logic = 1) Positive Clock Path Skew: 0.000ns Source Clock: u_clk0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<2> falling Clock Uncertainty: 0.000ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[2].u_en_dqs_ff to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X0Y31.DQ Tcko 0.433 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<2> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate[2].u_en_dqs_ff IODELAY_X0Y62.DATAIN net (fanout=1) 0.487 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/en_dqs<2> IODELAY_X0Y62.DATAOUTTioddo_DATAIN 1.728 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_iodelay_dq_ce ILOGIC_X0Y62.DDLY net (fanout=2) 0.000 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/en_dqs_sync ILOGIC_X0Y62.CLK Tiockdd (-Th) -0.115 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<2> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[2].u_iob_dqs/u_iddr_dq_ce ------------------------------------------------- --------------------------- Total 2.763ns (2.276ns logic, 0.487ns route) (82.4% logic, 17.6% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_DQ_CE = MAXDELAY FROM TIMEGRP "TNM_DQ_CE_IDDR" TO TIMEGRP "TNM_DQS_FLOPS" 1.9 ns; For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612). 128 paths analyzed, 64 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum period is 3.684ns. Maximum delay is 1.866ns. -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[40].u_iob_dq/gen_stg2_sg1.u_iddr_dq (ILOGIC_X0Y241.CE1), 2 paths -------------------------------------------------------------------------------- Slack (setup paths): 0.034ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[40].u_iob_dq/gen_stg2_sg1.u_iddr_dq (FF) Requirement: 1.900ns Data Path Delay: 1.909ns (Levels of Logic = 0) Clock Path Skew: 0.078ns (0.301 - 0.223) Source Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5> falling Destination Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5> falling Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[40].u_iob_dq/gen_stg2_sg1.u_iddr_dq Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- ILOGIC_X0Y256.Q1 Tickq 0.517 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<5> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce ILOGIC_X0Y241.CE1 net (fanout=8) 0.811 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<5> ILOGIC_X0Y241.CLK Tice1ck 0.581 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[40].u_iob_dq/stg1_out_fall_sg1 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[40].u_iob_dq/gen_stg2_sg1.u_iddr_dq ------------------------------------------------- --------------------------- Total 1.909ns (1.098ns logic, 0.811ns route) (57.5% logic, 42.5% route) -------------------------------------------------------------------------------- Slack (setup paths): 0.058ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[40].u_iob_dq/gen_stg2_sg1.u_iddr_dq (FF) Requirement: 1.900ns Data Path Delay: 1.885ns (Levels of Logic = 0) Clock Path Skew: 0.078ns (0.301 - 0.223) Source Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5> falling Destination Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5> rising Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[40].u_iob_dq/gen_stg2_sg1.u_iddr_dq Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- ILOGIC_X0Y256.Q1 Tickq 0.517 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<5> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce ILOGIC_X0Y241.CE1 net (fanout=8) 0.811 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<5> ILOGIC_X0Y241.CLKB Tice1ck 0.557 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[40].u_iob_dq/stg1_out_fall_sg1 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[40].u_iob_dq/gen_stg2_sg1.u_iddr_dq ------------------------------------------------- --------------------------- Total 1.885ns (1.074ns logic, 0.811ns route) (57.0% logic, 43.0% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[44].u_iob_dq/gen_stg2_sg1.u_iddr_dq (ILOGIC_X0Y240.CE1), 2 paths -------------------------------------------------------------------------------- Slack (setup paths): 0.034ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[44].u_iob_dq/gen_stg2_sg1.u_iddr_dq (FF) Requirement: 1.900ns Data Path Delay: 1.909ns (Levels of Logic = 0) Clock Path Skew: 0.078ns (0.301 - 0.223) Source Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5> falling Destination Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5> falling Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[44].u_iob_dq/gen_stg2_sg1.u_iddr_dq Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- ILOGIC_X0Y256.Q1 Tickq 0.517 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<5> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce ILOGIC_X0Y240.CE1 net (fanout=8) 0.811 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<5> ILOGIC_X0Y240.CLK Tice1ck 0.581 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[44].u_iob_dq/stg1_out_fall_sg1 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[44].u_iob_dq/gen_stg2_sg1.u_iddr_dq ------------------------------------------------- --------------------------- Total 1.909ns (1.098ns logic, 0.811ns route) (57.5% logic, 42.5% route) -------------------------------------------------------------------------------- Slack (setup paths): 0.058ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[44].u_iob_dq/gen_stg2_sg1.u_iddr_dq (FF) Requirement: 1.900ns Data Path Delay: 1.885ns (Levels of Logic = 0) Clock Path Skew: 0.078ns (0.301 - 0.223) Source Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5> falling Destination Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5> rising Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[44].u_iob_dq/gen_stg2_sg1.u_iddr_dq Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- ILOGIC_X0Y256.Q1 Tickq 0.517 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<5> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce ILOGIC_X0Y240.CE1 net (fanout=8) 0.811 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<5> ILOGIC_X0Y240.CLKB Tice1ck 0.557 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[44].u_iob_dq/stg1_out_fall_sg1 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[44].u_iob_dq/gen_stg2_sg1.u_iddr_dq ------------------------------------------------- --------------------------- Total 1.885ns (1.074ns logic, 0.811ns route) (57.0% logic, 43.0% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[47].u_iob_dq/gen_stg2_sg1.u_iddr_dq (ILOGIC_X0Y248.CE1), 2 paths -------------------------------------------------------------------------------- Slack (setup paths): 0.051ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[47].u_iob_dq/gen_stg2_sg1.u_iddr_dq (FF) Requirement: 1.900ns Data Path Delay: 1.863ns (Levels of Logic = 0) Clock Path Skew: 0.049ns (0.272 - 0.223) Source Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5> falling Destination Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5> falling Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[47].u_iob_dq/gen_stg2_sg1.u_iddr_dq Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- ILOGIC_X0Y256.Q1 Tickq 0.517 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<5> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce ILOGIC_X0Y248.CE1 net (fanout=8) 0.765 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<5> ILOGIC_X0Y248.CLK Tice1ck 0.581 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[47].u_iob_dq/stg1_out_fall_sg1 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[47].u_iob_dq/gen_stg2_sg1.u_iddr_dq ------------------------------------------------- --------------------------- Total 1.863ns (1.098ns logic, 0.765ns route) (58.9% logic, 41.1% route) -------------------------------------------------------------------------------- Slack (setup paths): 0.075ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[47].u_iob_dq/gen_stg2_sg1.u_iddr_dq (FF) Requirement: 1.900ns Data Path Delay: 1.839ns (Levels of Logic = 0) Clock Path Skew: 0.049ns (0.272 - 0.223) Source Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5> falling Destination Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<5> rising Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[47].u_iob_dq/gen_stg2_sg1.u_iddr_dq Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- ILOGIC_X0Y256.Q1 Tickq 0.517 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<5> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[5].u_iob_dqs/u_iddr_dq_ce ILOGIC_X0Y248.CE1 net (fanout=8) 0.765 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<5> ILOGIC_X0Y248.CLKB Tice1ck 0.557 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[47].u_iob_dq/stg1_out_fall_sg1 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[47].u_iob_dq/gen_stg2_sg1.u_iddr_dq ------------------------------------------------- --------------------------- Total 1.839ns (1.074ns logic, 0.765ns route) (58.4% logic, 41.6% route) -------------------------------------------------------------------------------- Hold Paths: TS_DQ_CE = MAXDELAY FROM TIMEGRP "TNM_DQ_CE_IDDR" TO TIMEGRP "TNM_DQS_FLOPS" 1.9 ns; -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[51].u_iob_dq/gen_stg2_sg1.u_iddr_dq (ILOGIC_X0Y267.CE1), 2 paths -------------------------------------------------------------------------------- Slack (hold path): 1.004ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[51].u_iob_dq/gen_stg2_sg1.u_iddr_dq (FF) Requirement: 0.000ns Data Path Delay: 1.085ns (Levels of Logic = 0) Positive Clock Path Skew: 0.081ns (0.264 - 0.183) Source Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6> falling Destination Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6> rising Clock Uncertainty: 0.000ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[51].u_iob_dq/gen_stg2_sg1.u_iddr_dq Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- ILOGIC_X0Y260.Q1 Tickq 0.476 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<6> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce ILOGIC_X0Y267.CE1 net (fanout=8) 0.348 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<6> ILOGIC_X0Y267.CLKB Tickce1 (-Th) -0.261 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[51].u_iob_dq/stg1_out_fall_sg1 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[51].u_iob_dq/gen_stg2_sg1.u_iddr_dq ------------------------------------------------- --------------------------- Total 1.085ns (0.737ns logic, 0.348ns route) (67.9% logic, 32.1% route) -------------------------------------------------------------------------------- Slack (hold path): 1.030ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[51].u_iob_dq/gen_stg2_sg1.u_iddr_dq (FF) Requirement: 0.000ns Data Path Delay: 1.111ns (Levels of Logic = 0) Positive Clock Path Skew: 0.081ns (0.264 - 0.183) Source Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6> falling Destination Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6> falling Clock Uncertainty: 0.000ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[51].u_iob_dq/gen_stg2_sg1.u_iddr_dq Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- ILOGIC_X0Y260.Q1 Tickq 0.476 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<6> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce ILOGIC_X0Y267.CE1 net (fanout=8) 0.348 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<6> ILOGIC_X0Y267.CLK Tickce1 (-Th) -0.287 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[51].u_iob_dq/stg1_out_fall_sg1 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[51].u_iob_dq/gen_stg2_sg1.u_iddr_dq ------------------------------------------------- --------------------------- Total 1.111ns (0.763ns logic, 0.348ns route) (68.7% logic, 31.3% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[54].u_iob_dq/gen_stg2_sg1.u_iddr_dq (ILOGIC_X0Y266.CE1), 2 paths -------------------------------------------------------------------------------- Slack (hold path): 1.004ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[54].u_iob_dq/gen_stg2_sg1.u_iddr_dq (FF) Requirement: 0.000ns Data Path Delay: 1.085ns (Levels of Logic = 0) Positive Clock Path Skew: 0.081ns (0.264 - 0.183) Source Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6> falling Destination Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6> rising Clock Uncertainty: 0.000ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[54].u_iob_dq/gen_stg2_sg1.u_iddr_dq Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- ILOGIC_X0Y260.Q1 Tickq 0.476 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<6> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce ILOGIC_X0Y266.CE1 net (fanout=8) 0.348 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<6> ILOGIC_X0Y266.CLKB Tickce1 (-Th) -0.261 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[54].u_iob_dq/stg1_out_fall_sg1 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[54].u_iob_dq/gen_stg2_sg1.u_iddr_dq ------------------------------------------------- --------------------------- Total 1.085ns (0.737ns logic, 0.348ns route) (67.9% logic, 32.1% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[54].u_iob_dq/gen_stg2_sg1.u_iddr_dq (ILOGIC_X0Y266.CE1), 2 paths -------------------------------------------------------------------------------- Slack (hold path): 1.030ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[54].u_iob_dq/gen_stg2_sg1.u_iddr_dq (FF) Requirement: 0.000ns Data Path Delay: 1.111ns (Levels of Logic = 0) Positive Clock Path Skew: 0.081ns (0.264 - 0.183) Source Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6> falling Destination Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<6> falling Clock Uncertainty: 0.000ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[54].u_iob_dq/gen_stg2_sg1.u_iddr_dq Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- ILOGIC_X0Y260.Q1 Tickq 0.476 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<6> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[6].u_iob_dqs/u_iddr_dq_ce ILOGIC_X0Y266.CE1 net (fanout=8) 0.348 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<6> ILOGIC_X0Y266.CLK Tickce1 (-Th) -0.287 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[54].u_iob_dq/stg1_out_fall_sg1 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[54].u_iob_dq/gen_stg2_sg1.u_iddr_dq ------------------------------------------------- --------------------------- Total 1.111ns (0.763ns logic, 0.348ns route) (68.7% logic, 31.3% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[36].u_iob_dq/gen_stg2_sg1.u_iddr_dq (ILOGIC_X0Y109.CE1), 2 paths -------------------------------------------------------------------------------- Slack (hold path): 1.006ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[36].u_iob_dq/gen_stg2_sg1.u_iddr_dq (FF) Requirement: 0.000ns Data Path Delay: 1.078ns (Levels of Logic = 0) Positive Clock Path Skew: 0.072ns (0.279 - 0.207) Source Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4> falling Destination Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4> rising Clock Uncertainty: 0.000ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[36].u_iob_dq/gen_stg2_sg1.u_iddr_dq Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- ILOGIC_X0Y102.Q1 Tickq 0.476 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<4> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce ILOGIC_X0Y109.CE1 net (fanout=8) 0.341 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<4> ILOGIC_X0Y109.CLKB Tickce1 (-Th) -0.261 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[36].u_iob_dq/stg1_out_fall_sg1 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[36].u_iob_dq/gen_stg2_sg1.u_iddr_dq ------------------------------------------------- --------------------------- Total 1.078ns (0.737ns logic, 0.341ns route) (68.4% logic, 31.6% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[36].u_iob_dq/gen_stg2_sg1.u_iddr_dq (ILOGIC_X0Y109.CE1), 2 paths -------------------------------------------------------------------------------- Slack (hold path): 1.032ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[36].u_iob_dq/gen_stg2_sg1.u_iddr_dq (FF) Requirement: 0.000ns Data Path Delay: 1.104ns (Levels of Logic = 0) Positive Clock Path Skew: 0.072ns (0.279 - 0.207) Source Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4> falling Destination Clock: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/delayed_dqs<4> falling Clock Uncertainty: 0.000ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[36].u_iob_dq/gen_stg2_sg1.u_iddr_dq Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- ILOGIC_X0Y102.Q1 Tickq 0.476 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<4> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_iddr_dq_ce ILOGIC_X0Y109.CE1 net (fanout=8) 0.341 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/dq_ce<4> ILOGIC_X0Y109.CLK Tickce1 (-Th) -0.287 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[36].u_iob_dq/stg1_out_fall_sg1 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[36].u_iob_dq/gen_stg2_sg1.u_iddr_dq ------------------------------------------------- --------------------------- Total 1.104ns (0.763ns logic, 0.341ns route) (69.1% logic, 30.9% route) -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_DDR2_RAM_CORE_u_ddr2_infrastructure_clk0_bufg_in = PERIOD TIMEGRP "DDR2_RAM_CORE_u_ddr2_infrastructure_clk0_bufg_in" TS_SYS_CLK HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 28579 paths analyzed, 4285 endpoints analyzed, 44 failing endpoints 44 timing errors detected. (44 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 4.640ns. -------------------------------------------------------------------------------- Paths for end point u_DDR2_Control/u_DDR2_Address/read_addr_24 (SLICE_X62Y120.B5), 552 paths -------------------------------------------------------------------------------- Slack (setup path): -0.890ns (requirement - (data path - clock path skew + uncertainty)) Source: u_DDR2_Control/u_DDR2_Address/read_addr_5 (FF) Destination: u_DDR2_Control/u_DDR2_Address/read_addr_24 (FF) Requirement: 3.750ns Data Path Delay: 4.569ns (Levels of Logic = 9) Clock Path Skew: -0.006ns (1.429 - 1.435) Source Clock: u_clk0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.065ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.108ns Phase Error (PE): 0.000ns Maximum Data Path: u_DDR2_Control/u_DDR2_Address/read_addr_5 to u_DDR2_Control/u_DDR2_Address/read_addr_24 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X64Y117.CQ Tcko 0.471 u_DDR2_Control/u_DDR2_Address/read_addr<6> u_DDR2_Control/u_DDR2_Address/read_addr_5 SLICE_X64Y118.A1 net (fanout=5) 0.913 u_DDR2_Control/u_DDR2_Address/read_addr<5> SLICE_X64Y118.COUT Topcya 0.499 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_lut<0>1 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> SLICE_X64Y119.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> SLICE_X64Y119.AMUX Tcina 0.310 u_DDR2_Control/u_DDR2_Address/N2 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<4> SLICE_X65Y117.C5 net (fanout=26) 0.638 u_DDR2_Control/u_DDR2_Address/read_active_cmp_eq0002 SLICE_X65Y117.COUT Topcyc 0.423 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> u_DDR2_Control/u_DDR2_Address/read_addr_mux0001<4>1 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> SLICE_X65Y118.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> SLICE_X65Y118.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> SLICE_X65Y119.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> SLICE_X65Y119.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> SLICE_X65Y120.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> SLICE_X65Y120.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> SLICE_X65Y121.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> SLICE_X65Y121.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> SLICE_X65Y122.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> SLICE_X65Y122.CMUX Tcinc 0.334 u_DDR2_Control/u_DDR2_Address/read_addr_share0000<24> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_xor<24> SLICE_X62Y120.B5 net (fanout=1) 0.538 u_DDR2_Control/u_DDR2_Address/read_addr_share0000<24> SLICE_X62Y120.CLK Tas 0.027 u_DDR2_Control/u_DDR2_Address/read_active u_DDR2_Control/u_DDR2_Address/read_addr_mux0000<24>1 u_DDR2_Control/u_DDR2_Address/read_addr_24 ------------------------------------------------- --------------------------- Total 4.569ns (2.480ns logic, 2.089ns route) (54.3% logic, 45.7% route) -------------------------------------------------------------------------------- Slack (setup path): -0.872ns (requirement - (data path - clock path skew + uncertainty)) Source: u_DDR2_Control/u_DDR2_Address/read_addr_6 (FF) Destination: u_DDR2_Control/u_DDR2_Address/read_addr_24 (FF) Requirement: 3.750ns Data Path Delay: 4.551ns (Levels of Logic = 9) Clock Path Skew: -0.006ns (1.429 - 1.435) Source Clock: u_clk0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.065ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.108ns Phase Error (PE): 0.000ns Maximum Data Path: u_DDR2_Control/u_DDR2_Address/read_addr_6 to u_DDR2_Control/u_DDR2_Address/read_addr_24 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X64Y117.DQ Tcko 0.471 u_DDR2_Control/u_DDR2_Address/read_addr<6> u_DDR2_Control/u_DDR2_Address/read_addr_6 SLICE_X64Y118.B1 net (fanout=5) 0.911 u_DDR2_Control/u_DDR2_Address/read_addr<6> SLICE_X64Y118.COUT Topcyb 0.483 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_lut<1> u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> SLICE_X64Y119.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> SLICE_X64Y119.AMUX Tcina 0.310 u_DDR2_Control/u_DDR2_Address/N2 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<4> SLICE_X65Y117.C5 net (fanout=26) 0.638 u_DDR2_Control/u_DDR2_Address/read_active_cmp_eq0002 SLICE_X65Y117.COUT Topcyc 0.423 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> u_DDR2_Control/u_DDR2_Address/read_addr_mux0001<4>1 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> SLICE_X65Y118.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> SLICE_X65Y118.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> SLICE_X65Y119.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> SLICE_X65Y119.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> SLICE_X65Y120.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> SLICE_X65Y120.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> SLICE_X65Y121.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> SLICE_X65Y121.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> SLICE_X65Y122.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> SLICE_X65Y122.CMUX Tcinc 0.334 u_DDR2_Control/u_DDR2_Address/read_addr_share0000<24> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_xor<24> SLICE_X62Y120.B5 net (fanout=1) 0.538 u_DDR2_Control/u_DDR2_Address/read_addr_share0000<24> SLICE_X62Y120.CLK Tas 0.027 u_DDR2_Control/u_DDR2_Address/read_active u_DDR2_Control/u_DDR2_Address/read_addr_mux0000<24>1 u_DDR2_Control/u_DDR2_Address/read_addr_24 ------------------------------------------------- --------------------------- Total 4.551ns (2.464ns logic, 2.087ns route) (54.1% logic, 45.9% route) -------------------------------------------------------------------------------- Slack (setup path): -0.864ns (requirement - (data path - clock path skew + uncertainty)) Source: u_DDR2_Control/u_DDR2_Address/read_addr_14 (FF) Destination: u_DDR2_Control/u_DDR2_Address/read_addr_24 (FF) Requirement: 3.750ns Data Path Delay: 4.503ns (Levels of Logic = 9) Clock Path Skew: -0.046ns (1.429 - 1.475) Source Clock: u_clk0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.065ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.108ns Phase Error (PE): 0.000ns Maximum Data Path: u_DDR2_Control/u_DDR2_Address/read_addr_14 to u_DDR2_Control/u_DDR2_Address/read_addr_24 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X66Y119.DQ Tcko 0.450 u_DDR2_Control/u_DDR2_Address/read_addr<14> u_DDR2_Control/u_DDR2_Address/read_addr_14 SLICE_X64Y118.C2 net (fanout=5) 0.958 u_DDR2_Control/u_DDR2_Address/read_addr<14> SLICE_X64Y118.COUT Topcyc 0.409 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_lut<2> u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> SLICE_X64Y119.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> SLICE_X64Y119.AMUX Tcina 0.310 u_DDR2_Control/u_DDR2_Address/N2 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<4> SLICE_X65Y117.C5 net (fanout=26) 0.638 u_DDR2_Control/u_DDR2_Address/read_active_cmp_eq0002 SLICE_X65Y117.COUT Topcyc 0.423 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> u_DDR2_Control/u_DDR2_Address/read_addr_mux0001<4>1 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> SLICE_X65Y118.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> SLICE_X65Y118.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> SLICE_X65Y119.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> SLICE_X65Y119.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> SLICE_X65Y120.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> SLICE_X65Y120.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> SLICE_X65Y121.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> SLICE_X65Y121.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> SLICE_X65Y122.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> SLICE_X65Y122.CMUX Tcinc 0.334 u_DDR2_Control/u_DDR2_Address/read_addr_share0000<24> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_xor<24> SLICE_X62Y120.B5 net (fanout=1) 0.538 u_DDR2_Control/u_DDR2_Address/read_addr_share0000<24> SLICE_X62Y120.CLK Tas 0.027 u_DDR2_Control/u_DDR2_Address/read_active u_DDR2_Control/u_DDR2_Address/read_addr_mux0000<24>1 u_DDR2_Control/u_DDR2_Address/read_addr_24 ------------------------------------------------- --------------------------- Total 4.503ns (2.369ns logic, 2.134ns route) (52.6% logic, 47.4% route) -------------------------------------------------------------------------------- Paths for end point u_DDR2_Control/u_DDR2_Address/read_addr_23 (SLICE_X64Y121.D6), 528 paths -------------------------------------------------------------------------------- Slack (setup path): -0.805ns (requirement - (data path - clock path skew + uncertainty)) Source: u_DDR2_Control/u_DDR2_Address/read_addr_5 (FF) Destination: u_DDR2_Control/u_DDR2_Address/read_addr_23 (FF) Requirement: 3.750ns Data Path Delay: 4.464ns (Levels of Logic = 9) Clock Path Skew: -0.026ns (1.409 - 1.435) Source Clock: u_clk0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.065ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.108ns Phase Error (PE): 0.000ns Maximum Data Path: u_DDR2_Control/u_DDR2_Address/read_addr_5 to u_DDR2_Control/u_DDR2_Address/read_addr_23 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X64Y117.CQ Tcko 0.471 u_DDR2_Control/u_DDR2_Address/read_addr<6> u_DDR2_Control/u_DDR2_Address/read_addr_5 SLICE_X64Y118.A1 net (fanout=5) 0.913 u_DDR2_Control/u_DDR2_Address/read_addr<5> SLICE_X64Y118.COUT Topcya 0.499 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_lut<0>1 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> SLICE_X64Y119.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> SLICE_X64Y119.AMUX Tcina 0.310 u_DDR2_Control/u_DDR2_Address/N2 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<4> SLICE_X65Y117.C5 net (fanout=26) 0.638 u_DDR2_Control/u_DDR2_Address/read_active_cmp_eq0002 SLICE_X65Y117.COUT Topcyc 0.423 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> u_DDR2_Control/u_DDR2_Address/read_addr_mux0001<4>1 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> SLICE_X65Y118.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> SLICE_X65Y118.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> SLICE_X65Y119.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> SLICE_X65Y119.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> SLICE_X65Y120.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> SLICE_X65Y120.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> SLICE_X65Y121.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> SLICE_X65Y121.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> SLICE_X65Y122.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> SLICE_X65Y122.BMUX Tcinb 0.335 u_DDR2_Control/u_DDR2_Address/read_addr_share0000<24> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_xor<24> SLICE_X64Y121.D6 net (fanout=1) 0.449 u_DDR2_Control/u_DDR2_Address/read_addr_share0000<23> SLICE_X64Y121.CLK Tas 0.010 u_DDR2_Control/u_DDR2_Address/read_addr<23> u_DDR2_Control/u_DDR2_Address/read_addr_mux0000<23>1 u_DDR2_Control/u_DDR2_Address/read_addr_23 ------------------------------------------------- --------------------------- Total 4.464ns (2.464ns logic, 2.000ns route) (55.2% logic, 44.8% route) -------------------------------------------------------------------------------- Slack (setup path): -0.787ns (requirement - (data path - clock path skew + uncertainty)) Source: u_DDR2_Control/u_DDR2_Address/read_addr_6 (FF) Destination: u_DDR2_Control/u_DDR2_Address/read_addr_23 (FF) Requirement: 3.750ns Data Path Delay: 4.446ns (Levels of Logic = 9) Clock Path Skew: -0.026ns (1.409 - 1.435) Source Clock: u_clk0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.065ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.108ns Phase Error (PE): 0.000ns Maximum Data Path: u_DDR2_Control/u_DDR2_Address/read_addr_6 to u_DDR2_Control/u_DDR2_Address/read_addr_23 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X64Y117.DQ Tcko 0.471 u_DDR2_Control/u_DDR2_Address/read_addr<6> u_DDR2_Control/u_DDR2_Address/read_addr_6 SLICE_X64Y118.B1 net (fanout=5) 0.911 u_DDR2_Control/u_DDR2_Address/read_addr<6> SLICE_X64Y118.COUT Topcyb 0.483 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_lut<1> u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> SLICE_X64Y119.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> SLICE_X64Y119.AMUX Tcina 0.310 u_DDR2_Control/u_DDR2_Address/N2 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<4> SLICE_X65Y117.C5 net (fanout=26) 0.638 u_DDR2_Control/u_DDR2_Address/read_active_cmp_eq0002 SLICE_X65Y117.COUT Topcyc 0.423 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> u_DDR2_Control/u_DDR2_Address/read_addr_mux0001<4>1 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> SLICE_X65Y118.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> SLICE_X65Y118.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> SLICE_X65Y119.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> SLICE_X65Y119.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> SLICE_X65Y120.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> SLICE_X65Y120.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> SLICE_X65Y121.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> SLICE_X65Y121.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> SLICE_X65Y122.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> SLICE_X65Y122.BMUX Tcinb 0.335 u_DDR2_Control/u_DDR2_Address/read_addr_share0000<24> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_xor<24> SLICE_X64Y121.D6 net (fanout=1) 0.449 u_DDR2_Control/u_DDR2_Address/read_addr_share0000<23> SLICE_X64Y121.CLK Tas 0.010 u_DDR2_Control/u_DDR2_Address/read_addr<23> u_DDR2_Control/u_DDR2_Address/read_addr_mux0000<23>1 u_DDR2_Control/u_DDR2_Address/read_addr_23 ------------------------------------------------- --------------------------- Total 4.446ns (2.448ns logic, 1.998ns route) (55.1% logic, 44.9% route) -------------------------------------------------------------------------------- Slack (setup path): -0.779ns (requirement - (data path - clock path skew + uncertainty)) Source: u_DDR2_Control/u_DDR2_Address/read_addr_14 (FF) Destination: u_DDR2_Control/u_DDR2_Address/read_addr_23 (FF) Requirement: 3.750ns Data Path Delay: 4.398ns (Levels of Logic = 9) Clock Path Skew: -0.066ns (1.409 - 1.475) Source Clock: u_clk0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.065ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.108ns Phase Error (PE): 0.000ns Maximum Data Path: u_DDR2_Control/u_DDR2_Address/read_addr_14 to u_DDR2_Control/u_DDR2_Address/read_addr_23 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X66Y119.DQ Tcko 0.450 u_DDR2_Control/u_DDR2_Address/read_addr<14> u_DDR2_Control/u_DDR2_Address/read_addr_14 SLICE_X64Y118.C2 net (fanout=5) 0.958 u_DDR2_Control/u_DDR2_Address/read_addr<14> SLICE_X64Y118.COUT Topcyc 0.409 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_lut<2> u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> SLICE_X64Y119.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> SLICE_X64Y119.AMUX Tcina 0.310 u_DDR2_Control/u_DDR2_Address/N2 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<4> SLICE_X65Y117.C5 net (fanout=26) 0.638 u_DDR2_Control/u_DDR2_Address/read_active_cmp_eq0002 SLICE_X65Y117.COUT Topcyc 0.423 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> u_DDR2_Control/u_DDR2_Address/read_addr_mux0001<4>1 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> SLICE_X65Y118.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> SLICE_X65Y118.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> SLICE_X65Y119.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> SLICE_X65Y119.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> SLICE_X65Y120.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> SLICE_X65Y120.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> SLICE_X65Y121.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> SLICE_X65Y121.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> SLICE_X65Y122.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> SLICE_X65Y122.BMUX Tcinb 0.335 u_DDR2_Control/u_DDR2_Address/read_addr_share0000<24> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_xor<24> SLICE_X64Y121.D6 net (fanout=1) 0.449 u_DDR2_Control/u_DDR2_Address/read_addr_share0000<23> SLICE_X64Y121.CLK Tas 0.010 u_DDR2_Control/u_DDR2_Address/read_addr<23> u_DDR2_Control/u_DDR2_Address/read_addr_mux0000<23>1 u_DDR2_Control/u_DDR2_Address/read_addr_23 ------------------------------------------------- --------------------------- Total 4.398ns (2.353ns logic, 2.045ns route) (53.5% logic, 46.5% route) -------------------------------------------------------------------------------- Paths for end point u_DDR2_Control/u_DDR2_Address/read_addr_22 (SLICE_X64Y121.C5), 504 paths -------------------------------------------------------------------------------- Slack (setup path): -0.662ns (requirement - (data path - clock path skew + uncertainty)) Source: u_DDR2_Control/u_DDR2_Address/read_addr_5 (FF) Destination: u_DDR2_Control/u_DDR2_Address/read_addr_22 (FF) Requirement: 3.750ns Data Path Delay: 4.321ns (Levels of Logic = 9) Clock Path Skew: -0.026ns (1.409 - 1.435) Source Clock: u_clk0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.065ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.108ns Phase Error (PE): 0.000ns Maximum Data Path: u_DDR2_Control/u_DDR2_Address/read_addr_5 to u_DDR2_Control/u_DDR2_Address/read_addr_22 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X64Y117.CQ Tcko 0.471 u_DDR2_Control/u_DDR2_Address/read_addr<6> u_DDR2_Control/u_DDR2_Address/read_addr_5 SLICE_X64Y118.A1 net (fanout=5) 0.913 u_DDR2_Control/u_DDR2_Address/read_addr<5> SLICE_X64Y118.COUT Topcya 0.499 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_lut<0>1 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> SLICE_X64Y119.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> SLICE_X64Y119.AMUX Tcina 0.310 u_DDR2_Control/u_DDR2_Address/N2 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<4> SLICE_X65Y117.C5 net (fanout=26) 0.638 u_DDR2_Control/u_DDR2_Address/read_active_cmp_eq0002 SLICE_X65Y117.COUT Topcyc 0.423 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> u_DDR2_Control/u_DDR2_Address/read_addr_mux0001<4>1 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> SLICE_X65Y118.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> SLICE_X65Y118.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> SLICE_X65Y119.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> SLICE_X65Y119.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> SLICE_X65Y120.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> SLICE_X65Y120.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> SLICE_X65Y121.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> SLICE_X65Y121.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> SLICE_X65Y122.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> SLICE_X65Y122.AMUX Tcina 0.271 u_DDR2_Control/u_DDR2_Address/read_addr_share0000<24> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_xor<24> SLICE_X64Y121.C5 net (fanout=1) 0.371 u_DDR2_Control/u_DDR2_Address/read_addr_share0000<22> SLICE_X64Y121.CLK Tas 0.009 u_DDR2_Control/u_DDR2_Address/read_addr<23> u_DDR2_Control/u_DDR2_Address/read_addr_mux0000<22>1 u_DDR2_Control/u_DDR2_Address/read_addr_22 ------------------------------------------------- --------------------------- Total 4.321ns (2.399ns logic, 1.922ns route) (55.5% logic, 44.5% route) -------------------------------------------------------------------------------- Slack (setup path): -0.644ns (requirement - (data path - clock path skew + uncertainty)) Source: u_DDR2_Control/u_DDR2_Address/read_addr_6 (FF) Destination: u_DDR2_Control/u_DDR2_Address/read_addr_22 (FF) Requirement: 3.750ns Data Path Delay: 4.303ns (Levels of Logic = 9) Clock Path Skew: -0.026ns (1.409 - 1.435) Source Clock: u_clk0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.065ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.108ns Phase Error (PE): 0.000ns Maximum Data Path: u_DDR2_Control/u_DDR2_Address/read_addr_6 to u_DDR2_Control/u_DDR2_Address/read_addr_22 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X64Y117.DQ Tcko 0.471 u_DDR2_Control/u_DDR2_Address/read_addr<6> u_DDR2_Control/u_DDR2_Address/read_addr_6 SLICE_X64Y118.B1 net (fanout=5) 0.911 u_DDR2_Control/u_DDR2_Address/read_addr<6> SLICE_X64Y118.COUT Topcyb 0.483 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_lut<1> u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> SLICE_X64Y119.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> SLICE_X64Y119.AMUX Tcina 0.310 u_DDR2_Control/u_DDR2_Address/N2 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<4> SLICE_X65Y117.C5 net (fanout=26) 0.638 u_DDR2_Control/u_DDR2_Address/read_active_cmp_eq0002 SLICE_X65Y117.COUT Topcyc 0.423 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> u_DDR2_Control/u_DDR2_Address/read_addr_mux0001<4>1 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> SLICE_X65Y118.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> SLICE_X65Y118.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> SLICE_X65Y119.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> SLICE_X65Y119.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> SLICE_X65Y120.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> SLICE_X65Y120.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> SLICE_X65Y121.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> SLICE_X65Y121.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> SLICE_X65Y122.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> SLICE_X65Y122.AMUX Tcina 0.271 u_DDR2_Control/u_DDR2_Address/read_addr_share0000<24> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_xor<24> SLICE_X64Y121.C5 net (fanout=1) 0.371 u_DDR2_Control/u_DDR2_Address/read_addr_share0000<22> SLICE_X64Y121.CLK Tas 0.009 u_DDR2_Control/u_DDR2_Address/read_addr<23> u_DDR2_Control/u_DDR2_Address/read_addr_mux0000<22>1 u_DDR2_Control/u_DDR2_Address/read_addr_22 ------------------------------------------------- --------------------------- Total 4.303ns (2.383ns logic, 1.920ns route) (55.4% logic, 44.6% route) -------------------------------------------------------------------------------- Slack (setup path): -0.636ns (requirement - (data path - clock path skew + uncertainty)) Source: u_DDR2_Control/u_DDR2_Address/read_addr_14 (FF) Destination: u_DDR2_Control/u_DDR2_Address/read_addr_22 (FF) Requirement: 3.750ns Data Path Delay: 4.255ns (Levels of Logic = 9) Clock Path Skew: -0.066ns (1.409 - 1.475) Source Clock: u_clk0 rising at 0.000ns Destination Clock: u_clk0 rising at 3.750ns Clock Uncertainty: 0.065ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.108ns Phase Error (PE): 0.000ns Maximum Data Path: u_DDR2_Control/u_DDR2_Address/read_addr_14 to u_DDR2_Control/u_DDR2_Address/read_addr_22 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X66Y119.DQ Tcko 0.450 u_DDR2_Control/u_DDR2_Address/read_addr<14> u_DDR2_Control/u_DDR2_Address/read_addr_14 SLICE_X64Y118.C2 net (fanout=5) 0.958 u_DDR2_Control/u_DDR2_Address/read_addr<14> SLICE_X64Y118.COUT Topcyc 0.409 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_lut<2> u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> SLICE_X64Y119.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<3> SLICE_X64Y119.AMUX Tcina 0.310 u_DDR2_Control/u_DDR2_Address/N2 u_DDR2_Control/u_DDR2_Address/Mcompar_read_active_cmp_eq0002_cy<4> SLICE_X65Y117.C5 net (fanout=26) 0.638 u_DDR2_Control/u_DDR2_Address/read_active_cmp_eq0002 SLICE_X65Y117.COUT Topcyc 0.423 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> u_DDR2_Control/u_DDR2_Address/read_addr_mux0001<4>1 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> SLICE_X65Y118.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<5> SLICE_X65Y118.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> SLICE_X65Y119.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<9> SLICE_X65Y119.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> SLICE_X65Y120.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<13> SLICE_X65Y120.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> SLICE_X65Y121.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<17> SLICE_X65Y121.COUT Tbyp 0.104 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> SLICE_X65Y122.CIN net (fanout=1) 0.000 u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_cy<21> SLICE_X65Y122.AMUX Tcina 0.271 u_DDR2_Control/u_DDR2_Address/read_addr_share0000<24> u_DDR2_Control/u_DDR2_Address/Madd_read_addr_share0000_xor<24> SLICE_X64Y121.C5 net (fanout=1) 0.371 u_DDR2_Control/u_DDR2_Address/read_addr_share0000<22> SLICE_X64Y121.CLK Tas 0.009 u_DDR2_Control/u_DDR2_Address/read_addr<23> u_DDR2_Control/u_DDR2_Address/read_addr_mux0000<22>1 u_DDR2_Control/u_DDR2_Address/read_addr_22 ------------------------------------------------- --------------------------- Total 4.255ns (2.288ns logic, 1.967ns route) (53.8% logic, 46.2% route) -------------------------------------------------------------------------------- Hold Paths: TS_DDR2_RAM_CORE_u_ddr2_infrastructure_clk0_bufg_in = PERIOD TIMEGRP "DDR2_RAM_CORE_u_ddr2_infrastructure_clk0_bufg_in" TS_SYS_CLK HIGH 50%; -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/ddr_cs_n_r1_0 (SLICE_X18Y115.AX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.015ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/ddr_cs_n_r_0 (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/ddr_cs_n_r1_0 (FF) Requirement: 0.000ns Data Path Delay: 0.496ns (Levels of Logic = 0) Clock Path Skew: 0.289ns (3.775 - 3.486) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 0.000ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/ddr_cs_n_r_0 to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/ddr_cs_n_r1_0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X19Y115.AQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/ddr_cs_n_r<0> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/ddr_cs_n_r_0 SLICE_X18Y115.AX net (fanout=1) 0.311 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/ddr_cs_n_r<0> SLICE_X18Y115.CLK Tckdi (-Th) 0.229 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/ddr_cs_n_r1<0> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/ddr_cs_n_r1_0 ------------------------------------------------- --------------------------- Total 0.496ns (0.185ns logic, 0.311ns route) (37.3% logic, 62.7% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[5].u_ff_rden_sel_mux (SLICE_X13Y95.BX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.025ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_sel_5 (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[5].u_ff_rden_sel_mux (FF) Requirement: 0.000ns Data Path Delay: 0.462ns (Levels of Logic = 0) Clock Path Skew: 0.245ns (3.663 - 3.418) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 0.000ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_sel_5 to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[5].u_ff_rden_sel_mux Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X15Y95.BQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_sel<7> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_sel_5 SLICE_X13Y95.BX net (fanout=1) 0.279 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_sel<5> SLICE_X13Y95.CLK Tckdi (-Th) 0.231 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rden_sel_mux<7> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[5].u_ff_rden_sel_mux ------------------------------------------------- --------------------------- Total 0.462ns (0.183ns logic, 0.279ns route) (39.6% logic, 60.4% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[6].u_ff_rden_sel_mux (SLICE_X13Y95.CX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.039ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_sel_6 (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[6].u_ff_rden_sel_mux (FF) Requirement: 0.000ns Data Path Delay: 0.476ns (Levels of Logic = 0) Clock Path Skew: 0.245ns (3.663 - 3.418) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: u_clk0 rising at 0.000ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_sel_6 to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[6].u_ff_rden_sel_mux Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X15Y95.CQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_sel<7> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_sel_6 SLICE_X13Y95.CX net (fanout=1) 0.280 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_sel<6> SLICE_X13Y95.CLK Tckdi (-Th) 0.218 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/rden_sel_mux<7> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_usr_top/u_usr_rd/gen_rden_sel_mux[6].u_ff_rden_sel_mux ------------------------------------------------- --------------------------- Total 0.476ns (0.196ns logic, 0.280ns route) (41.2% logic, 58.8% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_DDR2_RAM_CORE_u_ddr2_infrastructure_clk0_bufg_in = PERIOD TIMEGRP "DDR2_RAM_CORE_u_ddr2_infrastructure_clk0_bufg_in" TS_SYS_CLK HIGH 50%; -------------------------------------------------------------------------------- Slack: 1.200ns (period - (min high pulse limit / (high pulse / period))) Period: 3.750ns High pulse: 1.875ns High pulse limit: 1.275ns (Torpwh) Physical resource: ddr2_cs_n_0_OBUF/REV Logical resource: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_ctl_io/gen_cs_n[0].gen_cs_two_t_0.u_ff_cs_n/REV Location pin: OLOGIC_X0Y231.REV Clock network: DDR2_RAM_CORE/u_ddr2_infrastructure/rst0_sync_r_24_2 -------------------------------------------------------------------------------- Slack: 1.250ns (period - (min high pulse limit / (high pulse / period))) Period: 3.750ns High pulse: 1.875ns High pulse limit: 1.250ns (Tospwh) Physical resource: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/dqs_out/SR Logical resource: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[0].u_iob_dqs/u_tri_state_dqs/SR Location pin: OLOGIC_X0Y97.SR Clock network: DDR2_RAM_CORE/u_ddr2_infrastructure/rst0_sync_r_24_2 -------------------------------------------------------------------------------- Slack: 1.250ns (period - (min high pulse limit / (high pulse / period))) Period: 3.750ns High pulse: 1.875ns High pulse limit: 1.250ns (Tospwh) Physical resource: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/dqs_out/SR Logical resource: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_tri_state_dqs/SR Location pin: OLOGIC_X0Y59.SR Clock network: DDR2_RAM_CORE/u_ddr2_infrastructure/rst0_sync_r_24_1 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_DDR2_RAM_CORE_u_ddr2_infrastructure_clk90_bufg_in = PERIOD TIMEGRP "DDR2_RAM_CORE_u_ddr2_infrastructure_clk90_bufg_in" TS_SYS_CLK PHASE 0.9375 ns HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 649 paths analyzed, 636 endpoints analyzed, 1 failing endpoint 1 timing error detected. (1 setup error, 0 hold errors, 0 component switching limit errors) Minimum period is 3.894ns. -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/Mshreg_dq_oe_n_0 (SLICE_X0Y78.CI), 1 path -------------------------------------------------------------------------------- Slack (setup path): -0.072ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/dq_oe_270_0 (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/Mshreg_dq_oe_n_0 (FF) Requirement: 1.875ns Data Path Delay: 1.798ns (Levels of Logic = 1) Clock Path Skew: -0.084ns (1.342 - 1.426) Source Clock: DDR2_RAM_CORE/clk90 falling at 2.812ns Destination Clock: DDR2_RAM_CORE/clk90 rising at 4.687ns Clock Uncertainty: 0.065ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.108ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/dq_oe_270_0 to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/Mshreg_dq_oe_n_0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X3Y86.AQ Tcko 0.445 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/dq_oe_270<0> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/dq_oe_270_0 SLICE_X3Y86.D6 net (fanout=1) 0.286 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/dq_oe_270<0> SLICE_X3Y86.D Tilo 0.094 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/dq_oe_270<0> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/dq_oe_n_90_r1_0_rstpot1_INV_0 SLICE_X0Y78.CI net (fanout=1) 0.638 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/dq_oe_n_90_r1_0_rstpot SLICE_X0Y78.CLK Tds 0.335 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/dq_oe_n<0> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/Mshreg_dq_oe_n_0 ------------------------------------------------- --------------------------- Total 1.798ns (0.874ns logic, 0.924ns route) (48.6% logic, 51.4% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_108 (SLICE_X12Y101.SR), 1 path -------------------------------------------------------------------------------- Slack (setup path): 0.026ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/init_data_f_0 (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_108 (FF) Requirement: 3.750ns Data Path Delay: 3.651ns (Levels of Logic = 1) Clock Path Skew: -0.008ns (1.406 - 1.414) Source Clock: DDR2_RAM_CORE/clk90 rising at 0.937ns Destination Clock: DDR2_RAM_CORE/clk90 rising at 4.687ns Clock Uncertainty: 0.065ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.108ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/init_data_f_0 to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_108 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X9Y82.AQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/init_data_f<10> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/init_data_f_0 SLICE_X8Y82.A5 net (fanout=1) 0.433 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/init_data_f<0> SLICE_X8Y82.A Tilo 0.094 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/N3 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_mux0001<100>11 SLICE_X12Y101.SR net (fanout=15) 2.133 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/N3 SLICE_X12Y101.CLK Tsrck 0.541 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r<108> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_data_r_108 ------------------------------------------------- --------------------------- Total 3.651ns (1.085ns logic, 2.566ns route) (29.7% logic, 70.3% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[61].u_iob_dq/u_tri_state_dq (OLOGIC_X0Y273.T2), 1 path -------------------------------------------------------------------------------- Slack (setup path): 0.037ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/dq_oe_n_1 (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[61].u_iob_dq/u_tri_state_dq (FF) Requirement: 3.750ns Data Path Delay: 3.755ns (Levels of Logic = 0) Clock Path Skew: 0.107ns (1.550 - 1.443) Source Clock: DDR2_RAM_CORE/clk90 rising at 0.937ns Destination Clock: DDR2_RAM_CORE/clk90 rising at 4.687ns Clock Uncertainty: 0.065ns Clock Uncertainty: 0.065ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.108ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/dq_oe_n_1 to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[61].u_iob_dq/u_tri_state_dq Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X0Y80.AQ Tcko 0.471 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/dq_oe_n<1> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/dq_oe_n_1 OLOGIC_X0Y273.T2 net (fanout=64) 2.874 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/dq_oe_n<1> OLOGIC_X0Y273.CLK Totck 0.410 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[61].u_iob_dq/dq_out DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[61].u_iob_dq/u_tri_state_dq ------------------------------------------------- --------------------------- Total 3.755ns (0.881ns logic, 2.874ns route) (23.5% logic, 76.5% route) -------------------------------------------------------------------------------- Hold Paths: TS_DDR2_RAM_CORE_u_ddr2_infrastructure_clk90_bufg_in = PERIOD TIMEGRP "DDR2_RAM_CORE_u_ddr2_infrastructure_clk90_bufg_in" TS_SYS_CLK PHASE 0.9375 ns HIGH 50%; -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_rden_90_r1 (SLICE_X14Y81.D6), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.431ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_rden_90_r (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_rden_90_r1 (FF) Requirement: 0.000ns Data Path Delay: 0.501ns (Levels of Logic = 1) Clock Path Skew: 0.070ns (0.687 - 0.617) Source Clock: DDR2_RAM_CORE/clk90 rising at 4.687ns Destination Clock: DDR2_RAM_CORE/clk90 rising at 4.687ns Clock Uncertainty: 0.000ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_rden_90_r to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_rden_90_r1 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X13Y81.DQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_rden_90_r DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_rden_90_r SLICE_X14Y81.D6 net (fanout=2) 0.282 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_rden_90_r SLICE_X14Y81.CLK Tah (-Th) 0.195 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_rden_90_r1 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_rden_90_r1_rstpot DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_rden_90_r1 ------------------------------------------------- --------------------------- Total 0.501ns (0.219ns logic, 0.282ns route) (43.7% logic, 56.3% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/calib_rden_90_r (SLICE_X15Y81.DX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.446ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_rden_90_r (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/calib_rden_90_r (FF) Requirement: 0.000ns Data Path Delay: 0.489ns (Levels of Logic = 0) Clock Path Skew: 0.043ns (0.660 - 0.617) Source Clock: DDR2_RAM_CORE/clk90 rising at 4.687ns Destination Clock: DDR2_RAM_CORE/clk90 rising at 4.687ns Clock Uncertainty: 0.000ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_rden_90_r to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/calib_rden_90_r Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X13Y81.DQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_rden_90_r DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_rden_90_r SLICE_X15Y81.DX net (fanout=2) 0.294 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/wdf_rden_90_r SLICE_X15Y81.CLK Tckdi (-Th) 0.219 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/calib_rden_90_r DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_write/calib_rden_90_r ------------------------------------------------- --------------------------- Total 0.489ns (0.195ns logic, 0.294ns route) (39.9% logic, 60.1% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_infrastructure/rst_tmp_shift22 (SLICE_X9Y65.BX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.465ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_infrastructure/rst_tmp_shift21 (FF) Destination: DDR2_RAM_CORE/u_ddr2_infrastructure/rst_tmp_shift22 (FF) Requirement: 0.000ns Data Path Delay: 0.465ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: DDR2_RAM_CORE/clk90 rising at 4.687ns Destination Clock: DDR2_RAM_CORE/clk90 rising at 4.687ns Clock Uncertainty: 0.000ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_infrastructure/rst_tmp_shift21 to DDR2_RAM_CORE/u_ddr2_infrastructure/rst_tmp_shift22 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X9Y65.AQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_infrastructure/rst_tmp_shift23 DDR2_RAM_CORE/u_ddr2_infrastructure/rst_tmp_shift21 SLICE_X9Y65.BX net (fanout=1) 0.282 DDR2_RAM_CORE/u_ddr2_infrastructure/rst_tmp_shift21 SLICE_X9Y65.CLK Tckdi (-Th) 0.231 DDR2_RAM_CORE/u_ddr2_infrastructure/rst_tmp_shift23 DDR2_RAM_CORE/u_ddr2_infrastructure/rst_tmp_shift22 ------------------------------------------------- --------------------------- Total 0.465ns (0.183ns logic, 0.282ns route) (39.4% logic, 60.6% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_DDR2_RAM_CORE_u_ddr2_infrastructure_clk90_bufg_in = PERIOD TIMEGRP "DDR2_RAM_CORE_u_ddr2_infrastructure_clk90_bufg_in" TS_SYS_CLK PHASE 0.9375 ns HIGH 50%; -------------------------------------------------------------------------------- Slack: 1.250ns (period - (min high pulse limit / (high pulse / period))) Period: 3.750ns High pulse: 1.875ns High pulse limit: 1.250ns (Tospwh) Physical resource: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[0].u_iob_dq/dq_out/SR Logical resource: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[0].u_iob_dq/u_tri_state_dq/SR Location pin: OLOGIC_X0Y84.SR Clock network: DDR2_RAM_CORE/u_ddr2_infrastructure/rst90_sync_r<24> -------------------------------------------------------------------------------- Slack: 1.250ns (period - (min high pulse limit / (high pulse / period))) Period: 3.750ns High pulse: 1.875ns High pulse limit: 1.250ns (Tospwh) Physical resource: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[1].u_iob_dq/dq_out/SR Logical resource: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[1].u_iob_dq/u_tri_state_dq/SR Location pin: OLOGIC_X0Y86.SR Clock network: DDR2_RAM_CORE/u_ddr2_infrastructure/rst90_sync_r_24_6 -------------------------------------------------------------------------------- Slack: 1.250ns (period - (min high pulse limit / (high pulse / period))) Period: 3.750ns High pulse: 1.875ns High pulse limit: 1.250ns (Tospwh) Physical resource: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[2].u_iob_dq/dq_out/SR Logical resource: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[2].u_iob_dq/u_tri_state_dq/SR Location pin: OLOGIC_X0Y91.SR Clock network: DDR2_RAM_CORE/u_ddr2_infrastructure/rst90_sync_r_24_5 -------------------------------------------------------------------------------- ================================================================================ Timing constraint: TS_DDR2_RAM_CORE_u_ddr2_infrastructure_clkdiv0_bufg_in = PERIOD TIMEGRP "DDR2_RAM_CORE_u_ddr2_infrastructure_clkdiv0_bufg_in" TS_SYS_CLK / 0.5 HIGH 50%; For more information, see Period Analysis in the Timing Closure User Guide (UG612). 11739 paths analyzed, 4010 endpoints analyzed, 0 failing endpoints 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) Minimum period is 7.472ns. -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyinc_dqs_2 (SLICE_X5Y31.SR), 6 paths -------------------------------------------------------------------------------- Slack (setup path): 0.028ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/count_dqs_2 (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyinc_dqs_2 (FF) Requirement: 7.500ns Data Path Delay: 7.662ns (Levels of Logic = 1) Clock Path Skew: 0.262ns (1.482 - 1.220) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clkdiv0 rising at 7.500ns Clock Uncertainty: 0.072ns Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/count_dqs_2 to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyinc_dqs_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X46Y91.BQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/count_dqs<2> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/count_dqs_2 SLICE_X14Y40.D1 net (fanout=32) 5.507 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/count_dqs<2> SLICE_X14Y40.D Tilo 0.094 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_rise_1x_r<15> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2_or00001 SLICE_X5Y31.SR net (fanout=2) 1.066 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2_or0000 SLICE_X5Y31.CLK Tsrck 0.545 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyinc_dqs<2> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyinc_dqs_2 ------------------------------------------------- --------------------------- Total 7.662ns (1.089ns logic, 6.573ns route) (14.2% logic, 85.8% route) -------------------------------------------------------------------------------- Slack (setup path): 1.078ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal1_dlyce_dq (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyinc_dqs_2 (FF) Requirement: 7.500ns Data Path Delay: 6.493ns (Levels of Logic = 1) Clock Path Skew: 0.143ns (1.482 - 1.339) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clkdiv0 rising at 7.500ns Clock Uncertainty: 0.072ns Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal1_dlyce_dq to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyinc_dqs_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X37Y109.CQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal1_dlyce_dq DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal1_dlyce_dq SLICE_X14Y40.D4 net (fanout=158) 4.338 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal1_dlyce_dq SLICE_X14Y40.D Tilo 0.094 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_rise_1x_r<15> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2_or00001 SLICE_X5Y31.SR net (fanout=2) 1.066 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2_or0000 SLICE_X5Y31.CLK Tsrck 0.545 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyinc_dqs<2> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyinc_dqs_2 ------------------------------------------------- --------------------------- Total 6.493ns (1.089ns logic, 5.404ns route) (16.8% logic, 83.2% route) -------------------------------------------------------------------------------- Slack (setup path): 1.527ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/count_dqs_0 (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyinc_dqs_2 (FF) Requirement: 7.500ns Data Path Delay: 6.174ns (Levels of Logic = 1) Clock Path Skew: 0.273ns (1.482 - 1.209) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clkdiv0 rising at 7.500ns Clock Uncertainty: 0.072ns Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/count_dqs_0 to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyinc_dqs_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X49Y89.BQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/count_dqs<0> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/count_dqs_0 SLICE_X14Y40.D3 net (fanout=28) 4.019 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/count_dqs<0> SLICE_X14Y40.D Tilo 0.094 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_rise_1x_r<15> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2_or00001 SLICE_X5Y31.SR net (fanout=2) 1.066 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2_or0000 SLICE_X5Y31.CLK Tsrck 0.545 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyinc_dqs<2> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyinc_dqs_2 ------------------------------------------------- --------------------------- Total 6.174ns (1.089ns logic, 5.085ns route) (17.6% logic, 82.4% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2 (SLICE_X4Y31.SR), 6 paths -------------------------------------------------------------------------------- Slack (setup path): 0.032ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/count_dqs_2 (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2 (FF) Requirement: 7.500ns Data Path Delay: 7.658ns (Levels of Logic = 1) Clock Path Skew: 0.262ns (1.482 - 1.220) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clkdiv0 rising at 7.500ns Clock Uncertainty: 0.072ns Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/count_dqs_2 to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X46Y91.BQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/count_dqs<2> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/count_dqs_2 SLICE_X14Y40.D1 net (fanout=32) 5.507 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/count_dqs<2> SLICE_X14Y40.D Tilo 0.094 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_rise_1x_r<15> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2_or00001 SLICE_X4Y31.SR net (fanout=2) 1.066 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2_or0000 SLICE_X4Y31.CLK Tsrck 0.541 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs<2> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2 ------------------------------------------------- --------------------------- Total 7.658ns (1.085ns logic, 6.573ns route) (14.2% logic, 85.8% route) -------------------------------------------------------------------------------- Slack (setup path): 1.082ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal1_dlyce_dq (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2 (FF) Requirement: 7.500ns Data Path Delay: 6.489ns (Levels of Logic = 1) Clock Path Skew: 0.143ns (1.482 - 1.339) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clkdiv0 rising at 7.500ns Clock Uncertainty: 0.072ns Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal1_dlyce_dq to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X37Y109.CQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal1_dlyce_dq DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal1_dlyce_dq SLICE_X14Y40.D4 net (fanout=158) 4.338 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal1_dlyce_dq SLICE_X14Y40.D Tilo 0.094 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_rise_1x_r<15> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2_or00001 SLICE_X4Y31.SR net (fanout=2) 1.066 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2_or0000 SLICE_X4Y31.CLK Tsrck 0.541 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs<2> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2 ------------------------------------------------- --------------------------- Total 6.489ns (1.085ns logic, 5.404ns route) (16.7% logic, 83.3% route) -------------------------------------------------------------------------------- Slack (setup path): 1.531ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/count_dqs_0 (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2 (FF) Requirement: 7.500ns Data Path Delay: 6.170ns (Levels of Logic = 1) Clock Path Skew: 0.273ns (1.482 - 1.209) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clkdiv0 rising at 7.500ns Clock Uncertainty: 0.072ns Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/count_dqs_0 to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X49Y89.BQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/count_dqs<0> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/count_dqs_0 SLICE_X14Y40.D3 net (fanout=28) 4.019 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/count_dqs<0> SLICE_X14Y40.D Tilo 0.094 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/rd_data_rise_1x_r<15> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2_or00001 SLICE_X4Y31.SR net (fanout=2) 1.066 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2_or0000 SLICE_X4Y31.CLK Tsrck 0.541 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs<2> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/i_dlyce_dqs_2 ------------------------------------------------- --------------------------- Total 6.170ns (1.085ns logic, 5.085ns route) (17.6% logic, 82.4% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_gate_srl_a_2 (SLICE_X4Y84.A2), 14 paths -------------------------------------------------------------------------------- Slack (setup path): 0.036ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_valid (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_gate_srl_a_2 (FF) Requirement: 7.500ns Data Path Delay: 7.297ns (Levels of Logic = 3) Clock Path Skew: -0.095ns (1.340 - 1.435) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clkdiv0 rising at 7.500ns Clock Uncertainty: 0.072ns Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_valid to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_gate_srl_a_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X27Y103.AQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/phy_init_done_r1 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_valid SLICE_X41Y92.A2 net (fanout=21) 2.299 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_valid SLICE_X41Y92.A Tilo 0.094 DDR2_RAM_CORE/u_ddr2_infrastructure/rst0_sync_r_24_2 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_data_good_or00001 SLICE_X14Y90.D3 net (fanout=10) 3.032 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_data_good SLICE_X14Y90.D Tilo 0.094 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_dlyrst_gate DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_gate_srl_a_mux0000<1>21 SLICE_X4Y84.A2 net (fanout=5) 1.321 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_dlyrst_gate_mux0006 SLICE_X4Y84.CLK Tas 0.007 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_gate_srl_a<4> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_gate_srl_a_mux0000<2>1 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_gate_srl_a_2 ------------------------------------------------- --------------------------- Total 7.297ns (0.645ns logic, 6.652ns route) (8.8% logic, 91.2% route) -------------------------------------------------------------------------------- Slack (setup path): 0.785ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_valid_stgd (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_gate_srl_a_2 (FF) Requirement: 7.500ns Data Path Delay: 6.593ns (Levels of Logic = 3) Clock Path Skew: -0.050ns (1.340 - 1.390) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clkdiv0 rising at 7.500ns Clock Uncertainty: 0.072ns Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_valid_stgd to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_gate_srl_a_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X34Y104.CQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_valid_stgd DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_valid_stgd SLICE_X41Y92.A5 net (fanout=21) 1.595 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/calib_rden_valid_stgd SLICE_X41Y92.A Tilo 0.094 DDR2_RAM_CORE/u_ddr2_infrastructure/rst0_sync_r_24_2 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_data_good_or00001 SLICE_X14Y90.D3 net (fanout=10) 3.032 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_data_good SLICE_X14Y90.D Tilo 0.094 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_dlyrst_gate DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_gate_srl_a_mux0000<1>21 SLICE_X4Y84.A2 net (fanout=5) 1.321 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_dlyrst_gate_mux0006 SLICE_X4Y84.CLK Tas 0.007 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_gate_srl_a<4> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_gate_srl_a_mux0000<2>1 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_gate_srl_a_2 ------------------------------------------------- --------------------------- Total 6.593ns (0.645ns logic, 5.948ns route) (9.8% logic, 90.2% route) -------------------------------------------------------------------------------- Slack (setup path): 2.100ns (requirement - (data path - clock path skew + uncertainty)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_data_match (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_gate_srl_a_2 (FF) Requirement: 7.500ns Data Path Delay: 5.484ns (Levels of Logic = 3) Clock Path Skew: 0.156ns (1.340 - 1.184) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 0.000ns Destination Clock: DDR2_RAM_CORE/clkdiv0 rising at 7.500ns Clock Uncertainty: 0.072ns Clock Uncertainty: 0.072ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.000ns Maximum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_data_match to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_gate_srl_a_2 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X41Y91.AQ Tcko 0.450 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_data_match DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_data_match SLICE_X41Y92.A4 net (fanout=4) 0.486 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_data_match SLICE_X41Y92.A Tilo 0.094 DDR2_RAM_CORE/u_ddr2_infrastructure/rst0_sync_r_24_2 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_data_good_or00001 SLICE_X14Y90.D3 net (fanout=10) 3.032 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_data_good SLICE_X14Y90.D Tilo 0.094 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_dlyrst_gate DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_gate_srl_a_mux0000<1>21 SLICE_X4Y84.A2 net (fanout=5) 1.321 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_dlyrst_gate_mux0006 SLICE_X4Y84.CLK Tas 0.007 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_gate_srl_a<4> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_gate_srl_a_mux0000<2>1 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/cal4_gate_srl_a_2 ------------------------------------------------- --------------------------- Total 5.484ns (0.645ns logic, 4.839ns route) (11.8% logic, 88.2% route) -------------------------------------------------------------------------------- Hold Paths: TS_DDR2_RAM_CORE_u_ddr2_infrastructure_clkdiv0_bufg_in = PERIOD TIMEGRP "DDR2_RAM_CORE_u_ddr2_infrastructure_clkdiv0_bufg_in" TS_SYS_CLK / 0.5 HIGH 50%; -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/cke_200us_cnt_en_r (SLICE_X32Y124.B4), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.093ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/ctrl_ref_flag_r (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/cke_200us_cnt_en_r (FF) Requirement: 0.000ns Data Path Delay: 0.538ns (Levels of Logic = 1) Clock Path Skew: 0.253ns (3.707 - 3.454) Source Clock: u_clk0 rising at 7.500ns Destination Clock: DDR2_RAM_CORE/clkdiv0 rising at 7.500ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/ctrl_ref_flag_r to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/cke_200us_cnt_en_r Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X33Y124.AQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/ctrl_ref_flag_r DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/ctrl_ref_flag_r SLICE_X32Y124.B4 net (fanout=1) 0.346 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/ctrl_ref_flag_r SLICE_X32Y124.CLK Tah (-Th) 0.222 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/cke_200us_cnt_en_r DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/cke_200us_cnt_en_r_rstpot DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/cke_200us_cnt_en_r ------------------------------------------------- --------------------------- Total 0.538ns (0.192ns logic, 0.346ns route) (35.7% logic, 64.3% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/cke_200us_cnt_en_r (SLICE_X32Y124.B5), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.130ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_ctrl/ref_flag_r (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/cke_200us_cnt_en_r (FF) Requirement: 0.000ns Data Path Delay: 0.582ns (Levels of Logic = 1) Clock Path Skew: 0.260ns (3.707 - 3.447) Source Clock: u_clk0 rising at 7.500ns Destination Clock: DDR2_RAM_CORE/clkdiv0 rising at 7.500ns Clock Uncertainty: 0.192ns Clock Uncertainty: 0.192ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE Total System Jitter (TSJ): 0.070ns Discrete Jitter (DJ): 0.124ns Phase Error (PE): 0.120ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_ctrl/ref_flag_r to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/cke_200us_cnt_en_r Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X32Y126.DQ Tcko 0.433 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_ctrl/ref_flag_r DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_ctrl/ref_flag_r SLICE_X32Y124.B5 net (fanout=3) 0.371 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_ctrl/ref_flag_r SLICE_X32Y124.CLK Tah (-Th) 0.222 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/cke_200us_cnt_en_r DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/cke_200us_cnt_en_r_rstpot DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_init/cke_200us_cnt_en_r ------------------------------------------------- --------------------------- Total 0.582ns (0.211ns logic, 0.371ns route) (36.3% logic, 63.7% route) -------------------------------------------------------------------------------- Paths for end point DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[37].u_ff_gate_dly (SLICE_X4Y88.BX), 1 path -------------------------------------------------------------------------------- Slack (hold path): 0.317ns (requirement - (clock path skew + uncertainty - data path)) Source: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_dly_37 (FF) Destination: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[37].u_ff_gate_dly (FF) Requirement: 0.000ns Data Path Delay: 0.326ns (Levels of Logic = 0) Clock Path Skew: 0.009ns (0.131 - 0.122) Source Clock: DDR2_RAM_CORE/clkdiv0 rising at 7.500ns Destination Clock: DDR2_RAM_CORE/clkdiv0 rising at 7.500ns Clock Uncertainty: 0.000ns Minimum Data Path: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_dly_37 to DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[37].u_ff_gate_dly Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X5Y88.AQ Tcko 0.414 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_dly<37> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_dly_37 SLICE_X4Y88.BX net (fanout=2) 0.154 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_dly<37> SLICE_X4Y88.CLK Tckdi (-Th) 0.242 DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gate_dly_r<39> DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/u_phy_calib/gen_gate_dly[37].u_ff_gate_dly ------------------------------------------------- --------------------------- Total 0.326ns (0.172ns logic, 0.154ns route) (52.8% logic, 47.2% route) -------------------------------------------------------------------------------- Component Switching Limit Checks: TS_DDR2_RAM_CORE_u_ddr2_infrastructure_clkdiv0_bufg_in = PERIOD TIMEGRP "DDR2_RAM_CORE_u_ddr2_infrastructure_clkdiv0_bufg_in" TS_SYS_CLK / 0.5 HIGH 50%; -------------------------------------------------------------------------------- Slack: 3.501ns (period - min period limit) Period: 7.500ns Min period limit: 3.999ns (250.063MHz) (Tiodper_C) Physical resource: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[58].u_iob_dq/u_idelay_dq/C Logical resource: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dq[58].u_iob_dq/u_idelay_dq/C Location pin: IODELAY_X0Y275.C Clock network: DDR2_RAM_CORE/clkdiv0 -------------------------------------------------------------------------------- Slack: 3.501ns (period - min period limit) Period: 7.500ns Min period limit: 3.999ns (250.063MHz) (Tiodper_C) Physical resource: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce/C Logical resource: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[1].u_iob_dqs/u_iodelay_dq_ce/C Location pin: IODELAY_X0Y58.C Clock network: DDR2_RAM_CORE/clkdiv0 -------------------------------------------------------------------------------- Slack: 3.501ns (period - min period limit) Period: 7.500ns Min period limit: 3.999ns (250.063MHz) (Tiodper_C) Physical resource: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_idelay_dqs/C Logical resource: DDR2_RAM_CORE/u_ddr2_top_0/u_mem_if_top/u_phy_top/u_phy_io/gen_dqs[4].u_iob_dqs/u_idelay_dqs/C Location pin: IODELAY_X0Y103.C Clock network: DDR2_RAM_CORE/clkdiv0 -------------------------------------------------------------------------------- Derived Constraint Report Derived Constraints for TS_SYS_CLK +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ |TS_SYS_CLK | 3.750ns| 2.334ns| 4.640ns| 0| 45| 0| 41823| | TS_MC_RD_DATA_SEL | 15.000ns| 4.652ns| N/A| 0| 0| 384| 0| | TS_MC_RDEN_SEL_MUX | 15.000ns| 3.412ns| N/A| 0| 0| 128| 0| | TS_MC_PHY_INIT_DATA_SEL_0 | 15.000ns| 4.933ns| N/A| 0| 0| 294| 0| | TS_MC_PHY_INIT_DATA_SEL_90 | 15.000ns| N/A| N/A| 0| 0| 0| 0| | TS_MC_GATE_DLY | 15.000ns| 2.067ns| N/A| 0| 0| 40| 0| | TS_MC_RDEN_DLY | 15.000ns| 1.917ns| N/A| 0| 0| 5| 0| | TS_MC_CAL_RDEN_DLY | 15.000ns| 1.844ns| N/A| 0| 0| 5| 0| | TS_DDR2_RAM_CORE_u_ddr2_infras| 3.750ns| 4.640ns| N/A| 44| 0| 28579| 0| | tructure_clk0_bufg_in | | | | | | | | | TS_DDR2_RAM_CORE_u_ddr2_infras| 3.750ns| 3.894ns| N/A| 1| 0| 649| 0| | tructure_clk90_bufg_in | | | | | | | | | TS_DDR2_RAM_CORE_u_ddr2_infras| 7.500ns| 7.472ns| N/A| 0| 0| 11739| 0| | tructure_clkdiv0_bufg_in | | | | | | | | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ 2 constraints not met. Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Clock to Setup on destination clock clk200_n ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk200_n | 2.892| | | | clk200_p | 2.892| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock clk200_p ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk200_n | 2.892| | | | clk200_p | 2.892| | | | ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock clk_100 ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk_100 | 7.472| 1.947| 2.717| 3.455| ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock ddr2_dqs<0> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk_100 | | | 2.690| | ddr2_dqs<0> | | 1.805| | 1.829| ddr2_dqs_n<0> | | 1.805| | 1.829| ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock ddr2_dqs<1> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk_100 | | | 2.690| | ddr2_dqs<1> | | 1.764| | 1.788| ddr2_dqs_n<1> | | 1.764| | 1.788| ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock ddr2_dqs<2> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk_100 | | | 2.690| | ddr2_dqs<2> | | 1.822| | 1.846| ddr2_dqs_n<2> | | 1.822| | 1.846| ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock ddr2_dqs<3> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk_100 | | | 2.690| | ddr2_dqs<3> | | 1.667| | 1.691| ddr2_dqs_n<3> | | 1.667| | 1.691| ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock ddr2_dqs<4> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk_100 | | | 2.693| | ddr2_dqs<4> | | 1.823| | 1.847| ddr2_dqs_n<4> | | 1.823| | 1.847| ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock ddr2_dqs<5> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk_100 | | | 2.690| | ddr2_dqs<5> | | 1.842| | 1.866| ddr2_dqs_n<5> | | 1.842| | 1.866| ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock ddr2_dqs<6> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk_100 | | | 2.690| | ddr2_dqs<6> | | 1.792| | 1.816| ddr2_dqs_n<6> | | 1.792| | 1.816| ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock ddr2_dqs<7> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk_100 | | | 2.690| | ddr2_dqs<7> | | 1.817| | 1.841| ddr2_dqs_n<7> | | 1.817| | 1.841| ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock ddr2_dqs_n<0> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk_100 | | | 2.690| | ddr2_dqs<0> | | 1.805| | 1.829| ddr2_dqs_n<0> | | 1.805| | 1.829| ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock ddr2_dqs_n<1> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk_100 | | | 2.690| | ddr2_dqs<1> | | 1.764| | 1.788| ddr2_dqs_n<1> | | 1.764| | 1.788| ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock ddr2_dqs_n<2> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk_100 | | | 2.690| | ddr2_dqs<2> | | 1.822| | 1.846| ddr2_dqs_n<2> | | 1.822| | 1.846| ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock ddr2_dqs_n<3> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk_100 | | | 2.690| | ddr2_dqs<3> | | 1.667| | 1.691| ddr2_dqs_n<3> | | 1.667| | 1.691| ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock ddr2_dqs_n<4> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk_100 | | | 2.693| | ddr2_dqs<4> | | 1.823| | 1.847| ddr2_dqs_n<4> | | 1.823| | 1.847| ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock ddr2_dqs_n<5> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk_100 | | | 2.690| | ddr2_dqs<5> | | 1.842| | 1.866| ddr2_dqs_n<5> | | 1.842| | 1.866| ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock ddr2_dqs_n<6> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk_100 | | | 2.690| | ddr2_dqs<6> | | 1.792| | 1.816| ddr2_dqs_n<6> | | 1.792| | 1.816| ---------------+---------+---------+---------+---------+ Clock to Setup on destination clock ddr2_dqs_n<7> ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk_100 | | | 2.690| | ddr2_dqs<7> | | 1.817| | 1.841| ddr2_dqs_n<7> | | 1.817| | 1.841| ---------------+---------+---------+---------+---------+ Timing summary: --------------- Timing errors: 45 Score: 12094 (Setup/Max: 12094, Hold: 0) Constraints cover 41983 paths, 16 nets, and 12801 connections Design statistics: Minimum period: 7.472ns{1} (Maximum frequency: 133.833MHz) Maximum path delay from/to any node: 4.933ns Maximum net delay: 0.805ns ------------------------------------Footnotes----------------------------------- 1) The minimum period statistic assumes all single cycle delays. Analysis completed Wed Jun 20 09:51:52 2012 -------------------------------------------------------------------------------- Trace Settings: ------------------------- Trace Settings Peak Memory Usage: 460 MB