CNC.elf: file format elf32-littlearm Disassembly of section .text: 08000000 : 8000000: 7c 0f 00 20 31 21 00 08 71 25 00 08 7d 25 00 08 |.. 1!..q%..}%.. 8000010: 85 25 00 08 8d 25 00 08 95 25 00 08 00 00 00 00 .%...%...%...... ... 800002c: 9d 25 00 08 a9 25 00 08 00 00 00 00 b5 25 00 08 .%...%.......%.. 800003c: c1 25 00 08 99 21 00 08 99 21 00 08 99 21 00 08 .%...!...!...!.. 800004c: 99 21 00 08 99 21 00 08 99 21 00 08 99 21 00 08 .!...!...!...!.. 800005c: 99 21 00 08 99 21 00 08 99 21 00 08 99 21 00 08 .!...!...!...!.. 800006c: 99 21 00 08 99 21 00 08 99 21 00 08 99 21 00 08 .!...!...!...!.. 800007c: 99 21 00 08 99 21 00 08 99 21 00 08 99 21 00 08 .!...!...!...!.. 800008c: 99 21 00 08 99 21 00 08 99 21 00 08 99 21 00 08 .!...!...!...!.. 800009c: 99 21 00 08 99 21 00 08 99 21 00 08 99 21 00 08 .!...!...!...!.. 80000ac: 99 21 00 08 d5 19 00 08 99 21 00 08 99 21 00 08 .!.......!...!.. 80000bc: 99 21 00 08 99 21 00 08 99 21 00 08 99 21 00 08 .!...!...!...!.. 80000cc: 99 21 00 08 99 21 00 08 99 21 00 08 99 21 00 08 .!...!...!...!.. 80000dc: 85 4e 00 08 99 21 00 08 99 21 00 08 99 21 00 08 .N...!...!...!.. 80000ec: 99 21 00 08 99 21 00 08 99 21 00 08 99 21 00 08 .!...!...!...!.. 80000fc: 99 21 00 08 99 21 00 08 99 21 00 08 99 21 00 08 .!...!...!...!.. 800010c: 99 21 00 08 99 21 00 08 99 21 00 08 99 21 00 08 .!...!...!...!.. 800011c: 99 21 00 08 99 21 00 08 99 21 00 08 99 21 00 08 .!...!...!...!.. 800012c: 99 21 00 08 99 21 00 08 99 21 00 08 99 21 00 08 .!...!...!...!.. 800013c: 99 21 00 08 99 21 00 08 99 21 00 08 99 21 00 08 .!...!...!...!.. 800014c: 99 21 00 08 99 21 00 08 99 21 00 08 99 21 00 08 .!...!...!...!.. 800015c: 99 21 00 08 99 21 00 08 99 21 00 08 99 21 00 08 .!...!...!...!.. 800016c: 99 21 00 08 99 21 00 08 99 21 00 08 99 21 00 08 .!...!...!...!.. 800017c: 99 21 00 08 99 21 00 08 99 21 00 08 .!...!...!.. 08000188 : static char line[LINE_BUFFER_SIZE]; // Line to be executed. Zero-terminated. static uint8_t char_counter; // Last character counter in line variable. static uint8_t iscomment; // Comment/block delete flag for processor to ignore comment characters. static void status_message(int status_code) { 8000188: b580 push {r7, lr} 800018a: b082 sub sp, #8 800018c: af00 add r7, sp, #0 800018e: 6078 str r0, [r7, #4] if (status_code == 0) { 8000190: 687b ldr r3, [r7, #4] 8000192: 2b00 cmp r3, #0 8000194: d106 bne.n 80001a4 printPgmString("ok\r\n"); 8000196: f64a 2090 movw r0, #43664 ; 0xaa90 800019a: f6c0 0000 movt r0, #2048 ; 0x800 800019e: f000 fabd bl 800071c 80001a2: e03a b.n 800021a } else { printPgmString("error: "); 80001a4: f64a 2098 movw r0, #43672 ; 0xaa98 80001a8: f6c0 0000 movt r0, #2048 ; 0x800 80001ac: f000 fab6 bl 800071c switch(status_code) { 80001b0: 687b ldr r3, [r7, #4] 80001b2: f103 33ff add.w r3, r3, #4294967295 80001b6: 2b03 cmp r3, #3 80001b8: d826 bhi.n 8000208 80001ba: a201 add r2, pc, #4 ; (adr r2, 80001c0 ) 80001bc: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80001c0: 080001d1 .word 0x080001d1 80001c4: 080001df .word 0x080001df 80001c8: 080001ed .word 0x080001ed 80001cc: 080001fb .word 0x080001fb case STATUS_BAD_NUMBER_FORMAT: printPgmString("Bad number format\r\n"); break; 80001d0: f64a 20a0 movw r0, #43680 ; 0xaaa0 80001d4: f6c0 0000 movt r0, #2048 ; 0x800 80001d8: f000 faa0 bl 800071c 80001dc: e01d b.n 800021a case STATUS_EXPECTED_COMMAND_LETTER: printPgmString("Expected command letter\r\n"); break; 80001de: f64a 20b4 movw r0, #43700 ; 0xaab4 80001e2: f6c0 0000 movt r0, #2048 ; 0x800 80001e6: f000 fa99 bl 800071c 80001ea: e016 b.n 800021a case STATUS_UNSUPPORTED_STATEMENT: printPgmString("Unsupported statement\r\n"); break; 80001ec: f64a 20d0 movw r0, #43728 ; 0xaad0 80001f0: f6c0 0000 movt r0, #2048 ; 0x800 80001f4: f000 fa92 bl 800071c 80001f8: e00f b.n 800021a case STATUS_FLOATING_POINT_ERROR: printPgmString("Floating point error\r\n"); break; 80001fa: f64a 20e8 movw r0, #43752 ; 0xaae8 80001fe: f6c0 0000 movt r0, #2048 ; 0x800 8000202: f000 fa8b bl 800071c 8000206: e008 b.n 800021a default: printInteger(status_code); 8000208: 6878 ldr r0, [r7, #4] 800020a: f000 fafd bl 8000808 printPgmString("\r\n"); 800020e: f64a 3000 movw r0, #43776 ; 0xab00 8000212: f6c0 0000 movt r0, #2048 ; 0x800 8000216: f000 fa81 bl 800071c } } } 800021a: f107 0708 add.w r7, r7, #8 800021e: 46bd mov sp, r7 8000220: bd80 pop {r7, pc} 8000222: bf00 nop 08000224 : void protocol_init() { 8000224: b580 push {r7, lr} 8000226: af00 add r7, sp, #0 char_counter = 0; // Reset line input 8000228: f240 4372 movw r3, #1138 ; 0x472 800022c: f2c2 0300 movt r3, #8192 ; 0x2000 8000230: f04f 0200 mov.w r2, #0 8000234: 701a strb r2, [r3, #0] iscomment = false; 8000236: f240 4373 movw r3, #1139 ; 0x473 800023a: f2c2 0300 movt r3, #8192 ; 0x2000 800023e: f04f 0200 mov.w r2, #0 8000242: 701a strb r2, [r3, #0] printPgmString("\r\nGrbl " GRBL_VERSION); 8000244: f64a 3004 movw r0, #43780 ; 0xab04 8000248: f6c0 0000 movt r0, #2048 ; 0x800 800024c: f000 fa66 bl 800071c printPgmString("\r\n"); 8000250: f64a 3000 movw r0, #43776 ; 0xab00 8000254: f6c0 0000 movt r0, #2048 ; 0x800 8000258: f000 fa60 bl 800071c } 800025c: bd80 pop {r7, pc} 800025e: bf00 nop 08000260 : // Executes one line of input according to protocol uint8_t protocol_execute_line(char *line) { 8000260: b580 push {r7, lr} 8000262: b082 sub sp, #8 8000264: af00 add r7, sp, #0 8000266: 6078 str r0, [r7, #4] if(line[0] == '$') { 8000268: 687b ldr r3, [r7, #4] 800026a: 781b ldrb r3, [r3, #0] 800026c: 2b24 cmp r3, #36 ; 0x24 800026e: d104 bne.n 800027a return(settings_execute_line(line)); // Delegate lines starting with '$' to the settings module 8000270: 6878 ldr r0, [r7, #4] 8000272: f003 f9b9 bl 80035e8 8000276: 4603 mov r3, r0 8000278: e003 b.n 8000282 } else { return(gc_execute_line(line)); // Everything else is gcode 800027a: 6878 ldr r0, [r7, #4] 800027c: f000 fc30 bl 8000ae0 8000280: 4603 mov r3, r0 } } 8000282: 4618 mov r0, r3 8000284: f107 0708 add.w r7, r7, #8 8000288: 46bd mov sp, r7 800028a: bd80 pop {r7, pc} 0800028c : // Process one line of incoming serial data. Remove unneeded characters and capitalize. void protocol_process() { 800028c: b580 push {r7, lr} 800028e: b084 sub sp, #16 8000290: af00 add r7, sp, #0 char c; //while((c = serial_read()) != SERIAL_NO_DATA) char s[] = "G01 X-10"; 8000292: f64a 3210 movw r2, #43792 ; 0xab10 8000296: f6c0 0200 movt r2, #2048 ; 0x800 800029a: 463b mov r3, r7 800029c: ca07 ldmia r2, {r0, r1, r2} 800029e: c303 stmia r3!, {r0, r1} 80002a0: 701a strb r2, [r3, #0] s[8]='\n'; 80002a2: f04f 030a mov.w r3, #10 80002a6: 723b strb r3, [r7, #8] int i=0; 80002a8: f04f 0300 mov.w r3, #0 80002ac: 60fb str r3, [r7, #12] while(s[i]!=0) 80002ae: e09c b.n 80003ea { c=s[i]; 80002b0: 463a mov r2, r7 80002b2: 68fb ldr r3, [r7, #12] 80002b4: 18d3 adds r3, r2, r3 80002b6: 781b ldrb r3, [r3, #0] 80002b8: 72fb strb r3, [r7, #11] i++; 80002ba: 68fb ldr r3, [r7, #12] 80002bc: f103 0301 add.w r3, r3, #1 80002c0: 60fb str r3, [r7, #12] if ((c == '\n') || (c == '\r')) { // End of line reached 80002c2: 7afb ldrb r3, [r7, #11] 80002c4: 2b0a cmp r3, #10 80002c6: d002 beq.n 80002ce 80002c8: 7afb ldrb r3, [r7, #11] 80002ca: 2b0d cmp r3, #13 80002cc: d131 bne.n 8000332 if (char_counter > 0) {// Line is complete. Then execute! 80002ce: f240 4372 movw r3, #1138 ; 0x472 80002d2: f2c2 0300 movt r3, #8192 ; 0x2000 80002d6: 781b ldrb r3, [r3, #0] 80002d8: 2b00 cmp r3, #0 80002da: d017 beq.n 800030c line[char_counter] = 0; // Terminate string 80002dc: f240 4372 movw r3, #1138 ; 0x472 80002e0: f2c2 0300 movt r3, #8192 ; 0x2000 80002e4: 781b ldrb r3, [r3, #0] 80002e6: 461a mov r2, r3 80002e8: f240 4340 movw r3, #1088 ; 0x440 80002ec: f2c2 0300 movt r3, #8192 ; 0x2000 80002f0: f04f 0100 mov.w r1, #0 80002f4: 5499 strb r1, [r3, r2] status_message(protocol_execute_line(line)); 80002f6: f240 4040 movw r0, #1088 ; 0x440 80002fa: f2c2 0000 movt r0, #8192 ; 0x2000 80002fe: f7ff ffaf bl 8000260 8000302: 4603 mov r3, r0 8000304: 4618 mov r0, r3 8000306: f7ff ff3f bl 8000188 800030a: e003 b.n 8000314 } else { // Empty or comment line. Skip block. status_message(STATUS_OK); // Send status message for syncing purposes. 800030c: f04f 0000 mov.w r0, #0 8000310: f7ff ff3a bl 8000188 } char_counter = 0; // Reset line buffer index 8000314: f240 4372 movw r3, #1138 ; 0x472 8000318: f2c2 0300 movt r3, #8192 ; 0x2000 800031c: f04f 0200 mov.w r2, #0 8000320: 701a strb r2, [r3, #0] iscomment = false; // Reset comment flag 8000322: f240 4373 movw r3, #1139 ; 0x473 8000326: f2c2 0300 movt r3, #8192 ; 0x2000 800032a: f04f 0200 mov.w r2, #0 800032e: 701a strb r2, [r3, #0] 8000330: e05b b.n 80003ea } else { if (iscomment) { 8000332: f240 4373 movw r3, #1139 ; 0x473 8000336: f2c2 0300 movt r3, #8192 ; 0x2000 800033a: 781b ldrb r3, [r3, #0] 800033c: 2b00 cmp r3, #0 800033e: d00a beq.n 8000356 // Throw away all comment characters if (c == ')') { 8000340: 7afb ldrb r3, [r7, #11] 8000342: 2b29 cmp r3, #41 ; 0x29 8000344: d151 bne.n 80003ea // End of comment. Resume line. iscomment = false; 8000346: f240 4373 movw r3, #1139 ; 0x473 800034a: f2c2 0300 movt r3, #8192 ; 0x2000 800034e: f04f 0200 mov.w r2, #0 8000352: 701a strb r2, [r3, #0] 8000354: e049 b.n 80003ea } } else { if (c <= ' ') { 8000356: 7afb ldrb r3, [r7, #11] 8000358: 2b20 cmp r3, #32 800035a: d946 bls.n 80003ea // Throw away whitepace and control characters } else if (c == '/') { 800035c: 7afb ldrb r3, [r7, #11] 800035e: 2b2f cmp r3, #47 ; 0x2f 8000360: d043 beq.n 80003ea // Disable block delete and throw away character // To enable block delete, uncomment following line. Will ignore until EOL. // iscomment = true; } else if (c == '(') { 8000362: 7afb ldrb r3, [r7, #11] 8000364: 2b28 cmp r3, #40 ; 0x28 8000366: d107 bne.n 8000378 // Enable comments flag and ignore all characters until ')' or EOL. iscomment = true; 8000368: f240 4373 movw r3, #1139 ; 0x473 800036c: f2c2 0300 movt r3, #8192 ; 0x2000 8000370: f04f 0201 mov.w r2, #1 8000374: 701a strb r2, [r3, #0] 8000376: e038 b.n 80003ea } else if (char_counter >= LINE_BUFFER_SIZE-1) { 8000378: f240 4372 movw r3, #1138 ; 0x472 800037c: f2c2 0300 movt r3, #8192 ; 0x2000 8000380: 781b ldrb r3, [r3, #0] 8000382: 2b30 cmp r3, #48 ; 0x30 8000384: d831 bhi.n 80003ea // Throw away any characters beyond the end of the line buffer } else if (c >= 'a' && c <= 'z') { // Upcase lowercase 8000386: 7afb ldrb r3, [r7, #11] 8000388: 2b60 cmp r3, #96 ; 0x60 800038a: d91a bls.n 80003c2 800038c: 7afb ldrb r3, [r7, #11] 800038e: 2b7a cmp r3, #122 ; 0x7a 8000390: d817 bhi.n 80003c2 line[char_counter++] = c-'a'+'A'; 8000392: f240 4372 movw r3, #1138 ; 0x472 8000396: f2c2 0300 movt r3, #8192 ; 0x2000 800039a: 781a ldrb r2, [r3, #0] 800039c: 4611 mov r1, r2 800039e: 7afb ldrb r3, [r7, #11] 80003a0: f1a3 0320 sub.w r3, r3, #32 80003a4: b2d8 uxtb r0, r3 80003a6: f240 4340 movw r3, #1088 ; 0x440 80003aa: f2c2 0300 movt r3, #8192 ; 0x2000 80003ae: 5458 strb r0, [r3, r1] 80003b0: f102 0301 add.w r3, r2, #1 80003b4: b2da uxtb r2, r3 80003b6: f240 4372 movw r3, #1138 ; 0x472 80003ba: f2c2 0300 movt r3, #8192 ; 0x2000 80003be: 701a strb r2, [r3, #0] 80003c0: e013 b.n 80003ea } else { line[char_counter++] = c; 80003c2: f240 4372 movw r3, #1138 ; 0x472 80003c6: f2c2 0300 movt r3, #8192 ; 0x2000 80003ca: 781a ldrb r2, [r3, #0] 80003cc: 4611 mov r1, r2 80003ce: f240 4340 movw r3, #1088 ; 0x440 80003d2: f2c2 0300 movt r3, #8192 ; 0x2000 80003d6: 7af8 ldrb r0, [r7, #11] 80003d8: 5458 strb r0, [r3, r1] 80003da: f102 0301 add.w r3, r2, #1 80003de: b2da uxtb r2, r3 80003e0: f240 4372 movw r3, #1138 ; 0x472 80003e4: f2c2 0300 movt r3, #8192 ; 0x2000 80003e8: 701a strb r2, [r3, #0] char c; //while((c = serial_read()) != SERIAL_NO_DATA) char s[] = "G01 X-10"; s[8]='\n'; int i=0; while(s[i]!=0) 80003ea: 463a mov r2, r7 80003ec: 68fb ldr r3, [r7, #12] 80003ee: 18d3 adds r3, r2, r3 80003f0: 781b ldrb r3, [r3, #0] 80003f2: 2b00 cmp r3, #0 80003f4: f47f af5c bne.w 80002b0 line[char_counter++] = c; } } } } } 80003f8: f107 0710 add.w r7, r7, #16 80003fc: 46bd mov sp, r7 80003fe: bd80 pop {r7, pc} 08000400 : * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains * the configuration information for the specified USART peripheral. * @retval None */ void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) { 8000400: b580 push {r7, lr} 8000402: b08a sub sp, #40 ; 0x28 8000404: af00 add r7, sp, #0 8000406: 6078 str r0, [r7, #4] 8000408: 6039 str r1, [r7, #0] uint32_t tmpreg = 0x00, apbclock = 0x00; 800040a: f04f 0300 mov.w r3, #0 800040e: 627b str r3, [r7, #36] ; 0x24 8000410: f04f 0300 mov.w r3, #0 8000414: 623b str r3, [r7, #32] uint32_t integerdivider = 0x00; 8000416: f04f 0300 mov.w r3, #0 800041a: 61fb str r3, [r7, #28] uint32_t fractionaldivider = 0x00; 800041c: f04f 0300 mov.w r3, #0 8000420: 61bb str r3, [r7, #24] { assert_param(IS_USART_1236_PERIPH(USARTx)); } /*---------------------------- USART CR2 Configuration -----------------------*/ tmpreg = USARTx->CR2; 8000422: 687b ldr r3, [r7, #4] 8000424: 8a1b ldrh r3, [r3, #16] 8000426: b29b uxth r3, r3 8000428: 627b str r3, [r7, #36] ; 0x24 /* Clear STOP[13:12] bits */ tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP); 800042a: 6a7b ldr r3, [r7, #36] ; 0x24 800042c: f423 5340 bic.w r3, r3, #12288 ; 0x3000 8000430: 627b str r3, [r7, #36] ; 0x24 /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit : Set STOP[13:12] bits according to USART_StopBits value */ tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; 8000432: 683b ldr r3, [r7, #0] 8000434: 88db ldrh r3, [r3, #6] 8000436: 6a7a ldr r2, [r7, #36] ; 0x24 8000438: 4313 orrs r3, r2 800043a: 627b str r3, [r7, #36] ; 0x24 /* Write to USART CR2 */ USARTx->CR2 = (uint16_t)tmpreg; 800043c: 6a7b ldr r3, [r7, #36] ; 0x24 800043e: b29a uxth r2, r3 8000440: 687b ldr r3, [r7, #4] 8000442: 821a strh r2, [r3, #16] /*---------------------------- USART CR1 Configuration -----------------------*/ tmpreg = USARTx->CR1; 8000444: 687b ldr r3, [r7, #4] 8000446: 899b ldrh r3, [r3, #12] 8000448: b29b uxth r3, r3 800044a: 627b str r3, [r7, #36] ; 0x24 /* Clear M, PCE, PS, TE and RE bits */ tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK); 800044c: 6a7b ldr r3, [r7, #36] ; 0x24 800044e: f423 53b0 bic.w r3, r3, #5632 ; 0x1600 8000452: f023 030c bic.w r3, r3, #12 8000456: 627b str r3, [r7, #36] ; 0x24 /* Configure the USART Word Length, Parity and mode: Set the M bits according to USART_WordLength value Set PCE and PS bits according to USART_Parity value Set TE and RE bits according to USART_Mode value */ tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | 8000458: 683b ldr r3, [r7, #0] 800045a: 889a ldrh r2, [r3, #4] 800045c: 683b ldr r3, [r7, #0] 800045e: 891b ldrh r3, [r3, #8] 8000460: 4313 orrs r3, r2 8000462: b29a uxth r2, r3 USART_InitStruct->USART_Mode; 8000464: 683b ldr r3, [r7, #0] 8000466: 895b ldrh r3, [r3, #10] /* Configure the USART Word Length, Parity and mode: Set the M bits according to USART_WordLength value Set PCE and PS bits according to USART_Parity value Set TE and RE bits according to USART_Mode value */ tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | 8000468: 4313 orrs r3, r2 800046a: b29b uxth r3, r3 800046c: 6a7a ldr r2, [r7, #36] ; 0x24 800046e: 4313 orrs r3, r2 8000470: 627b str r3, [r7, #36] ; 0x24 USART_InitStruct->USART_Mode; /* Write to USART CR1 */ USARTx->CR1 = (uint16_t)tmpreg; 8000472: 6a7b ldr r3, [r7, #36] ; 0x24 8000474: b29a uxth r2, r3 8000476: 687b ldr r3, [r7, #4] 8000478: 819a strh r2, [r3, #12] /*---------------------------- USART CR3 Configuration -----------------------*/ tmpreg = USARTx->CR3; 800047a: 687b ldr r3, [r7, #4] 800047c: 8a9b ldrh r3, [r3, #20] 800047e: b29b uxth r3, r3 8000480: 627b str r3, [r7, #36] ; 0x24 /* Clear CTSE and RTSE bits */ tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK); 8000482: 6a7b ldr r3, [r7, #36] ; 0x24 8000484: f423 7340 bic.w r3, r3, #768 ; 0x300 8000488: 627b str r3, [r7, #36] ; 0x24 /* Configure the USART HFC : Set CTSE and RTSE bits according to USART_HardwareFlowControl value */ tmpreg |= USART_InitStruct->USART_HardwareFlowControl; 800048a: 683b ldr r3, [r7, #0] 800048c: 899b ldrh r3, [r3, #12] 800048e: 6a7a ldr r2, [r7, #36] ; 0x24 8000490: 4313 orrs r3, r2 8000492: 627b str r3, [r7, #36] ; 0x24 /* Write to USART CR3 */ USARTx->CR3 = (uint16_t)tmpreg; 8000494: 6a7b ldr r3, [r7, #36] ; 0x24 8000496: b29a uxth r2, r3 8000498: 687b ldr r3, [r7, #4] 800049a: 829a strh r2, [r3, #20] /*---------------------------- USART BRR Configuration -----------------------*/ /* Configure the USART Baud Rate */ RCC_GetClocksFreq(&RCC_ClocksStatus); 800049c: f107 0308 add.w r3, r7, #8 80004a0: 4618 mov r0, r3 80004a2: f001 ff25 bl 80022f0 if ((USARTx == USART1) || (USARTx == USART6)) 80004a6: 687a ldr r2, [r7, #4] 80004a8: f44f 5380 mov.w r3, #4096 ; 0x1000 80004ac: f2c4 0301 movt r3, #16385 ; 0x4001 80004b0: 429a cmp r2, r3 80004b2: d006 beq.n 80004c2 80004b4: 687a ldr r2, [r7, #4] 80004b6: f44f 53a0 mov.w r3, #5120 ; 0x1400 80004ba: f2c4 0301 movt r3, #16385 ; 0x4001 80004be: 429a cmp r2, r3 80004c0: d102 bne.n 80004c8 { apbclock = RCC_ClocksStatus.PCLK2_Frequency; 80004c2: 697b ldr r3, [r7, #20] 80004c4: 623b str r3, [r7, #32] 80004c6: e001 b.n 80004cc } else { apbclock = RCC_ClocksStatus.PCLK1_Frequency; 80004c8: 693b ldr r3, [r7, #16] 80004ca: 623b str r3, [r7, #32] } /* Determine the integer part */ if ((USARTx->CR1 & USART_CR1_OVER8) != 0) 80004cc: 687b ldr r3, [r7, #4] 80004ce: 899b ldrh r3, [r3, #12] 80004d0: b29b uxth r3, r3 80004d2: b29b uxth r3, r3 80004d4: b21b sxth r3, r3 80004d6: 2b00 cmp r3, #0 80004d8: da0f bge.n 80004fa { /* Integer part computing in case Oversampling mode is 8 Samples */ integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate))); 80004da: 6a3a ldr r2, [r7, #32] 80004dc: 4613 mov r3, r2 80004de: ea4f 0383 mov.w r3, r3, lsl #2 80004e2: 189b adds r3, r3, r2 80004e4: ea4f 0283 mov.w r2, r3, lsl #2 80004e8: 189a adds r2, r3, r2 80004ea: 683b ldr r3, [r7, #0] 80004ec: 681b ldr r3, [r3, #0] 80004ee: ea4f 0343 mov.w r3, r3, lsl #1 80004f2: fbb2 f3f3 udiv r3, r2, r3 80004f6: 61fb str r3, [r7, #28] 80004f8: e00e b.n 8000518 } else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ { /* Integer part computing in case Oversampling mode is 16 Samples */ integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); 80004fa: 6a3a ldr r2, [r7, #32] 80004fc: 4613 mov r3, r2 80004fe: ea4f 0383 mov.w r3, r3, lsl #2 8000502: 189b adds r3, r3, r2 8000504: ea4f 0283 mov.w r2, r3, lsl #2 8000508: 189a adds r2, r3, r2 800050a: 683b ldr r3, [r7, #0] 800050c: 681b ldr r3, [r3, #0] 800050e: ea4f 0383 mov.w r3, r3, lsl #2 8000512: fbb2 f3f3 udiv r3, r2, r3 8000516: 61fb str r3, [r7, #28] } tmpreg = (integerdivider / 100) << 4; 8000518: 69fa ldr r2, [r7, #28] 800051a: f248 531f movw r3, #34079 ; 0x851f 800051e: f2c5 13eb movt r3, #20971 ; 0x51eb 8000522: fba3 1302 umull r1, r3, r3, r2 8000526: ea4f 1353 mov.w r3, r3, lsr #5 800052a: ea4f 1303 mov.w r3, r3, lsl #4 800052e: 627b str r3, [r7, #36] ; 0x24 /* Determine the fractional part */ fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); 8000530: 6a7b ldr r3, [r7, #36] ; 0x24 8000532: ea4f 1313 mov.w r3, r3, lsr #4 8000536: f04f 0264 mov.w r2, #100 ; 0x64 800053a: fb02 f303 mul.w r3, r2, r3 800053e: 69fa ldr r2, [r7, #28] 8000540: 1ad3 subs r3, r2, r3 8000542: 61bb str r3, [r7, #24] /* Implement the fractional part in the register */ if ((USARTx->CR1 & USART_CR1_OVER8) != 0) 8000544: 687b ldr r3, [r7, #4] 8000546: 899b ldrh r3, [r3, #12] 8000548: b29b uxth r3, r3 800054a: b29b uxth r3, r3 800054c: b21b sxth r3, r3 800054e: 2b00 cmp r3, #0 8000550: da12 bge.n 8000578 { tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07); 8000552: 69bb ldr r3, [r7, #24] 8000554: ea4f 03c3 mov.w r3, r3, lsl #3 8000558: f103 0232 add.w r2, r3, #50 ; 0x32 800055c: f248 531f movw r3, #34079 ; 0x851f 8000560: f2c5 13eb movt r3, #20971 ; 0x51eb 8000564: fba3 1302 umull r1, r3, r3, r2 8000568: ea4f 1353 mov.w r3, r3, lsr #5 800056c: f003 0307 and.w r3, r3, #7 8000570: 6a7a ldr r2, [r7, #36] ; 0x24 8000572: 4313 orrs r3, r2 8000574: 627b str r3, [r7, #36] ; 0x24 8000576: e011 b.n 800059c } else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */ { tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); 8000578: 69bb ldr r3, [r7, #24] 800057a: ea4f 1303 mov.w r3, r3, lsl #4 800057e: f103 0232 add.w r2, r3, #50 ; 0x32 8000582: f248 531f movw r3, #34079 ; 0x851f 8000586: f2c5 13eb movt r3, #20971 ; 0x51eb 800058a: fba3 1302 umull r1, r3, r3, r2 800058e: ea4f 1353 mov.w r3, r3, lsr #5 8000592: f003 030f and.w r3, r3, #15 8000596: 6a7a ldr r2, [r7, #36] ; 0x24 8000598: 4313 orrs r3, r2 800059a: 627b str r3, [r7, #36] ; 0x24 } /* Write to USART BRR register */ USARTx->BRR = (uint16_t)tmpreg; 800059c: 6a7b ldr r3, [r7, #36] ; 0x24 800059e: b29a uxth r2, r3 80005a0: 687b ldr r3, [r7, #4] 80005a2: 811a strh r2, [r3, #8] } 80005a4: f107 0728 add.w r7, r7, #40 ; 0x28 80005a8: 46bd mov sp, r7 80005aa: bd80 pop {r7, pc} 080005ac : * @param NewState: new state of the USARTx peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) { 80005ac: b480 push {r7} 80005ae: b083 sub sp, #12 80005b0: af00 add r7, sp, #0 80005b2: 6078 str r0, [r7, #4] 80005b4: 460b mov r3, r1 80005b6: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 80005b8: 78fb ldrb r3, [r7, #3] 80005ba: 2b00 cmp r3, #0 80005bc: d008 beq.n 80005d0 { /* Enable the selected USART by setting the UE bit in the CR1 register */ USARTx->CR1 |= USART_CR1_UE; 80005be: 687b ldr r3, [r7, #4] 80005c0: 899b ldrh r3, [r3, #12] 80005c2: b29b uxth r3, r3 80005c4: f443 5300 orr.w r3, r3, #8192 ; 0x2000 80005c8: b29a uxth r2, r3 80005ca: 687b ldr r3, [r7, #4] 80005cc: 819a strh r2, [r3, #12] 80005ce: e007 b.n 80005e0 } else { /* Disable the selected USART by clearing the UE bit in the CR1 register */ USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE); 80005d0: 687b ldr r3, [r7, #4] 80005d2: 899b ldrh r3, [r3, #12] 80005d4: b29b uxth r3, r3 80005d6: f423 5300 bic.w r3, r3, #8192 ; 0x2000 80005da: b29a uxth r2, r3 80005dc: 687b ldr r3, [r7, #4] 80005de: 819a strh r2, [r3, #12] } } 80005e0: f107 070c add.w r7, r7, #12 80005e4: 46bd mov sp, r7 80005e6: bc80 pop {r7} 80005e8: 4770 bx lr 80005ea: bf00 nop 080005ec : * UART peripheral. * @param Data: the data to transmit. * @retval None */ void USART_SendData(USART_TypeDef* USARTx, uint16_t Data) { 80005ec: b480 push {r7} 80005ee: b083 sub sp, #12 80005f0: af00 add r7, sp, #0 80005f2: 6078 str r0, [r7, #4] 80005f4: 460b mov r3, r1 80005f6: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); assert_param(IS_USART_DATA(Data)); /* Transmit Data */ USARTx->DR = (Data & (uint16_t)0x01FF); 80005f8: 887b ldrh r3, [r7, #2] 80005fa: ea4f 53c3 mov.w r3, r3, lsl #23 80005fe: ea4f 53d3 mov.w r3, r3, lsr #23 8000602: b29a uxth r2, r3 8000604: 687b ldr r3, [r7, #4] 8000606: 809a strh r2, [r3, #4] } 8000608: f107 070c add.w r7, r7, #12 800060c: 46bd mov sp, r7 800060e: bc80 pop {r7} 8000610: 4770 bx lr 8000612: bf00 nop 08000614 : * @param USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or * UART peripheral. * @retval The received data. */ uint16_t USART_ReceiveData(USART_TypeDef* USARTx) { 8000614: b480 push {r7} 8000616: b083 sub sp, #12 8000618: af00 add r7, sp, #0 800061a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_USART_ALL_PERIPH(USARTx)); /* Receive Data */ return (uint16_t)(USARTx->DR & (uint16_t)0x01FF); 800061c: 687b ldr r3, [r7, #4] 800061e: 889b ldrh r3, [r3, #4] 8000620: b29b uxth r3, r3 8000622: ea4f 53c3 mov.w r3, r3, lsl #23 8000626: ea4f 53d3 mov.w r3, r3, lsr #23 800062a: b29b uxth r3, r3 } 800062c: 4618 mov r0, r3 800062e: f107 070c add.w r7, r7, #12 8000632: 46bd mov sp, r7 8000634: bc80 pop {r7} 8000636: 4770 bx lr 08000638 : * @param NewState: new state of the specified USARTx interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState) { 8000638: b480 push {r7} 800063a: b087 sub sp, #28 800063c: af00 add r7, sp, #0 800063e: 6078 str r0, [r7, #4] 8000640: 4613 mov r3, r2 8000642: 460a mov r2, r1 8000644: 807a strh r2, [r7, #2] 8000646: 707b strb r3, [r7, #1] uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; 8000648: f04f 0300 mov.w r3, #0 800064c: 613b str r3, [r7, #16] 800064e: f04f 0300 mov.w r3, #0 8000652: 60fb str r3, [r7, #12] 8000654: f04f 0300 mov.w r3, #0 8000658: 60bb str r3, [r7, #8] uint32_t usartxbase = 0x00; 800065a: f04f 0300 mov.w r3, #0 800065e: 617b str r3, [r7, #20] if (USART_IT == USART_IT_CTS) { assert_param(IS_USART_1236_PERIPH(USARTx)); } usartxbase = (uint32_t)USARTx; 8000660: 687b ldr r3, [r7, #4] 8000662: 617b str r3, [r7, #20] /* Get the USART register index */ usartreg = (((uint8_t)USART_IT) >> 0x05); 8000664: 887b ldrh r3, [r7, #2] 8000666: b2db uxtb r3, r3 8000668: ea4f 1353 mov.w r3, r3, lsr #5 800066c: b2db uxtb r3, r3 800066e: 613b str r3, [r7, #16] /* Get the interrupt position */ itpos = USART_IT & IT_MASK; 8000670: 887b ldrh r3, [r7, #2] 8000672: f003 031f and.w r3, r3, #31 8000676: 60fb str r3, [r7, #12] itmask = (((uint32_t)0x01) << itpos); 8000678: 68fb ldr r3, [r7, #12] 800067a: f04f 0201 mov.w r2, #1 800067e: fa02 f303 lsl.w r3, r2, r3 8000682: 60bb str r3, [r7, #8] if (usartreg == 0x01) /* The IT is in CR1 register */ 8000684: 693b ldr r3, [r7, #16] 8000686: 2b01 cmp r3, #1 8000688: d104 bne.n 8000694 { usartxbase += 0x0C; 800068a: 697b ldr r3, [r7, #20] 800068c: f103 030c add.w r3, r3, #12 8000690: 617b str r3, [r7, #20] 8000692: e00b b.n 80006ac } else if (usartreg == 0x02) /* The IT is in CR2 register */ 8000694: 693b ldr r3, [r7, #16] 8000696: 2b02 cmp r3, #2 8000698: d104 bne.n 80006a4 { usartxbase += 0x10; 800069a: 697b ldr r3, [r7, #20] 800069c: f103 0310 add.w r3, r3, #16 80006a0: 617b str r3, [r7, #20] 80006a2: e003 b.n 80006ac } else /* The IT is in CR3 register */ { usartxbase += 0x14; 80006a4: 697b ldr r3, [r7, #20] 80006a6: f103 0314 add.w r3, r3, #20 80006aa: 617b str r3, [r7, #20] } if (NewState != DISABLE) 80006ac: 787b ldrb r3, [r7, #1] 80006ae: 2b00 cmp r3, #0 80006b0: d006 beq.n 80006c0 { *(__IO uint32_t*)usartxbase |= itmask; 80006b2: 697b ldr r3, [r7, #20] 80006b4: 697a ldr r2, [r7, #20] 80006b6: 6811 ldr r1, [r2, #0] 80006b8: 68ba ldr r2, [r7, #8] 80006ba: 430a orrs r2, r1 80006bc: 601a str r2, [r3, #0] 80006be: e007 b.n 80006d0 } else { *(__IO uint32_t*)usartxbase &= ~itmask; 80006c0: 697b ldr r3, [r7, #20] 80006c2: 697a ldr r2, [r7, #20] 80006c4: 6811 ldr r1, [r2, #0] 80006c6: 68ba ldr r2, [r7, #8] 80006c8: ea6f 0202 mvn.w r2, r2 80006cc: 400a ands r2, r1 80006ce: 601a str r2, [r3, #0] } } 80006d0: f107 071c add.w r7, r7, #28 80006d4: 46bd mov sp, r7 80006d6: bc80 pop {r7} 80006d8: 4770 bx lr 80006da: bf00 nop 080006dc : * @arg USART_FLAG_FE: Framing Error flag * @arg USART_FLAG_PE: Parity Error flag * @retval The new state of USART_FLAG (SET or RESET). */ FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG) { 80006dc: b480 push {r7} 80006de: b085 sub sp, #20 80006e0: af00 add r7, sp, #0 80006e2: 6078 str r0, [r7, #4] 80006e4: 460b mov r3, r1 80006e6: 807b strh r3, [r7, #2] FlagStatus bitstatus = RESET; 80006e8: f04f 0300 mov.w r3, #0 80006ec: 73fb strb r3, [r7, #15] if (USART_FLAG == USART_FLAG_CTS) { assert_param(IS_USART_1236_PERIPH(USARTx)); } if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET) 80006ee: 687b ldr r3, [r7, #4] 80006f0: 881b ldrh r3, [r3, #0] 80006f2: b29a uxth r2, r3 80006f4: 887b ldrh r3, [r7, #2] 80006f6: 4013 ands r3, r2 80006f8: b29b uxth r3, r3 80006fa: 2b00 cmp r3, #0 80006fc: d003 beq.n 8000706 { bitstatus = SET; 80006fe: f04f 0301 mov.w r3, #1 8000702: 73fb strb r3, [r7, #15] 8000704: e002 b.n 800070c } else { bitstatus = RESET; 8000706: f04f 0300 mov.w r3, #0 800070a: 73fb strb r3, [r7, #15] } return bitstatus; 800070c: 7bfb ldrb r3, [r7, #15] } 800070e: 4618 mov r0, r3 8000710: f107 0714 add.w r7, r7, #20 8000714: 46bd mov sp, r7 8000716: bc80 pop {r7} 8000718: 4770 bx lr 800071a: bf00 nop 0800071c : serial_write(*s++); } // Print a string stored in PGM-memory void printPgmString(const char *s) { 800071c: b580 push {r7, lr} 800071e: b084 sub sp, #16 8000720: af00 add r7, sp, #0 8000722: 6078 str r0, [r7, #4] char c; //while ((c = pgm_read_byte_near(s++))) //Todo EPIC or FAIL while ((c = *(s++))) 8000724: e003 b.n 800072e serial_write(c); 8000726: 7bfb ldrb r3, [r7, #15] 8000728: 4618 mov r0, r3 800072a: f004 fc2d bl 8004f88 void printPgmString(const char *s) { char c; //while ((c = pgm_read_byte_near(s++))) //Todo EPIC or FAIL while ((c = *(s++))) 800072e: 687b ldr r3, [r7, #4] 8000730: 781b ldrb r3, [r3, #0] 8000732: 73fb strb r3, [r7, #15] 8000734: 7bfb ldrb r3, [r7, #15] 8000736: 2b00 cmp r3, #0 8000738: bf0c ite eq 800073a: 2300 moveq r3, #0 800073c: 2301 movne r3, #1 800073e: b2db uxtb r3, r3 8000740: 687a ldr r2, [r7, #4] 8000742: f102 0201 add.w r2, r2, #1 8000746: 607a str r2, [r7, #4] 8000748: 2b00 cmp r3, #0 800074a: d1ec bne.n 8000726 serial_write(c); } 800074c: f107 0710 add.w r7, r7, #16 8000750: 46bd mov sp, r7 8000752: bd80 pop {r7, pc} 08000754 : void printIntegerInBase(unsigned long n, unsigned long base) { 8000754: b580 push {r7, lr} 8000756: b08c sub sp, #48 ; 0x30 8000758: af00 add r7, sp, #0 800075a: 6078 str r0, [r7, #4] 800075c: 6039 str r1, [r7, #0] unsigned char buf[8 * sizeof(long)]; // Assumes 8-bit chars. unsigned long i = 0; 800075e: f04f 0300 mov.w r3, #0 8000762: 62fb str r3, [r7, #44] ; 0x2c if (n == 0) { 8000764: 687b ldr r3, [r7, #4] 8000766: 2b00 cmp r3, #0 8000768: d11b bne.n 80007a2 serial_write('0'); 800076a: f04f 0030 mov.w r0, #48 ; 0x30 800076e: f004 fc0b bl 8004f88 return; 8000772: e045 b.n 8000800 } while (n > 0) { buf[i++] = n % base; 8000774: 687b ldr r3, [r7, #4] 8000776: 683a ldr r2, [r7, #0] 8000778: fbb3 f2f2 udiv r2, r3, r2 800077c: 6839 ldr r1, [r7, #0] 800077e: fb01 f202 mul.w r2, r1, r2 8000782: 1a9b subs r3, r3, r2 8000784: b2da uxtb r2, r3 8000786: f107 010c add.w r1, r7, #12 800078a: 6afb ldr r3, [r7, #44] ; 0x2c 800078c: 18cb adds r3, r1, r3 800078e: 701a strb r2, [r3, #0] 8000790: 6afb ldr r3, [r7, #44] ; 0x2c 8000792: f103 0301 add.w r3, r3, #1 8000796: 62fb str r3, [r7, #44] ; 0x2c n /= base; 8000798: 687a ldr r2, [r7, #4] 800079a: 683b ldr r3, [r7, #0] 800079c: fbb2 f3f3 udiv r3, r2, r3 80007a0: 607b str r3, [r7, #4] if (n == 0) { serial_write('0'); return; } while (n > 0) { 80007a2: 687b ldr r3, [r7, #4] 80007a4: 2b00 cmp r3, #0 80007a6: d1e5 bne.n 8000774 buf[i++] = n % base; n /= base; } for (; i > 0; i--) 80007a8: e027 b.n 80007fa serial_write(buf[i - 1] < 10 ? 80007aa: 6afb ldr r3, [r7, #44] ; 0x2c 80007ac: f103 33ff add.w r3, r3, #4294967295 80007b0: f107 0230 add.w r2, r7, #48 ; 0x30 80007b4: 18d3 adds r3, r2, r3 80007b6: f813 3c24 ldrb.w r3, [r3, #-36] 80007ba: 2b09 cmp r3, #9 80007bc: d80b bhi.n 80007d6 '0' + buf[i - 1] : 80007be: 6afb ldr r3, [r7, #44] ; 0x2c 80007c0: f103 33ff add.w r3, r3, #4294967295 80007c4: f107 0230 add.w r2, r7, #48 ; 0x30 80007c8: 18d3 adds r3, r2, r3 80007ca: f813 3c24 ldrb.w r3, [r3, #-36] buf[i++] = n % base; n /= base; } for (; i > 0; i--) serial_write(buf[i - 1] < 10 ? 80007ce: f103 0330 add.w r3, r3, #48 ; 0x30 80007d2: b2db uxtb r3, r3 80007d4: e00a b.n 80007ec '0' + buf[i - 1] : 'A' + buf[i - 1] - 10); 80007d6: 6afb ldr r3, [r7, #44] ; 0x2c 80007d8: f103 33ff add.w r3, r3, #4294967295 80007dc: f107 0230 add.w r2, r7, #48 ; 0x30 80007e0: 18d3 adds r3, r2, r3 80007e2: f813 3c24 ldrb.w r3, [r3, #-36] buf[i++] = n % base; n /= base; } for (; i > 0; i--) serial_write(buf[i - 1] < 10 ? 80007e6: f103 0337 add.w r3, r3, #55 ; 0x37 80007ea: b2db uxtb r3, r3 80007ec: 4618 mov r0, r3 80007ee: f004 fbcb bl 8004f88 while (n > 0) { buf[i++] = n % base; n /= base; } for (; i > 0; i--) 80007f2: 6afb ldr r3, [r7, #44] ; 0x2c 80007f4: f103 33ff add.w r3, r3, #4294967295 80007f8: 62fb str r3, [r7, #44] ; 0x2c 80007fa: 6afb ldr r3, [r7, #44] ; 0x2c 80007fc: 2b00 cmp r3, #0 80007fe: d1d4 bne.n 80007aa serial_write(buf[i - 1] < 10 ? '0' + buf[i - 1] : 'A' + buf[i - 1] - 10); } 8000800: f107 0730 add.w r7, r7, #48 ; 0x30 8000804: 46bd mov sp, r7 8000806: bd80 pop {r7, pc} 08000808 : void printInteger(long n) { 8000808: b580 push {r7, lr} 800080a: b082 sub sp, #8 800080c: af00 add r7, sp, #0 800080e: 6078 str r0, [r7, #4] if (n < 0) { 8000810: 687b ldr r3, [r7, #4] 8000812: 2b00 cmp r3, #0 8000814: da07 bge.n 8000826 serial_write('-'); 8000816: f04f 002d mov.w r0, #45 ; 0x2d 800081a: f004 fbb5 bl 8004f88 n = -n; 800081e: 687b ldr r3, [r7, #4] 8000820: f1c3 0300 rsb r3, r3, #0 8000824: 607b str r3, [r7, #4] } printIntegerInBase(n, 10); 8000826: 687b ldr r3, [r7, #4] 8000828: 4618 mov r0, r3 800082a: f04f 010a mov.w r1, #10 800082e: f7ff ff91 bl 8000754 } 8000832: f107 0708 add.w r7, r7, #8 8000836: 46bd mov sp, r7 8000838: bd80 pop {r7, pc} 800083a: bf00 nop 800083c: 0000 movs r0, r0 ... 08000840 : // A very simple void printFloat(double n) { 8000840: b590 push {r4, r7, lr} 8000842: b087 sub sp, #28 8000844: af00 add r7, sp, #0 8000846: e9c7 0100 strd r0, r1, [r7] if (n < 0) { 800084a: f04f 0301 mov.w r3, #1 800084e: 461c mov r4, r3 8000850: e9d7 0100 ldrd r0, r1, [r7] 8000854: a33c add r3, pc, #240 ; (adr r3, 8000948 ) 8000856: e9d3 2300 ldrd r2, r3, [r3] 800085a: f008 fc33 bl 80090c4 <__aeabi_dcmplt> 800085e: 4603 mov r3, r0 8000860: 2b00 cmp r3, #0 8000862: d102 bne.n 800086a 8000864: f04f 0300 mov.w r3, #0 8000868: 461c mov r4, r3 800086a: b2e3 uxtb r3, r4 800086c: 2b00 cmp r3, #0 800086e: d009 beq.n 8000884 serial_write('-'); 8000870: f04f 002d mov.w r0, #45 ; 0x2d 8000874: f004 fb88 bl 8004f88 n = -n; 8000878: 683b ldr r3, [r7, #0] 800087a: 603b str r3, [r7, #0] 800087c: 687b ldr r3, [r7, #4] 800087e: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 8000882: 607b str r3, [r7, #4] } n += 0.5/DECIMAL_MULTIPLIER; // Add rounding factor 8000884: e9d7 0100 ldrd r0, r1, [r7] 8000888: a331 add r3, pc, #196 ; (adr r3, 8000950 ) 800088a: e9d3 2300 ldrd r2, r3, [r3] 800088e: f007 fff5 bl 800887c <__adddf3> 8000892: 4602 mov r2, r0 8000894: 460b mov r3, r1 8000896: e9c7 2300 strd r2, r3, [r7] long integer_part; integer_part = (int)n; 800089a: e9d7 0100 ldrd r0, r1, [r7] 800089e: f008 fc39 bl 8009114 <__aeabi_d2iz> 80008a2: 4603 mov r3, r0 80008a4: 613b str r3, [r7, #16] printIntegerInBase(integer_part,10); 80008a6: 693b ldr r3, [r7, #16] 80008a8: 4618 mov r0, r3 80008aa: f04f 010a mov.w r1, #10 80008ae: f7ff ff51 bl 8000754 serial_write('.'); 80008b2: f04f 002e mov.w r0, #46 ; 0x2e 80008b6: f004 fb67 bl 8004f88 n -= integer_part; 80008ba: 6938 ldr r0, [r7, #16] 80008bc: f008 f92a bl 8008b14 <__aeabi_i2d> 80008c0: 4602 mov r2, r0 80008c2: 460b mov r3, r1 80008c4: e9d7 0100 ldrd r0, r1, [r7] 80008c8: f007 ffd6 bl 8008878 <__aeabi_dsub> 80008cc: 4602 mov r2, r0 80008ce: 460b mov r3, r1 80008d0: e9c7 2300 strd r2, r3, [r7] int decimals = DECIMAL_PLACES; 80008d4: f04f 0303 mov.w r3, #3 80008d8: 617b str r3, [r7, #20] uint8_t decimal_part; while(decimals-- > 0) { 80008da: e025 b.n 8000928 n *= 10; 80008dc: e9d7 0100 ldrd r0, r1, [r7] 80008e0: a31d add r3, pc, #116 ; (adr r3, 8000958 ) 80008e2: e9d3 2300 ldrd r2, r3, [r3] 80008e6: f008 f97b bl 8008be0 <__aeabi_dmul> 80008ea: 4602 mov r2, r0 80008ec: 460b mov r3, r1 80008ee: e9c7 2300 strd r2, r3, [r7] decimal_part = (int) n; 80008f2: e9d7 0100 ldrd r0, r1, [r7] 80008f6: f008 fc0d bl 8009114 <__aeabi_d2iz> 80008fa: 4603 mov r3, r0 80008fc: 73fb strb r3, [r7, #15] serial_write('0'+decimal_part); 80008fe: 7bfb ldrb r3, [r7, #15] 8000900: f103 0330 add.w r3, r3, #48 ; 0x30 8000904: b2db uxtb r3, r3 8000906: 4618 mov r0, r3 8000908: f004 fb3e bl 8004f88 n -= decimal_part; 800090c: 7bfb ldrb r3, [r7, #15] 800090e: 4618 mov r0, r3 8000910: f008 f900 bl 8008b14 <__aeabi_i2d> 8000914: 4602 mov r2, r0 8000916: 460b mov r3, r1 8000918: e9d7 0100 ldrd r0, r1, [r7] 800091c: f007 ffac bl 8008878 <__aeabi_dsub> 8000920: 4602 mov r2, r0 8000922: 460b mov r3, r1 8000924: e9c7 2300 strd r2, r3, [r7] serial_write('.'); n -= integer_part; int decimals = DECIMAL_PLACES; uint8_t decimal_part; while(decimals-- > 0) { 8000928: 697b ldr r3, [r7, #20] 800092a: 2b00 cmp r3, #0 800092c: bfd4 ite le 800092e: 2300 movle r3, #0 8000930: 2301 movgt r3, #1 8000932: b2db uxtb r3, r3 8000934: 697a ldr r2, [r7, #20] 8000936: f102 32ff add.w r2, r2, #4294967295 800093a: 617a str r2, [r7, #20] 800093c: 2b00 cmp r3, #0 800093e: d1cd bne.n 80008dc n *= 10; decimal_part = (int) n; serial_write('0'+decimal_part); n -= decimal_part; } } 8000940: f107 071c add.w r7, r7, #28 8000944: 46bd mov sp, r7 8000946: bd90 pop {r4, r7, pc} ... 8000950: d2f1a9fc .word 0xd2f1a9fc 8000954: 3f40624d .word 0x3f40624d 8000958: 00000000 .word 0x00000000 800095c: 40240000 .word 0x40240000 08000960 : #define FAIL(status) gc.status_code = status; static int next_statement(char *letter, double *double_ptr, char *line, uint8_t *char_counter); static void select_plane(uint8_t axis_0, uint8_t axis_1, uint8_t axis_2) { 8000960: b480 push {r7} 8000962: b083 sub sp, #12 8000964: af00 add r7, sp, #0 8000966: 4613 mov r3, r2 8000968: 4602 mov r2, r0 800096a: 71fa strb r2, [r7, #7] 800096c: 460a mov r2, r1 800096e: 71ba strb r2, [r7, #6] 8000970: 717b strb r3, [r7, #5] gc.plane_axis_0 = axis_0; 8000972: f240 4378 movw r3, #1144 ; 0x478 8000976: f2c2 0300 movt r3, #8192 ; 0x2000 800097a: 79fa ldrb r2, [r7, #7] 800097c: f883 2034 strb.w r2, [r3, #52] ; 0x34 gc.plane_axis_1 = axis_1; 8000980: f240 4378 movw r3, #1144 ; 0x478 8000984: f2c2 0300 movt r3, #8192 ; 0x2000 8000988: 79ba ldrb r2, [r7, #6] 800098a: f883 2035 strb.w r2, [r3, #53] ; 0x35 gc.plane_axis_2 = axis_2; 800098e: f240 4378 movw r3, #1144 ; 0x478 8000992: f2c2 0300 movt r3, #8192 ; 0x2000 8000996: 797a ldrb r2, [r7, #5] 8000998: f883 2036 strb.w r2, [r3, #54] ; 0x36 } 800099c: f107 070c add.w r7, r7, #12 80009a0: 46bd mov sp, r7 80009a2: bc80 pop {r7} 80009a4: 4770 bx lr 80009a6: bf00 nop 080009a8 : void gc_init() { 80009a8: b580 push {r7, lr} 80009aa: af00 add r7, sp, #0 memset(&gc, 0, sizeof(gc)); 80009ac: f240 4378 movw r3, #1144 ; 0x478 80009b0: f2c2 0300 movt r3, #8192 ; 0x2000 80009b4: f04f 0200 mov.w r2, #0 80009b8: 601a str r2, [r3, #0] 80009ba: f103 0304 add.w r3, r3, #4 80009be: f04f 0200 mov.w r2, #0 80009c2: 601a str r2, [r3, #0] 80009c4: f103 0304 add.w r3, r3, #4 80009c8: f04f 0200 mov.w r2, #0 80009cc: 601a str r2, [r3, #0] 80009ce: f103 0304 add.w r3, r3, #4 80009d2: f04f 0200 mov.w r2, #0 80009d6: 601a str r2, [r3, #0] 80009d8: f103 0304 add.w r3, r3, #4 80009dc: f04f 0200 mov.w r2, #0 80009e0: 601a str r2, [r3, #0] 80009e2: f103 0304 add.w r3, r3, #4 80009e6: f04f 0200 mov.w r2, #0 80009ea: 601a str r2, [r3, #0] 80009ec: f103 0304 add.w r3, r3, #4 80009f0: f04f 0200 mov.w r2, #0 80009f4: 601a str r2, [r3, #0] 80009f6: f103 0304 add.w r3, r3, #4 80009fa: f04f 0200 mov.w r2, #0 80009fe: 601a str r2, [r3, #0] 8000a00: f103 0304 add.w r3, r3, #4 8000a04: f04f 0200 mov.w r2, #0 8000a08: 601a str r2, [r3, #0] 8000a0a: f103 0304 add.w r3, r3, #4 8000a0e: f04f 0200 mov.w r2, #0 8000a12: 601a str r2, [r3, #0] 8000a14: f103 0304 add.w r3, r3, #4 8000a18: f04f 0200 mov.w r2, #0 8000a1c: 601a str r2, [r3, #0] 8000a1e: f103 0304 add.w r3, r3, #4 8000a22: f04f 0200 mov.w r2, #0 8000a26: 601a str r2, [r3, #0] 8000a28: f103 0304 add.w r3, r3, #4 8000a2c: f04f 0200 mov.w r2, #0 8000a30: 601a str r2, [r3, #0] 8000a32: f103 0304 add.w r3, r3, #4 8000a36: f04f 0200 mov.w r2, #0 8000a3a: 601a str r2, [r3, #0] 8000a3c: f103 0304 add.w r3, r3, #4 gc.feed_rate = settings.default_feed_rate; 8000a40: f240 63d8 movw r3, #1752 ; 0x6d8 8000a44: f2c2 0300 movt r3, #8192 ; 0x2000 8000a48: e9d3 0108 ldrd r0, r1, [r3, #32] 8000a4c: f240 4378 movw r3, #1144 ; 0x478 8000a50: f2c2 0300 movt r3, #8192 ; 0x2000 8000a54: e9c3 0102 strd r0, r1, [r3, #8] gc.seek_rate = settings.default_seek_rate; 8000a58: f240 63d8 movw r3, #1752 ; 0x6d8 8000a5c: f2c2 0300 movt r3, #8192 ; 0x2000 8000a60: e9d3 010a ldrd r0, r1, [r3, #40] ; 0x28 8000a64: f240 4378 movw r3, #1144 ; 0x478 8000a68: f2c2 0300 movt r3, #8192 ; 0x2000 8000a6c: e9c3 0104 strd r0, r1, [r3, #16] select_plane(X_AXIS, Y_AXIS, Z_AXIS); 8000a70: f04f 0000 mov.w r0, #0 8000a74: f04f 0101 mov.w r1, #1 8000a78: f04f 0202 mov.w r2, #2 8000a7c: f7ff ff70 bl 8000960 gc.absolute_mode = true; 8000a80: f240 4378 movw r3, #1144 ; 0x478 8000a84: f2c2 0300 movt r3, #8192 ; 0x2000 8000a88: f04f 0201 mov.w r2, #1 8000a8c: 711a strb r2, [r3, #4] } 8000a8e: bd80 pop {r7, pc} 08000a90 : static float to_millimeters(double value) { 8000a90: b580 push {r7, lr} 8000a92: b082 sub sp, #8 8000a94: af00 add r7, sp, #0 8000a96: e9c7 0100 strd r0, r1, [r7] return(gc.inches_mode ? (value * MM_PER_INCH) : value); 8000a9a: f240 4378 movw r3, #1144 ; 0x478 8000a9e: f2c2 0300 movt r3, #8192 ; 0x2000 8000aa2: 78db ldrb r3, [r3, #3] 8000aa4: 2b00 cmp r3, #0 8000aa6: d009 beq.n 8000abc 8000aa8: e9d7 0100 ldrd r0, r1, [r7] 8000aac: a30a add r3, pc, #40 ; (adr r3, 8000ad8 ) 8000aae: e9d3 2300 ldrd r2, r3, [r3] 8000ab2: f008 f895 bl 8008be0 <__aeabi_dmul> 8000ab6: 4602 mov r2, r0 8000ab8: 460b mov r3, r1 8000aba: e001 b.n 8000ac0 8000abc: e9d7 2300 ldrd r2, r3, [r7] 8000ac0: 4610 mov r0, r2 8000ac2: 4619 mov r1, r3 8000ac4: f008 fb6e bl 80091a4 <__aeabi_d2f> 8000ac8: 4603 mov r3, r0 } 8000aca: 4618 mov r0, r3 8000acc: f107 0708 add.w r7, r7, #8 8000ad0: 46bd mov sp, r7 8000ad2: bd80 pop {r7, pc} 8000ad4: f3af 8000 nop.w 8000ad8: 66666666 .word 0x66666666 8000adc: 40396666 .word 0x40396666 08000ae0 : // Executes one line of 0-terminated G-Code. The line is assumed to contain only uppercase // characters and signed floating point values (no whitespace). Comments and block delete // characters have been removed. uint8_t gc_execute_line(char *line) { 8000ae0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8000ae4: b0af sub sp, #188 ; 0xbc 8000ae6: af0a add r7, sp, #40 ; 0x28 8000ae8: 6078 str r0, [r7, #4] uint8_t char_counter = 0; 8000aea: f04f 0300 mov.w r3, #0 8000aee: f887 3047 strb.w r3, [r7, #71] ; 0x47 char letter; double value; double unit_converted_value; double inverse_feed_rate = -1; // negative inverse_feed_rate means no inverse_feed_rate specified 8000af2: f60f 33c4 addw r3, pc, #3012 ; 0xbc4 8000af6: e9d3 2300 ldrd r2, r3, [r3] 8000afa: e9c7 2322 strd r2, r3, [r7, #136] ; 0x88 uint8_t radius_mode = false; 8000afe: f04f 0300 mov.w r3, #0 8000b02: f887 3087 strb.w r3, [r7, #135] ; 0x87 uint8_t absolute_override = false; /* 1 = absolute motion for this block only {G53} */ 8000b06: f04f 0300 mov.w r3, #0 8000b0a: f887 3086 strb.w r3, [r7, #134] ; 0x86 uint8_t next_action = NEXT_ACTION_DEFAULT; /* The action that will be taken by the parsed line */ 8000b0e: f04f 0300 mov.w r3, #0 8000b12: f887 3085 strb.w r3, [r7, #133] ; 0x85 double target[3], offset[3]; double p = 0, r = 0; 8000b16: f60f 33a8 addw r3, pc, #2984 ; 0xba8 8000b1a: e9d3 2300 ldrd r2, r3, [r3] 8000b1e: e9c7 231e strd r2, r3, [r7, #120] ; 0x78 8000b22: f60f 339c addw r3, pc, #2972 ; 0xb9c 8000b26: e9d3 2300 ldrd r2, r3, [r3] 8000b2a: e9c7 231c strd r2, r3, [r7, #112] ; 0x70 int int_value; gc.status_code = STATUS_OK; 8000b2e: f240 4378 movw r3, #1144 ; 0x478 8000b32: f2c2 0300 movt r3, #8192 ; 0x2000 8000b36: f04f 0200 mov.w r2, #0 8000b3a: 701a strb r2, [r3, #0] 8000b3c: e000 b.n 8000b40 } break; case 'T': gc.tool = trunc(value); break; } if(gc.status_code) { break; } } 8000b3e: bf00 nop gc.status_code = STATUS_OK; // Pass 1: Commands while(1) { if(next_statement(&letter, &value, line, &char_counter)==0) 8000b40: f107 0146 add.w r1, r7, #70 ; 0x46 8000b44: f107 0238 add.w r2, r7, #56 ; 0x38 8000b48: f107 0347 add.w r3, r7, #71 ; 0x47 8000b4c: 4608 mov r0, r1 8000b4e: 4611 mov r1, r2 8000b50: 687a ldr r2, [r7, #4] 8000b52: f000 fe51 bl 80017f8 8000b56: 4603 mov r3, r0 8000b58: 2b00 cmp r3, #0 8000b5a: f000 8240 beq.w 8000fde { break; } int_value = trunc(value); 8000b5e: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38 8000b62: 4610 mov r0, r2 8000b64: 4619 mov r1, r3 8000b66: f005 e99e blx 8005ea4 8000b6a: 4602 mov r2, r0 8000b6c: 460b mov r3, r1 8000b6e: 4610 mov r0, r2 8000b70: 4619 mov r1, r3 8000b72: f008 facf bl 8009114 <__aeabi_d2iz> 8000b76: 4603 mov r3, r0 8000b78: 663b str r3, [r7, #96] ; 0x60 switch(letter) { 8000b7a: f897 3046 ldrb.w r3, [r7, #70] ; 0x46 8000b7e: 2b4d cmp r3, #77 ; 0x4d 8000b80: f000 815c beq.w 8000e3c 8000b84: 2b54 cmp r3, #84 ; 0x54 8000b86: f000 820c beq.w 8000fa2 8000b8a: 2b47 cmp r3, #71 ; 0x47 8000b8c: f040 821e bne.w 8000fcc case 'G': switch(int_value) { 8000b90: 6e3b ldr r3, [r7, #96] ; 0x60 8000b92: 2b5e cmp r3, #94 ; 0x5e 8000b94: f200 8149 bhi.w 8000e2a 8000b98: a001 add r0, pc, #4 ; (adr r0, 8000ba0 ) 8000b9a: f850 f023 ldr.w pc, [r0, r3, lsl #2] 8000b9e: bf00 nop 8000ba0: 08000d1d .word 0x08000d1d 8000ba4: 08000d2d .word 0x08000d2d 8000ba8: 08000d3d .word 0x08000d3d 8000bac: 08000d4d .word 0x08000d4d 8000bb0: 08000d5d .word 0x08000d5d 8000bb4: 08000e2b .word 0x08000e2b 8000bb8: 08000e2b .word 0x08000e2b 8000bbc: 08000e2b .word 0x08000e2b 8000bc0: 08000e2b .word 0x08000e2b 8000bc4: 08000e2b .word 0x08000e2b 8000bc8: 08000e2b .word 0x08000e2b 8000bcc: 08000e2b .word 0x08000e2b 8000bd0: 08000e2b .word 0x08000e2b 8000bd4: 08000e2b .word 0x08000e2b 8000bd8: 08000e2b .word 0x08000e2b 8000bdc: 08000e2b .word 0x08000e2b 8000be0: 08000e2b .word 0x08000e2b 8000be4: 08000d67 .word 0x08000d67 8000be8: 08000d79 .word 0x08000d79 8000bec: 08000d8b .word 0x08000d8b 8000bf0: 08000d9d .word 0x08000d9d 8000bf4: 08000dad .word 0x08000dad 8000bf8: 08000e2b .word 0x08000e2b 8000bfc: 08000e2b .word 0x08000e2b 8000c00: 08000e2b .word 0x08000e2b 8000c04: 08000e2b .word 0x08000e2b 8000c08: 08000e2b .word 0x08000e2b 8000c0c: 08000e2b .word 0x08000e2b 8000c10: 08000dbd .word 0x08000dbd 8000c14: 08000e2b .word 0x08000e2b 8000c18: 08000dbd .word 0x08000dbd 8000c1c: 08000e2b .word 0x08000e2b 8000c20: 08000e2b .word 0x08000e2b 8000c24: 08000e2b .word 0x08000e2b 8000c28: 08000e2b .word 0x08000e2b 8000c2c: 08000e2b .word 0x08000e2b 8000c30: 08000e2b .word 0x08000e2b 8000c34: 08000e2b .word 0x08000e2b 8000c38: 08000e2b .word 0x08000e2b 8000c3c: 08000e2b .word 0x08000e2b 8000c40: 08000e2b .word 0x08000e2b 8000c44: 08000e2b .word 0x08000e2b 8000c48: 08000e2b .word 0x08000e2b 8000c4c: 08000e2b .word 0x08000e2b 8000c50: 08000e2b .word 0x08000e2b 8000c54: 08000e2b .word 0x08000e2b 8000c58: 08000e2b .word 0x08000e2b 8000c5c: 08000e2b .word 0x08000e2b 8000c60: 08000e2b .word 0x08000e2b 8000c64: 08000e2b .word 0x08000e2b 8000c68: 08000e2b .word 0x08000e2b 8000c6c: 08000e2b .word 0x08000e2b 8000c70: 08000e2b .word 0x08000e2b 8000c74: 08000dc7 .word 0x08000dc7 8000c78: 08000e2b .word 0x08000e2b 8000c7c: 08000e2b .word 0x08000e2b 8000c80: 08000e2b .word 0x08000e2b 8000c84: 08000e2b .word 0x08000e2b 8000c88: 08000e2b .word 0x08000e2b 8000c8c: 08000e2b .word 0x08000e2b 8000c90: 08000e2b .word 0x08000e2b 8000c94: 08000e2b .word 0x08000e2b 8000c98: 08000e2b .word 0x08000e2b 8000c9c: 08000e2b .word 0x08000e2b 8000ca0: 08000e2b .word 0x08000e2b 8000ca4: 08000e2b .word 0x08000e2b 8000ca8: 08000e2b .word 0x08000e2b 8000cac: 08000e2b .word 0x08000e2b 8000cb0: 08000e2b .word 0x08000e2b 8000cb4: 08000e2b .word 0x08000e2b 8000cb8: 08000e2b .word 0x08000e2b 8000cbc: 08000e2b .word 0x08000e2b 8000cc0: 08000e2b .word 0x08000e2b 8000cc4: 08000e2b .word 0x08000e2b 8000cc8: 08000e2b .word 0x08000e2b 8000ccc: 08000e2b .word 0x08000e2b 8000cd0: 08000e2b .word 0x08000e2b 8000cd4: 08000e2b .word 0x08000e2b 8000cd8: 08000e2b .word 0x08000e2b 8000cdc: 08000e2b .word 0x08000e2b 8000ce0: 08000dd1 .word 0x08000dd1 8000ce4: 08000e2b .word 0x08000e2b 8000ce8: 08000e2b .word 0x08000e2b 8000cec: 08000e2b .word 0x08000e2b 8000cf0: 08000e2b .word 0x08000e2b 8000cf4: 08000e2b .word 0x08000e2b 8000cf8: 08000e2b .word 0x08000e2b 8000cfc: 08000e2b .word 0x08000e2b 8000d00: 08000e2b .word 0x08000e2b 8000d04: 08000e2b .word 0x08000e2b 8000d08: 08000de1 .word 0x08000de1 8000d0c: 08000df1 .word 0x08000df1 8000d10: 08000e01 .word 0x08000e01 8000d14: 08000e0b .word 0x08000e0b 8000d18: 08000e1b .word 0x08000e1b case 0: gc.motion_mode = MOTION_MODE_SEEK; break; 8000d1c: f240 4378 movw r3, #1144 ; 0x478 8000d20: f2c2 0300 movt r3, #8192 ; 0x2000 8000d24: f04f 0200 mov.w r2, #0 8000d28: 705a strb r2, [r3, #1] 8000d2a: e086 b.n 8000e3a case 1: gc.motion_mode = MOTION_MODE_LINEAR; break; 8000d2c: f240 4378 movw r3, #1144 ; 0x478 8000d30: f2c2 0300 movt r3, #8192 ; 0x2000 8000d34: f04f 0201 mov.w r2, #1 8000d38: 705a strb r2, [r3, #1] 8000d3a: e07e b.n 8000e3a case 2: gc.motion_mode = MOTION_MODE_CW_ARC; break; 8000d3c: f240 4378 movw r3, #1144 ; 0x478 8000d40: f2c2 0300 movt r3, #8192 ; 0x2000 8000d44: f04f 0202 mov.w r2, #2 8000d48: 705a strb r2, [r3, #1] 8000d4a: e076 b.n 8000e3a case 3: gc.motion_mode = MOTION_MODE_CCW_ARC; break; 8000d4c: f240 4378 movw r3, #1144 ; 0x478 8000d50: f2c2 0300 movt r3, #8192 ; 0x2000 8000d54: f04f 0203 mov.w r2, #3 8000d58: 705a strb r2, [r3, #1] 8000d5a: e06e b.n 8000e3a case 4: next_action = NEXT_ACTION_DWELL; break; 8000d5c: f04f 0301 mov.w r3, #1 8000d60: f887 3085 strb.w r3, [r7, #133] ; 0x85 8000d64: e069 b.n 8000e3a case 17: select_plane(X_AXIS, Y_AXIS, Z_AXIS); break; 8000d66: f04f 0000 mov.w r0, #0 8000d6a: f04f 0101 mov.w r1, #1 8000d6e: f04f 0202 mov.w r2, #2 8000d72: f7ff fdf5 bl 8000960 8000d76: e060 b.n 8000e3a case 18: select_plane(X_AXIS, Z_AXIS, Y_AXIS); break; 8000d78: f04f 0000 mov.w r0, #0 8000d7c: f04f 0102 mov.w r1, #2 8000d80: f04f 0201 mov.w r2, #1 8000d84: f7ff fdec bl 8000960 8000d88: e057 b.n 8000e3a case 19: select_plane(Y_AXIS, Z_AXIS, X_AXIS); break; 8000d8a: f04f 0001 mov.w r0, #1 8000d8e: f04f 0102 mov.w r1, #2 8000d92: f04f 0200 mov.w r2, #0 8000d96: f7ff fde3 bl 8000960 8000d9a: e04e b.n 8000e3a case 20: gc.inches_mode = true; break; 8000d9c: f240 4378 movw r3, #1144 ; 0x478 8000da0: f2c2 0300 movt r3, #8192 ; 0x2000 8000da4: f04f 0201 mov.w r2, #1 8000da8: 70da strb r2, [r3, #3] 8000daa: e046 b.n 8000e3a case 21: gc.inches_mode = false; break; 8000dac: f240 4378 movw r3, #1144 ; 0x478 8000db0: f2c2 0300 movt r3, #8192 ; 0x2000 8000db4: f04f 0200 mov.w r2, #0 8000db8: 70da strb r2, [r3, #3] 8000dba: e03e b.n 8000e3a case 28: case 30: next_action = NEXT_ACTION_GO_HOME; break; 8000dbc: f04f 0302 mov.w r3, #2 8000dc0: f887 3085 strb.w r3, [r7, #133] ; 0x85 8000dc4: e039 b.n 8000e3a case 53: absolute_override = true; break; 8000dc6: f04f 0301 mov.w r3, #1 8000dca: f887 3086 strb.w r3, [r7, #134] ; 0x86 8000dce: e034 b.n 8000e3a case 80: gc.motion_mode = MOTION_MODE_CANCEL; break; 8000dd0: f240 4378 movw r3, #1144 ; 0x478 8000dd4: f2c2 0300 movt r3, #8192 ; 0x2000 8000dd8: f04f 0204 mov.w r2, #4 8000ddc: 705a strb r2, [r3, #1] 8000dde: e02c b.n 8000e3a case 90: gc.absolute_mode = true; break; 8000de0: f240 4378 movw r3, #1144 ; 0x478 8000de4: f2c2 0300 movt r3, #8192 ; 0x2000 8000de8: f04f 0201 mov.w r2, #1 8000dec: 711a strb r2, [r3, #4] 8000dee: e024 b.n 8000e3a case 91: gc.absolute_mode = false; break; 8000df0: f240 4378 movw r3, #1144 ; 0x478 8000df4: f2c2 0300 movt r3, #8192 ; 0x2000 8000df8: f04f 0200 mov.w r2, #0 8000dfc: 711a strb r2, [r3, #4] 8000dfe: e01c b.n 8000e3a case 92: next_action = NEXT_ACTION_SET_COORDINATE_OFFSET; break; 8000e00: f04f 0303 mov.w r3, #3 8000e04: f887 3085 strb.w r3, [r7, #133] ; 0x85 8000e08: e017 b.n 8000e3a case 93: gc.inverse_feed_rate_mode = true; break; 8000e0a: f240 4378 movw r3, #1144 ; 0x478 8000e0e: f2c2 0300 movt r3, #8192 ; 0x2000 8000e12: f04f 0201 mov.w r2, #1 8000e16: 709a strb r2, [r3, #2] 8000e18: e00f b.n 8000e3a case 94: gc.inverse_feed_rate_mode = false; break; 8000e1a: f240 4378 movw r3, #1144 ; 0x478 8000e1e: f2c2 0300 movt r3, #8192 ; 0x2000 8000e22: f04f 0200 mov.w r2, #0 8000e26: 709a strb r2, [r3, #2] 8000e28: e007 b.n 8000e3a default: FAIL(STATUS_UNSUPPORTED_STATEMENT); 8000e2a: f240 4378 movw r3, #1144 ; 0x478 8000e2e: f2c2 0300 movt r3, #8192 ; 0x2000 8000e32: f04f 0203 mov.w r2, #3 8000e36: 701a strb r2, [r3, #0] } break; 8000e38: e0c8 b.n 8000fcc 8000e3a: e0c7 b.n 8000fcc case 'M': switch(int_value) { 8000e3c: 6e3b ldr r3, [r7, #96] ; 0x60 8000e3e: 2b3c cmp r3, #60 ; 0x3c 8000e40: f200 80a6 bhi.w 8000f90 8000e44: a201 add r2, pc, #4 ; (adr r2, 8000e4c ) 8000e46: f852 f023 ldr.w pc, [r2, r3, lsl #2] 8000e4a: bf00 nop 8000e4c: 08000f41 .word 0x08000f41 8000e50: 08000f41 .word 0x08000f41 8000e54: 08000f51 .word 0x08000f51 8000e58: 08000f61 .word 0x08000f61 8000e5c: 08000f71 .word 0x08000f71 8000e60: 08000f81 .word 0x08000f81 8000e64: 08000f91 .word 0x08000f91 8000e68: 08000f91 .word 0x08000f91 8000e6c: 08000f91 .word 0x08000f91 8000e70: 08000f91 .word 0x08000f91 8000e74: 08000f91 .word 0x08000f91 8000e78: 08000f91 .word 0x08000f91 8000e7c: 08000f91 .word 0x08000f91 8000e80: 08000f91 .word 0x08000f91 8000e84: 08000f91 .word 0x08000f91 8000e88: 08000f91 .word 0x08000f91 8000e8c: 08000f91 .word 0x08000f91 8000e90: 08000f91 .word 0x08000f91 8000e94: 08000f91 .word 0x08000f91 8000e98: 08000f91 .word 0x08000f91 8000e9c: 08000f91 .word 0x08000f91 8000ea0: 08000f91 .word 0x08000f91 8000ea4: 08000f91 .word 0x08000f91 8000ea8: 08000f91 .word 0x08000f91 8000eac: 08000f91 .word 0x08000f91 8000eb0: 08000f91 .word 0x08000f91 8000eb4: 08000f91 .word 0x08000f91 8000eb8: 08000f91 .word 0x08000f91 8000ebc: 08000f91 .word 0x08000f91 8000ec0: 08000f91 .word 0x08000f91 8000ec4: 08000f51 .word 0x08000f51 8000ec8: 08000f91 .word 0x08000f91 8000ecc: 08000f91 .word 0x08000f91 8000ed0: 08000f91 .word 0x08000f91 8000ed4: 08000f91 .word 0x08000f91 8000ed8: 08000f91 .word 0x08000f91 8000edc: 08000f91 .word 0x08000f91 8000ee0: 08000f91 .word 0x08000f91 8000ee4: 08000f91 .word 0x08000f91 8000ee8: 08000f91 .word 0x08000f91 8000eec: 08000f91 .word 0x08000f91 8000ef0: 08000f91 .word 0x08000f91 8000ef4: 08000f91 .word 0x08000f91 8000ef8: 08000f91 .word 0x08000f91 8000efc: 08000f91 .word 0x08000f91 8000f00: 08000f91 .word 0x08000f91 8000f04: 08000f91 .word 0x08000f91 8000f08: 08000f91 .word 0x08000f91 8000f0c: 08000f91 .word 0x08000f91 8000f10: 08000f91 .word 0x08000f91 8000f14: 08000f91 .word 0x08000f91 8000f18: 08000f91 .word 0x08000f91 8000f1c: 08000f91 .word 0x08000f91 8000f20: 08000f91 .word 0x08000f91 8000f24: 08000f91 .word 0x08000f91 8000f28: 08000f91 .word 0x08000f91 8000f2c: 08000f91 .word 0x08000f91 8000f30: 08000f91 .word 0x08000f91 8000f34: 08000f91 .word 0x08000f91 8000f38: 08000f91 .word 0x08000f91 8000f3c: 08000f51 .word 0x08000f51 case 0: case 1: gc.program_flow = PROGRAM_FLOW_PAUSED; break; 8000f40: f240 4378 movw r3, #1144 ; 0x478 8000f44: f2c2 0300 movt r3, #8192 ; 0x2000 8000f48: f04f 0201 mov.w r2, #1 8000f4c: 715a strb r2, [r3, #5] 8000f4e: e027 b.n 8000fa0 case 2: case 30: case 60: gc.program_flow = PROGRAM_FLOW_COMPLETED; break; 8000f50: f240 4378 movw r3, #1144 ; 0x478 8000f54: f2c2 0300 movt r3, #8192 ; 0x2000 8000f58: f04f 0202 mov.w r2, #2 8000f5c: 715a strb r2, [r3, #5] 8000f5e: e01f b.n 8000fa0 case 3: gc.spindle_direction = 1; break; 8000f60: f240 4378 movw r3, #1144 ; 0x478 8000f64: f2c2 0300 movt r3, #8192 ; 0x2000 8000f68: f04f 0201 mov.w r2, #1 8000f6c: 719a strb r2, [r3, #6] 8000f6e: e017 b.n 8000fa0 case 4: gc.spindle_direction = -1; break; 8000f70: f240 4378 movw r3, #1144 ; 0x478 8000f74: f2c2 0300 movt r3, #8192 ; 0x2000 8000f78: f04f 02ff mov.w r2, #255 ; 0xff 8000f7c: 719a strb r2, [r3, #6] 8000f7e: e00f b.n 8000fa0 case 5: gc.spindle_direction = 0; break; 8000f80: f240 4378 movw r3, #1144 ; 0x478 8000f84: f2c2 0300 movt r3, #8192 ; 0x2000 8000f88: f04f 0200 mov.w r2, #0 8000f8c: 719a strb r2, [r3, #6] 8000f8e: e007 b.n 8000fa0 default: FAIL(STATUS_UNSUPPORTED_STATEMENT); 8000f90: f240 4378 movw r3, #1144 ; 0x478 8000f94: f2c2 0300 movt r3, #8192 ; 0x2000 8000f98: f04f 0203 mov.w r2, #3 8000f9c: 701a strb r2, [r3, #0] } break; 8000f9e: e015 b.n 8000fcc 8000fa0: e014 b.n 8000fcc case 'T': gc.tool = trunc(value); break; 8000fa2: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38 8000fa6: 4610 mov r0, r2 8000fa8: 4619 mov r1, r3 8000faa: f004 ef7c blx 8005ea4 8000fae: 4602 mov r2, r0 8000fb0: 460b mov r3, r1 8000fb2: 4610 mov r0, r2 8000fb4: 4619 mov r1, r3 8000fb6: f008 f8d5 bl 8009164 <__aeabi_d2uiz> 8000fba: 4603 mov r3, r0 8000fbc: b2da uxtb r2, r3 8000fbe: f240 4378 movw r3, #1144 ; 0x478 8000fc2: f2c2 0300 movt r3, #8192 ; 0x2000 8000fc6: f883 2030 strb.w r2, [r3, #48] ; 0x30 8000fca: bf00 nop } if(gc.status_code) { break; } 8000fcc: f240 4378 movw r3, #1144 ; 0x478 8000fd0: f2c2 0300 movt r3, #8192 ; 0x2000 8000fd4: 781b ldrb r3, [r3, #0] 8000fd6: 2b00 cmp r3, #0 8000fd8: f43f adb1 beq.w 8000b3e 8000fdc: e000 b.n 8000fe0 // Pass 1: Commands while(1) { if(next_statement(&letter, &value, line, &char_counter)==0) { break; 8000fde: bf00 nop } if(gc.status_code) { break; } } // If there were any errors parsing this line, we will return right away with the bad news if (gc.status_code) { return(gc.status_code); } 8000fe0: f240 4378 movw r3, #1144 ; 0x478 8000fe4: f2c2 0300 movt r3, #8192 ; 0x2000 8000fe8: 781b ldrb r3, [r3, #0] 8000fea: 2b00 cmp r3, #0 8000fec: d005 beq.n 8000ffa 8000fee: f240 4378 movw r3, #1144 ; 0x478 8000ff2: f2c2 0300 movt r3, #8192 ; 0x2000 8000ff6: 781b ldrb r3, [r3, #0] 8000ff8: e3f3 b.n 80017e2 char_counter = 0; 8000ffa: f04f 0300 mov.w r3, #0 8000ffe: f887 3047 strb.w r3, [r7, #71] ; 0x47 clear_vector(target); 8001002: f107 0320 add.w r3, r7, #32 8001006: f04f 0200 mov.w r2, #0 800100a: 601a str r2, [r3, #0] 800100c: f103 0304 add.w r3, r3, #4 8001010: f04f 0200 mov.w r2, #0 8001014: 601a str r2, [r3, #0] 8001016: f103 0304 add.w r3, r3, #4 800101a: f04f 0200 mov.w r2, #0 800101e: 601a str r2, [r3, #0] 8001020: f103 0304 add.w r3, r3, #4 8001024: f04f 0200 mov.w r2, #0 8001028: 601a str r2, [r3, #0] 800102a: f103 0304 add.w r3, r3, #4 800102e: f04f 0200 mov.w r2, #0 8001032: 601a str r2, [r3, #0] 8001034: f103 0304 add.w r3, r3, #4 8001038: f04f 0200 mov.w r2, #0 800103c: 601a str r2, [r3, #0] 800103e: f103 0304 add.w r3, r3, #4 clear_vector(offset); 8001042: f107 0308 add.w r3, r7, #8 8001046: f04f 0200 mov.w r2, #0 800104a: 601a str r2, [r3, #0] 800104c: f103 0304 add.w r3, r3, #4 8001050: f04f 0200 mov.w r2, #0 8001054: 601a str r2, [r3, #0] 8001056: f103 0304 add.w r3, r3, #4 800105a: f04f 0200 mov.w r2, #0 800105e: 601a str r2, [r3, #0] 8001060: f103 0304 add.w r3, r3, #4 8001064: f04f 0200 mov.w r2, #0 8001068: 601a str r2, [r3, #0] 800106a: f103 0304 add.w r3, r3, #4 800106e: f04f 0200 mov.w r2, #0 8001072: 601a str r2, [r3, #0] 8001074: f103 0304 add.w r3, r3, #4 8001078: f04f 0200 mov.w r2, #0 800107c: 601a str r2, [r3, #0] 800107e: f103 0304 add.w r3, r3, #4 memcpy(target, gc.position, sizeof(target)); // i.e. target = gc.position 8001082: f240 4378 movw r3, #1144 ; 0x478 8001086: f2c2 0300 movt r3, #8192 ; 0x2000 800108a: f107 0420 add.w r4, r7, #32 800108e: f103 0518 add.w r5, r3, #24 8001092: cd0f ldmia r5!, {r0, r1, r2, r3} 8001094: c40f stmia r4!, {r0, r1, r2, r3} 8001096: e895 0003 ldmia.w r5, {r0, r1} 800109a: e884 0003 stmia.w r4, {r0, r1} // Pass 2: Parameters while(next_statement(&letter, &value, line, &char_counter)) { 800109e: e0f9 b.n 8001294 int_value = trunc(value); 80010a0: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38 80010a4: 4610 mov r0, r2 80010a6: 4619 mov r1, r3 80010a8: f004 eefc blx 8005ea4 80010ac: 4602 mov r2, r0 80010ae: 460b mov r3, r1 80010b0: 4610 mov r0, r2 80010b2: 4619 mov r1, r3 80010b4: f008 f82e bl 8009114 <__aeabi_d2iz> 80010b8: 4603 mov r3, r0 80010ba: 663b str r3, [r7, #96] ; 0x60 unit_converted_value = to_millimeters(value); 80010bc: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38 80010c0: 4610 mov r0, r2 80010c2: 4619 mov r1, r3 80010c4: f7ff fce4 bl 8000a90 80010c8: 4603 mov r3, r0 80010ca: 4618 mov r0, r3 80010cc: f007 fd34 bl 8008b38 <__aeabi_f2d> 80010d0: 4602 mov r2, r0 80010d2: 460b mov r3, r1 80010d4: e9c7 2316 strd r2, r3, [r7, #88] ; 0x58 switch(letter) { 80010d8: f897 3046 ldrb.w r3, [r7, #70] ; 0x46 80010dc: f1a3 0346 sub.w r3, r3, #70 ; 0x46 80010e0: 2b14 cmp r3, #20 80010e2: f200 80d7 bhi.w 8001294 80010e6: a001 add r0, pc, #4 ; (adr r0, 80010ec ) 80010e8: f850 f023 ldr.w pc, [r0, r3, lsl #2] 80010ec: 08001141 .word 0x08001141 80010f0: 08001295 .word 0x08001295 80010f4: 08001295 .word 0x08001295 80010f8: 080011c1 .word 0x080011c1 80010fc: 080011c1 .word 0x080011c1 8001100: 080011c1 .word 0x080011c1 8001104: 08001295 .word 0x08001295 8001108: 08001295 .word 0x08001295 800110c: 08001295 .word 0x08001295 8001110: 08001295 .word 0x08001295 8001114: 080011e1 .word 0x080011e1 8001118: 08001295 .word 0x08001295 800111c: 080011eb .word 0x080011eb 8001120: 080011fd .word 0x080011fd 8001124: 08001295 .word 0x08001295 8001128: 08001295 .word 0x08001295 800112c: 08001295 .word 0x08001295 8001130: 08001295 .word 0x08001295 8001134: 08001219 .word 0x08001219 8001138: 08001219 .word 0x08001219 800113c: 08001219 .word 0x08001219 case 'F': if (unit_converted_value <= 0) { FAIL(STATUS_BAD_NUMBER_FORMAT); } // Must be greater than zero 8001140: f04f 0301 mov.w r3, #1 8001144: 461c mov r4, r3 8001146: e9d7 0116 ldrd r0, r1, [r7, #88] ; 0x58 800114a: f20f 5374 addw r3, pc, #1396 ; 0x574 800114e: e9d3 2300 ldrd r2, r3, [r3] 8001152: f007 ffc1 bl 80090d8 <__aeabi_dcmple> 8001156: 4603 mov r3, r0 8001158: 2b00 cmp r3, #0 800115a: d102 bne.n 8001162 800115c: f04f 0300 mov.w r3, #0 8001160: 461c mov r4, r3 8001162: b2e3 uxtb r3, r4 8001164: 2b00 cmp r3, #0 8001166: d006 beq.n 8001176 8001168: f240 4378 movw r3, #1144 ; 0x478 800116c: f2c2 0300 movt r3, #8192 ; 0x2000 8001170: f04f 0201 mov.w r2, #1 8001174: 701a strb r2, [r3, #0] if (gc.inverse_feed_rate_mode) { 8001176: f240 4378 movw r3, #1144 ; 0x478 800117a: f2c2 0300 movt r3, #8192 ; 0x2000 800117e: 789b ldrb r3, [r3, #2] 8001180: 2b00 cmp r3, #0 8001182: d004 beq.n 800118e inverse_feed_rate = unit_converted_value; // seconds per motion for this motion only 8001184: e9d7 2316 ldrd r2, r3, [r7, #88] ; 0x58 8001188: e9c7 2322 strd r2, r3, [r7, #136] ; 0x88 gc.seek_rate = unit_converted_value; } else { gc.feed_rate = unit_converted_value; // millimeters per minute } } break; 800118c: e082 b.n 8001294 case 'F': if (unit_converted_value <= 0) { FAIL(STATUS_BAD_NUMBER_FORMAT); } // Must be greater than zero if (gc.inverse_feed_rate_mode) { inverse_feed_rate = unit_converted_value; // seconds per motion for this motion only } else { if (gc.motion_mode == MOTION_MODE_SEEK) { 800118e: f240 4378 movw r3, #1144 ; 0x478 8001192: f2c2 0300 movt r3, #8192 ; 0x2000 8001196: 785b ldrb r3, [r3, #1] 8001198: 2b00 cmp r3, #0 800119a: d108 bne.n 80011ae gc.seek_rate = unit_converted_value; 800119c: f240 4378 movw r3, #1144 ; 0x478 80011a0: f2c2 0300 movt r3, #8192 ; 0x2000 80011a4: e9d7 0116 ldrd r0, r1, [r7, #88] ; 0x58 80011a8: e9c3 0104 strd r0, r1, [r3, #16] } else { gc.feed_rate = unit_converted_value; // millimeters per minute } } break; 80011ac: e072 b.n 8001294 inverse_feed_rate = unit_converted_value; // seconds per motion for this motion only } else { if (gc.motion_mode == MOTION_MODE_SEEK) { gc.seek_rate = unit_converted_value; } else { gc.feed_rate = unit_converted_value; // millimeters per minute 80011ae: f240 4378 movw r3, #1144 ; 0x478 80011b2: f2c2 0300 movt r3, #8192 ; 0x2000 80011b6: e9d7 0116 ldrd r0, r1, [r7, #88] ; 0x58 80011ba: e9c3 0102 strd r0, r1, [r3, #8] } } break; 80011be: e069 b.n 8001294 case 'I': case 'J': case 'K': offset[letter-'I'] = unit_converted_value; break; 80011c0: f897 3046 ldrb.w r3, [r7, #70] ; 0x46 80011c4: f1a3 0349 sub.w r3, r3, #73 ; 0x49 80011c8: ea4f 03c3 mov.w r3, r3, lsl #3 80011cc: f107 0290 add.w r2, r7, #144 ; 0x90 80011d0: 18d3 adds r3, r2, r3 80011d2: f1a3 0188 sub.w r1, r3, #136 ; 0x88 80011d6: e9d7 2316 ldrd r2, r3, [r7, #88] ; 0x58 80011da: e9c1 2300 strd r2, r3, [r1] 80011de: e059 b.n 8001294 case 'P': p = value; break; 80011e0: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38 80011e4: e9c7 231e strd r2, r3, [r7, #120] ; 0x78 80011e8: e054 b.n 8001294 case 'R': r = unit_converted_value; radius_mode = true; break; 80011ea: e9d7 2316 ldrd r2, r3, [r7, #88] ; 0x58 80011ee: e9c7 231c strd r2, r3, [r7, #112] ; 0x70 80011f2: f04f 0301 mov.w r3, #1 80011f6: f887 3087 strb.w r3, [r7, #135] ; 0x87 80011fa: e04b b.n 8001294 case 'S': gc.spindle_speed = value; break; 80011fc: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38 8001200: 4610 mov r0, r2 8001202: 4619 mov r1, r3 8001204: f007 ff86 bl 8009114 <__aeabi_d2iz> 8001208: 4603 mov r3, r0 800120a: b29a uxth r2, r3 800120c: f240 4378 movw r3, #1144 ; 0x478 8001210: f2c2 0300 movt r3, #8192 ; 0x2000 8001214: 865a strh r2, [r3, #50] ; 0x32 8001216: e03d b.n 8001294 case 'X': case 'Y': case 'Z': if (gc.absolute_mode || absolute_override) { 8001218: f240 4378 movw r3, #1144 ; 0x478 800121c: f2c2 0300 movt r3, #8192 ; 0x2000 8001220: 791b ldrb r3, [r3, #4] 8001222: 2b00 cmp r3, #0 8001224: d103 bne.n 800122e 8001226: f897 3086 ldrb.w r3, [r7, #134] ; 0x86 800122a: 2b00 cmp r3, #0 800122c: d00f beq.n 800124e target[letter - 'X'] = unit_converted_value; 800122e: f897 3046 ldrb.w r3, [r7, #70] ; 0x46 8001232: f1a3 0358 sub.w r3, r3, #88 ; 0x58 8001236: ea4f 03c3 mov.w r3, r3, lsl #3 800123a: f107 0090 add.w r0, r7, #144 ; 0x90 800123e: 18c3 adds r3, r0, r3 8001240: f1a3 0170 sub.w r1, r3, #112 ; 0x70 8001244: e9d7 2316 ldrd r2, r3, [r7, #88] ; 0x58 8001248: e9c1 2300 strd r2, r3, [r1] } else { target[letter - 'X'] += unit_converted_value; } break; 800124c: e021 b.n 8001292 case 'S': gc.spindle_speed = value; break; case 'X': case 'Y': case 'Z': if (gc.absolute_mode || absolute_override) { target[letter - 'X'] = unit_converted_value; } else { target[letter - 'X'] += unit_converted_value; 800124e: f897 3046 ldrb.w r3, [r7, #70] ; 0x46 8001252: f1a3 0458 sub.w r4, r3, #88 ; 0x58 8001256: f897 3046 ldrb.w r3, [r7, #70] ; 0x46 800125a: f1a3 0358 sub.w r3, r3, #88 ; 0x58 800125e: ea4f 03c3 mov.w r3, r3, lsl #3 8001262: f107 0290 add.w r2, r7, #144 ; 0x90 8001266: 18d3 adds r3, r2, r3 8001268: f1a3 0370 sub.w r3, r3, #112 ; 0x70 800126c: e9d3 2300 ldrd r2, r3, [r3] 8001270: 4610 mov r0, r2 8001272: 4619 mov r1, r3 8001274: e9d7 2316 ldrd r2, r3, [r7, #88] ; 0x58 8001278: f007 fb00 bl 800887c <__adddf3> 800127c: 4602 mov r2, r0 800127e: 460b mov r3, r1 8001280: ea4f 01c4 mov.w r1, r4, lsl #3 8001284: f107 0090 add.w r0, r7, #144 ; 0x90 8001288: 1841 adds r1, r0, r1 800128a: f1a1 0170 sub.w r1, r1, #112 ; 0x70 800128e: e9c1 2300 strd r2, r3, [r1] } break; 8001292: bf00 nop clear_vector(target); clear_vector(offset); memcpy(target, gc.position, sizeof(target)); // i.e. target = gc.position // Pass 2: Parameters while(next_statement(&letter, &value, line, &char_counter)) { 8001294: f107 0146 add.w r1, r7, #70 ; 0x46 8001298: f107 0238 add.w r2, r7, #56 ; 0x38 800129c: f107 0347 add.w r3, r7, #71 ; 0x47 80012a0: 4608 mov r0, r1 80012a2: 4611 mov r1, r2 80012a4: 687a ldr r2, [r7, #4] 80012a6: f000 faa7 bl 80017f8 80012aa: 4603 mov r3, r0 80012ac: 2b00 cmp r3, #0 80012ae: f47f aef7 bne.w 80010a0 break; } } // If there were any errors parsing this line, we will return right away with the bad news if (gc.status_code) { return(gc.status_code); } 80012b2: f240 4378 movw r3, #1144 ; 0x478 80012b6: f2c2 0300 movt r3, #8192 ; 0x2000 80012ba: 781b ldrb r3, [r3, #0] 80012bc: 2b00 cmp r3, #0 80012be: d005 beq.n 80012cc 80012c0: f240 4378 movw r3, #1144 ; 0x478 80012c4: f2c2 0300 movt r3, #8192 ; 0x2000 80012c8: 781b ldrb r3, [r3, #0] 80012ca: e28a b.n 80017e2 // Update spindle state spindle_run(gc.spindle_direction, gc.spindle_speed); 80012cc: f240 4378 movw r3, #1144 ; 0x478 80012d0: f2c2 0300 movt r3, #8192 ; 0x2000 80012d4: 799a ldrb r2, [r3, #6] 80012d6: f240 4378 movw r3, #1144 ; 0x478 80012da: f2c2 0300 movt r3, #8192 ; 0x2000 80012de: 8e5b ldrh r3, [r3, #50] ; 0x32 80012e0: b21b sxth r3, r3 80012e2: b252 sxtb r2, r2 80012e4: 4610 mov r0, r2 80012e6: 4619 mov r1, r3 80012e8: f003 ffd0 bl 800528c // Perform any physical actions switch (next_action) { 80012ec: f897 3085 ldrb.w r3, [r7, #133] ; 0x85 80012f0: 2b03 cmp r3, #3 80012f2: f200 8262 bhi.w 80017ba 80012f6: a201 add r2, pc, #4 ; (adr r2, 80012fc ) 80012f8: f852 f023 ldr.w pc, [r2, r3, lsl #2] 80012fc: 08001373 .word 0x08001373 8001300: 08001353 .word 0x08001353 8001304: 0800130d .word 0x0800130d 8001308: 0800135d .word 0x0800135d case NEXT_ACTION_GO_HOME: mc_go_home(); clear_vector(target); break; 800130c: f002 f82c bl 8003368 8001310: f107 0320 add.w r3, r7, #32 8001314: f04f 0200 mov.w r2, #0 8001318: 601a str r2, [r3, #0] 800131a: f103 0304 add.w r3, r3, #4 800131e: f04f 0200 mov.w r2, #0 8001322: 601a str r2, [r3, #0] 8001324: f103 0304 add.w r3, r3, #4 8001328: f04f 0200 mov.w r2, #0 800132c: 601a str r2, [r3, #0] 800132e: f103 0304 add.w r3, r3, #4 8001332: f04f 0200 mov.w r2, #0 8001336: 601a str r2, [r3, #0] 8001338: f103 0304 add.w r3, r3, #4 800133c: f04f 0200 mov.w r2, #0 8001340: 601a str r2, [r3, #0] 8001342: f103 0304 add.w r3, r3, #4 8001346: f04f 0200 mov.w r2, #0 800134a: 601a str r2, [r3, #0] 800134c: f103 0304 add.w r3, r3, #4 8001350: e233 b.n 80017ba case NEXT_ACTION_DWELL: mc_dwell(p); break; 8001352: e9d7 011e ldrd r0, r1, [r7, #120] ; 0x78 8001356: f001 fccb bl 8002cf0 800135a: e22e b.n 80017ba case NEXT_ACTION_SET_COORDINATE_OFFSET: mc_set_current_position(target[X_AXIS], target[Y_AXIS], target[Z_AXIS]); 800135c: e9d7 0108 ldrd r0, r1, [r7, #32] 8001360: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28 8001364: e9d7 450c ldrd r4, r5, [r7, #48] ; 0x30 8001368: e9cd 4500 strd r4, r5, [sp] 800136c: f003 fbf4 bl 8004b58 break; 8001370: e223 b.n 80017ba case NEXT_ACTION_DEFAULT: switch (gc.motion_mode) { 8001372: f240 4378 movw r3, #1144 ; 0x478 8001376: f2c2 0300 movt r3, #8192 ; 0x2000 800137a: 785b ldrb r3, [r3, #1] 800137c: 2b04 cmp r3, #4 800137e: f200 821c bhi.w 80017ba 8001382: a001 add r0, pc, #4 ; (adr r0, 8001388 ) 8001384: f850 f023 ldr.w pc, [r0, r3, lsl #2] 8001388: 0800139d .word 0x0800139d 800138c: 080013cd .word 0x080013cd 8001390: 0800141b .word 0x0800141b 8001394: 0800141b .word 0x0800141b 8001398: 080017bb .word 0x080017bb case MOTION_MODE_CANCEL: break; case MOTION_MODE_SEEK: mc_line(target[X_AXIS], target[Y_AXIS], target[Z_AXIS], gc.seek_rate, false); 800139c: e9d7 0108 ldrd r0, r1, [r7, #32] 80013a0: e9d7 450a ldrd r4, r5, [r7, #40] ; 0x28 80013a4: e9d7 890c ldrd r8, r9, [r7, #48] ; 0x30 80013a8: f240 4378 movw r3, #1144 ; 0x478 80013ac: f2c2 0300 movt r3, #8192 ; 0x2000 80013b0: e9d3 2304 ldrd r2, r3, [r3, #16] 80013b4: e9cd 8900 strd r8, r9, [sp] 80013b8: e9cd 2302 strd r2, r3, [sp, #8] 80013bc: f04f 0300 mov.w r3, #0 80013c0: 9304 str r3, [sp, #16] 80013c2: 4622 mov r2, r4 80013c4: 462b mov r3, r5 80013c6: f002 ffe7 bl 8004398 break; 80013ca: e1f6 b.n 80017ba case MOTION_MODE_LINEAR: mc_line(target[X_AXIS], target[Y_AXIS], target[Z_AXIS], 80013cc: e9d7 8908 ldrd r8, r9, [r7, #32] 80013d0: e9d7 450a ldrd r4, r5, [r7, #40] ; 0x28 80013d4: e9d7 ab0c ldrd sl, fp, [r7, #48] ; 0x30 80013d8: f240 4378 movw r3, #1144 ; 0x478 80013dc: f2c2 0300 movt r3, #8192 ; 0x2000 80013e0: 789b ldrb r3, [r3, #2] 80013e2: 2b00 cmp r3, #0 80013e4: d106 bne.n 80013f4 80013e6: f240 4378 movw r3, #1144 ; 0x478 80013ea: f2c2 0300 movt r3, #8192 ; 0x2000 80013ee: e9d3 2302 ldrd r2, r3, [r3, #8] 80013f2: e001 b.n 80013f8 80013f4: e9d7 2322 ldrd r2, r3, [r7, #136] ; 0x88 80013f8: f240 4178 movw r1, #1144 ; 0x478 80013fc: f2c2 0100 movt r1, #8192 ; 0x2000 8001400: 7889 ldrb r1, [r1, #2] 8001402: e9cd ab00 strd sl, fp, [sp] 8001406: e9cd 2302 strd r2, r3, [sp, #8] 800140a: 9104 str r1, [sp, #16] 800140c: 4640 mov r0, r8 800140e: 4649 mov r1, r9 8001410: 4622 mov r2, r4 8001412: 462b mov r3, r5 8001414: f002 ffc0 bl 8004398 (gc.inverse_feed_rate_mode) ? inverse_feed_rate : gc.feed_rate, gc.inverse_feed_rate_mode); break; 8001418: e1cf b.n 80017ba //#ifdef __AVR_ATmega328P__ case MOTION_MODE_CW_ARC: case MOTION_MODE_CCW_ARC: if (radius_mode) { 800141a: f897 3087 ldrb.w r3, [r7, #135] ; 0x87 800141e: 2b00 cmp r3, #0 8001420: f000 815a beq.w 80016d8 j = (y + (x * h_x2_div_d))/2 */ // Calculate the change in position along each selected axis double x = target[gc.plane_axis_0]-gc.position[gc.plane_axis_0]; 8001424: f240 4378 movw r3, #1144 ; 0x478 8001428: f2c2 0300 movt r3, #8192 ; 0x2000 800142c: f893 3034 ldrb.w r3, [r3, #52] ; 0x34 8001430: ea4f 03c3 mov.w r3, r3, lsl #3 8001434: f107 0290 add.w r2, r7, #144 ; 0x90 8001438: 18d3 adds r3, r2, r3 800143a: f1a3 0370 sub.w r3, r3, #112 ; 0x70 800143e: e9d3 0100 ldrd r0, r1, [r3] 8001442: f240 4378 movw r3, #1144 ; 0x478 8001446: f2c2 0300 movt r3, #8192 ; 0x2000 800144a: f893 3034 ldrb.w r3, [r3, #52] ; 0x34 800144e: 461a mov r2, r3 8001450: f240 4378 movw r3, #1144 ; 0x478 8001454: f2c2 0300 movt r3, #8192 ; 0x2000 8001458: f102 0203 add.w r2, r2, #3 800145c: ea4f 02c2 mov.w r2, r2, lsl #3 8001460: 189b adds r3, r3, r2 8001462: e9d3 2300 ldrd r2, r3, [r3] 8001466: f007 fa07 bl 8008878 <__aeabi_dsub> 800146a: 4602 mov r2, r0 800146c: 460b mov r3, r1 800146e: e9c7 2314 strd r2, r3, [r7, #80] ; 0x50 double y = target[gc.plane_axis_1]-gc.position[gc.plane_axis_1]; 8001472: f240 4378 movw r3, #1144 ; 0x478 8001476: f2c2 0300 movt r3, #8192 ; 0x2000 800147a: f893 3035 ldrb.w r3, [r3, #53] ; 0x35 800147e: ea4f 03c3 mov.w r3, r3, lsl #3 8001482: f107 0090 add.w r0, r7, #144 ; 0x90 8001486: 18c3 adds r3, r0, r3 8001488: f1a3 0370 sub.w r3, r3, #112 ; 0x70 800148c: e9d3 0100 ldrd r0, r1, [r3] 8001490: f240 4378 movw r3, #1144 ; 0x478 8001494: f2c2 0300 movt r3, #8192 ; 0x2000 8001498: f893 3035 ldrb.w r3, [r3, #53] ; 0x35 800149c: 461a mov r2, r3 800149e: f240 4378 movw r3, #1144 ; 0x478 80014a2: f2c2 0300 movt r3, #8192 ; 0x2000 80014a6: f102 0203 add.w r2, r2, #3 80014aa: ea4f 02c2 mov.w r2, r2, lsl #3 80014ae: 189b adds r3, r3, r2 80014b0: e9d3 2300 ldrd r2, r3, [r3] 80014b4: f007 f9e0 bl 8008878 <__aeabi_dsub> 80014b8: 4602 mov r2, r0 80014ba: 460b mov r3, r1 80014bc: e9c7 2312 strd r2, r3, [r7, #72] ; 0x48 clear_vector(offset); 80014c0: f107 0308 add.w r3, r7, #8 80014c4: f04f 0200 mov.w r2, #0 80014c8: 601a str r2, [r3, #0] 80014ca: f103 0304 add.w r3, r3, #4 80014ce: f04f 0200 mov.w r2, #0 80014d2: 601a str r2, [r3, #0] 80014d4: f103 0304 add.w r3, r3, #4 80014d8: f04f 0200 mov.w r2, #0 80014dc: 601a str r2, [r3, #0] 80014de: f103 0304 add.w r3, r3, #4 80014e2: f04f 0200 mov.w r2, #0 80014e6: 601a str r2, [r3, #0] 80014e8: f103 0304 add.w r3, r3, #4 80014ec: f04f 0200 mov.w r2, #0 80014f0: 601a str r2, [r3, #0] 80014f2: f103 0304 add.w r3, r3, #4 80014f6: f04f 0200 mov.w r2, #0 80014fa: 601a str r2, [r3, #0] 80014fc: f103 0304 add.w r3, r3, #4 double h_x2_div_d = -sqrt(4 * r*r - x*x - y*y)/hypot(x,y); // == -(h * 2 / d) 8001500: e9d7 011c ldrd r0, r1, [r7, #112] ; 0x70 8001504: a370 add r3, pc, #448 ; (adr r3, 80016c8 ) 8001506: e9d3 2300 ldrd r2, r3, [r3] 800150a: f007 fb69 bl 8008be0 <__aeabi_dmul> 800150e: 4602 mov r2, r0 8001510: 460b mov r3, r1 8001512: 4610 mov r0, r2 8001514: 4619 mov r1, r3 8001516: e9d7 231c ldrd r2, r3, [r7, #112] ; 0x70 800151a: f007 fb61 bl 8008be0 <__aeabi_dmul> 800151e: 4602 mov r2, r0 8001520: 460b mov r3, r1 8001522: 4614 mov r4, r2 8001524: 461d mov r5, r3 8001526: e9d7 0114 ldrd r0, r1, [r7, #80] ; 0x50 800152a: e9d7 2314 ldrd r2, r3, [r7, #80] ; 0x50 800152e: f007 fb57 bl 8008be0 <__aeabi_dmul> 8001532: 4602 mov r2, r0 8001534: 460b mov r3, r1 8001536: 4620 mov r0, r4 8001538: 4629 mov r1, r5 800153a: f007 f99d bl 8008878 <__aeabi_dsub> 800153e: 4602 mov r2, r0 8001540: 460b mov r3, r1 8001542: 4614 mov r4, r2 8001544: 461d mov r5, r3 8001546: e9d7 0112 ldrd r0, r1, [r7, #72] ; 0x48 800154a: e9d7 2312 ldrd r2, r3, [r7, #72] ; 0x48 800154e: f007 fb47 bl 8008be0 <__aeabi_dmul> 8001552: 4602 mov r2, r0 8001554: 460b mov r3, r1 8001556: 4620 mov r0, r4 8001558: 4629 mov r1, r5 800155a: f007 f98d bl 8008878 <__aeabi_dsub> 800155e: 4602 mov r2, r0 8001560: 460b mov r3, r1 8001562: 4610 mov r0, r2 8001564: 4619 mov r1, r3 8001566: f004 ed92 blx 800608c 800156a: 4602 mov r2, r0 800156c: 460b mov r3, r1 800156e: 4690 mov r8, r2 8001570: f083 4900 eor.w r9, r3, #2147483648 ; 0x80000000 8001574: e9d7 0114 ldrd r0, r1, [r7, #80] ; 0x50 8001578: e9d7 2312 ldrd r2, r3, [r7, #72] ; 0x48 800157c: f004 ecf0 blx 8005f60 8001580: 4602 mov r2, r0 8001582: 460b mov r3, r1 8001584: 4640 mov r0, r8 8001586: 4649 mov r1, r9 8001588: f007 fc54 bl 8008e34 <__aeabi_ddiv> 800158c: 4602 mov r2, r0 800158e: 460b mov r3, r1 8001590: e9c7 231a strd r2, r3, [r7, #104] ; 0x68 // If r is smaller than d, the arc is now traversing the complex plane beyond the reach of any // real CNC, and thus - for practical reasons - we will terminate promptly: if(isnan(h_x2_div_d)) { FAIL(STATUS_FLOATING_POINT_ERROR); return(gc.status_code); } 8001594: e9d7 011a ldrd r0, r1, [r7, #104] ; 0x68 8001598: f004 e8a8 blx 80056ec <__fpclassifyd> 800159c: 4603 mov r3, r0 800159e: 2b00 cmp r3, #0 80015a0: d10c bne.n 80015bc 80015a2: f240 4378 movw r3, #1144 ; 0x478 80015a6: f2c2 0300 movt r3, #8192 ; 0x2000 80015aa: f04f 0204 mov.w r2, #4 80015ae: 701a strb r2, [r3, #0] 80015b0: f240 4378 movw r3, #1144 ; 0x478 80015b4: f2c2 0300 movt r3, #8192 ; 0x2000 80015b8: 781b ldrb r3, [r3, #0] 80015ba: e112 b.n 80017e2 // Invert the sign of h_x2_div_d if the circle is counter clockwise (see sketch below) if (gc.motion_mode == MOTION_MODE_CCW_ARC) { h_x2_div_d = -h_x2_div_d; } 80015bc: f240 4378 movw r3, #1144 ; 0x478 80015c0: f2c2 0300 movt r3, #8192 ; 0x2000 80015c4: 785b ldrb r3, [r3, #1] 80015c6: 2b03 cmp r3, #3 80015c8: d105 bne.n 80015d6 80015ca: 6ebb ldr r3, [r7, #104] ; 0x68 80015cc: 66bb str r3, [r7, #104] ; 0x68 80015ce: 6efb ldr r3, [r7, #108] ; 0x6c 80015d0: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 80015d4: 66fb str r3, [r7, #108] ; 0x6c // Negative R is g-code-alese for "I want a circle with more than 180 degrees of travel" (go figure!), // even though it is advised against ever generating such circles in a single line of g-code. By // inverting the sign of h_x2_div_d the center of the circles is placed on the opposite side of the line of // travel and thus we get the unadvisably long arcs as prescribed. if (r < 0) { 80015d6: f04f 0301 mov.w r3, #1 80015da: 461c mov r4, r3 80015dc: e9d7 011c ldrd r0, r1, [r7, #112] ; 0x70 80015e0: a337 add r3, pc, #220 ; (adr r3, 80016c0 ) 80015e2: e9d3 2300 ldrd r2, r3, [r3] 80015e6: f007 fd6d bl 80090c4 <__aeabi_dcmplt> 80015ea: 4603 mov r3, r0 80015ec: 2b00 cmp r3, #0 80015ee: d102 bne.n 80015f6 80015f0: f04f 0300 mov.w r3, #0 80015f4: 461c mov r4, r3 80015f6: b2e3 uxtb r3, r4 80015f8: 2b00 cmp r3, #0 80015fa: d00b beq.n 8001614 h_x2_div_d = -h_x2_div_d; 80015fc: 6ebb ldr r3, [r7, #104] ; 0x68 80015fe: 66bb str r3, [r7, #104] ; 0x68 8001600: 6efb ldr r3, [r7, #108] ; 0x6c 8001602: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 8001606: 66fb str r3, [r7, #108] ; 0x6c r = -r; // Finished with r. Set to positive for mc_arc 8001608: 6f3b ldr r3, [r7, #112] ; 0x70 800160a: 673b str r3, [r7, #112] ; 0x70 800160c: 6f7b ldr r3, [r7, #116] ; 0x74 800160e: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 8001612: 677b str r3, [r7, #116] ; 0x74 } // Complete the operation by calculating the actual center of the arc offset[gc.plane_axis_0] = 0.5*(x-(y*h_x2_div_d)); 8001614: f240 4378 movw r3, #1144 ; 0x478 8001618: f2c2 0300 movt r3, #8192 ; 0x2000 800161c: f893 3034 ldrb.w r3, [r3, #52] ; 0x34 8001620: 461c mov r4, r3 8001622: e9d7 0112 ldrd r0, r1, [r7, #72] ; 0x48 8001626: e9d7 231a ldrd r2, r3, [r7, #104] ; 0x68 800162a: f007 fad9 bl 8008be0 <__aeabi_dmul> 800162e: 4602 mov r2, r0 8001630: 460b mov r3, r1 8001632: e9d7 0114 ldrd r0, r1, [r7, #80] ; 0x50 8001636: f007 f91f bl 8008878 <__aeabi_dsub> 800163a: 4602 mov r2, r0 800163c: 460b mov r3, r1 800163e: 4610 mov r0, r2 8001640: 4619 mov r1, r3 8001642: a323 add r3, pc, #140 ; (adr r3, 80016d0 ) 8001644: e9d3 2300 ldrd r2, r3, [r3] 8001648: f007 faca bl 8008be0 <__aeabi_dmul> 800164c: 4602 mov r2, r0 800164e: 460b mov r3, r1 8001650: ea4f 01c4 mov.w r1, r4, lsl #3 8001654: f107 0090 add.w r0, r7, #144 ; 0x90 8001658: 1841 adds r1, r0, r1 800165a: f1a1 0188 sub.w r1, r1, #136 ; 0x88 800165e: e9c1 2300 strd r2, r3, [r1] offset[gc.plane_axis_1] = 0.5*(y+(x*h_x2_div_d)); 8001662: f240 4378 movw r3, #1144 ; 0x478 8001666: f2c2 0300 movt r3, #8192 ; 0x2000 800166a: f893 3035 ldrb.w r3, [r3, #53] ; 0x35 800166e: 461c mov r4, r3 8001670: e9d7 0114 ldrd r0, r1, [r7, #80] ; 0x50 8001674: e9d7 231a ldrd r2, r3, [r7, #104] ; 0x68 8001678: f007 fab2 bl 8008be0 <__aeabi_dmul> 800167c: 4602 mov r2, r0 800167e: 460b mov r3, r1 8001680: 4610 mov r0, r2 8001682: 4619 mov r1, r3 8001684: e9d7 2312 ldrd r2, r3, [r7, #72] ; 0x48 8001688: f007 f8f8 bl 800887c <__adddf3> 800168c: 4602 mov r2, r0 800168e: 460b mov r3, r1 8001690: 4610 mov r0, r2 8001692: 4619 mov r1, r3 8001694: a30e add r3, pc, #56 ; (adr r3, 80016d0 ) 8001696: e9d3 2300 ldrd r2, r3, [r3] 800169a: f007 faa1 bl 8008be0 <__aeabi_dmul> 800169e: 4602 mov r2, r0 80016a0: 460b mov r3, r1 80016a2: ea4f 01c4 mov.w r1, r4, lsl #3 80016a6: f107 0090 add.w r0, r7, #144 ; 0x90 80016aa: 1841 adds r1, r0, r1 80016ac: f1a1 0188 sub.w r1, r1, #136 ; 0x88 80016b0: e9c1 2300 strd r2, r3, [r1] 80016b4: e034 b.n 8001720 80016b6: bf00 nop 80016b8: 00000000 .word 0x00000000 80016bc: bff00000 .word 0xbff00000 ... 80016cc: 40100000 .word 0x40100000 80016d0: 00000000 .word 0x00000000 80016d4: 3fe00000 .word 0x3fe00000 } else { // Offset mode specific computations r = hypot(offset[gc.plane_axis_0], offset[gc.plane_axis_1]); // Compute arc radius for mc_arc 80016d8: f240 4378 movw r3, #1144 ; 0x478 80016dc: f2c2 0300 movt r3, #8192 ; 0x2000 80016e0: f893 3034 ldrb.w r3, [r3, #52] ; 0x34 80016e4: ea4f 03c3 mov.w r3, r3, lsl #3 80016e8: f107 0290 add.w r2, r7, #144 ; 0x90 80016ec: 18d3 adds r3, r2, r3 80016ee: f1a3 0388 sub.w r3, r3, #136 ; 0x88 80016f2: e9d3 0100 ldrd r0, r1, [r3] 80016f6: f240 4378 movw r3, #1144 ; 0x478 80016fa: f2c2 0300 movt r3, #8192 ; 0x2000 80016fe: f893 3035 ldrb.w r3, [r3, #53] ; 0x35 8001702: ea4f 03c3 mov.w r3, r3, lsl #3 8001706: f107 0290 add.w r2, r7, #144 ; 0x90 800170a: 18d3 adds r3, r2, r3 800170c: f1a3 0388 sub.w r3, r3, #136 ; 0x88 8001710: e9d3 2300 ldrd r2, r3, [r3] 8001714: f004 ec24 blx 8005f60 8001718: 4602 mov r2, r0 800171a: 460b mov r3, r1 800171c: e9c7 231c strd r2, r3, [r7, #112] ; 0x70 } // Set clockwise/counter-clockwise sign for mc_arc computations uint8_t isclockwise = false; 8001720: f04f 0300 mov.w r3, #0 8001724: f887 3067 strb.w r3, [r7, #103] ; 0x67 if (gc.motion_mode == MOTION_MODE_CW_ARC) { isclockwise = true; } 8001728: f240 4378 movw r3, #1144 ; 0x478 800172c: f2c2 0300 movt r3, #8192 ; 0x2000 8001730: 785b ldrb r3, [r3, #1] 8001732: 2b02 cmp r3, #2 8001734: d103 bne.n 800173e 8001736: f04f 0301 mov.w r3, #1 800173a: f887 3067 strb.w r3, [r7, #103] ; 0x67 // Trace the arc mc_arc(gc.position, target, offset, gc.plane_axis_0, gc.plane_axis_1, gc.plane_axis_2, 800173e: f240 4378 movw r3, #1144 ; 0x478 8001742: f2c2 0300 movt r3, #8192 ; 0x2000 8001746: f893 4034 ldrb.w r4, [r3, #52] ; 0x34 800174a: f240 4378 movw r3, #1144 ; 0x478 800174e: f2c2 0300 movt r3, #8192 ; 0x2000 8001752: f893 e035 ldrb.w lr, [r3, #53] ; 0x35 8001756: f240 4378 movw r3, #1144 ; 0x478 800175a: f2c2 0300 movt r3, #8192 ; 0x2000 800175e: f893 6036 ldrb.w r6, [r3, #54] ; 0x36 (gc.inverse_feed_rate_mode) ? inverse_feed_rate : gc.feed_rate, gc.inverse_feed_rate_mode, 8001762: f240 4378 movw r3, #1144 ; 0x478 8001766: f2c2 0300 movt r3, #8192 ; 0x2000 800176a: 789b ldrb r3, [r3, #2] // Set clockwise/counter-clockwise sign for mc_arc computations uint8_t isclockwise = false; if (gc.motion_mode == MOTION_MODE_CW_ARC) { isclockwise = true; } // Trace the arc mc_arc(gc.position, target, offset, gc.plane_axis_0, gc.plane_axis_1, gc.plane_axis_2, 800176c: 2b00 cmp r3, #0 800176e: d106 bne.n 800177e 8001770: f240 4378 movw r3, #1144 ; 0x478 8001774: f2c2 0300 movt r3, #8192 ; 0x2000 8001778: e9d3 2302 ldrd r2, r3, [r3, #8] 800177c: e001 b.n 8001782 800177e: e9d7 2322 ldrd r2, r3, [r7, #136] ; 0x88 8001782: f240 4178 movw r1, #1144 ; 0x478 8001786: f2c2 0100 movt r1, #8192 ; 0x2000 800178a: 7888 ldrb r0, [r1, #2] 800178c: f107 0120 add.w r1, r7, #32 8001790: f107 0508 add.w r5, r7, #8 8001794: f8cd e000 str.w lr, [sp] 8001798: 9601 str r6, [sp, #4] 800179a: e9cd 2302 strd r2, r3, [sp, #8] 800179e: 9004 str r0, [sp, #16] 80017a0: e9d7 231c ldrd r2, r3, [r7, #112] ; 0x70 80017a4: e9cd 2306 strd r2, r3, [sp, #24] 80017a8: f897 3067 ldrb.w r3, [r7, #103] ; 0x67 80017ac: 9308 str r3, [sp, #32] 80017ae: 4810 ldr r0, [pc, #64] ; (80017f0 ) 80017b0: 462a mov r2, r5 80017b2: 4623 mov r3, r4 80017b4: f001 fae8 bl 8002d88 (gc.inverse_feed_rate_mode) ? inverse_feed_rate : gc.feed_rate, gc.inverse_feed_rate_mode, r, isclockwise); break; 80017b8: bf00 nop } // As far as the parser is concerned, the position is now == target. In reality the // motion control system might still be processing the action and the real tool position // in any intermediate location. memcpy(gc.position, target, sizeof(double)*3); // gc.position[] = target[]; 80017ba: f240 4378 movw r3, #1144 ; 0x478 80017be: f2c2 0300 movt r3, #8192 ; 0x2000 80017c2: f107 0220 add.w r2, r7, #32 80017c6: f103 0418 add.w r4, r3, #24 80017ca: 4615 mov r5, r2 80017cc: cd0f ldmia r5!, {r0, r1, r2, r3} 80017ce: c40f stmia r4!, {r0, r1, r2, r3} 80017d0: e895 0003 ldmia.w r5, {r0, r1} 80017d4: e884 0003 stmia.w r4, {r0, r1} return(gc.status_code); 80017d8: f240 4378 movw r3, #1144 ; 0x478 80017dc: f2c2 0300 movt r3, #8192 ; 0x2000 80017e0: 781b ldrb r3, [r3, #0] } 80017e2: 4618 mov r0, r3 80017e4: f107 0794 add.w r7, r7, #148 ; 0x94 80017e8: 46bd mov sp, r7 80017ea: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 80017ee: bf00 nop 80017f0: 20000490 .word 0x20000490 80017f4: f3af 8000 nop.w 080017f8 : // Parses the next statement and leaves the counter on the first character following // the statement. Returns 1 if there was a statements, 0 if end of string was reached // or there was an error (check state.status_code). static int next_statement(char *letter, double *double_ptr, char *line, uint8_t *char_counter) { 80017f8: b580 push {r7, lr} 80017fa: b084 sub sp, #16 80017fc: af00 add r7, sp, #0 80017fe: 60f8 str r0, [r7, #12] 8001800: 60b9 str r1, [r7, #8] 8001802: 607a str r2, [r7, #4] 8001804: 603b str r3, [r7, #0] if (line[*char_counter] == 0) { 8001806: 683b ldr r3, [r7, #0] 8001808: 781b ldrb r3, [r3, #0] 800180a: 687a ldr r2, [r7, #4] 800180c: 18d3 adds r3, r2, r3 800180e: 781b ldrb r3, [r3, #0] 8001810: 2b00 cmp r3, #0 8001812: d102 bne.n 800181a return(0); // No more statements 8001814: f04f 0300 mov.w r3, #0 8001818: e033 b.n 8001882 } *letter = line[*char_counter]; 800181a: 683b ldr r3, [r7, #0] 800181c: 781b ldrb r3, [r3, #0] 800181e: 687a ldr r2, [r7, #4] 8001820: 18d3 adds r3, r2, r3 8001822: 781a ldrb r2, [r3, #0] 8001824: 68fb ldr r3, [r7, #12] 8001826: 701a strb r2, [r3, #0] if((*letter < 'A') || (*letter > 'Z')) { 8001828: 68fb ldr r3, [r7, #12] 800182a: 781b ldrb r3, [r3, #0] 800182c: 2b40 cmp r3, #64 ; 0x40 800182e: d903 bls.n 8001838 8001830: 68fb ldr r3, [r7, #12] 8001832: 781b ldrb r3, [r3, #0] 8001834: 2b5a cmp r3, #90 ; 0x5a 8001836: d909 bls.n 800184c FAIL(STATUS_EXPECTED_COMMAND_LETTER); 8001838: f240 4378 movw r3, #1144 ; 0x478 800183c: f2c2 0300 movt r3, #8192 ; 0x2000 8001840: f04f 0202 mov.w r2, #2 8001844: 701a strb r2, [r3, #0] return(0); 8001846: f04f 0300 mov.w r3, #0 800184a: e01a b.n 8001882 } (*char_counter)++; 800184c: 683b ldr r3, [r7, #0] 800184e: 781b ldrb r3, [r3, #0] 8001850: f103 0301 add.w r3, r3, #1 8001854: b2da uxtb r2, r3 8001856: 683b ldr r3, [r7, #0] 8001858: 701a strb r2, [r3, #0] if (!read_double(line, char_counter, double_ptr)) { 800185a: 6878 ldr r0, [r7, #4] 800185c: 6839 ldr r1, [r7, #0] 800185e: 68ba ldr r2, [r7, #8] 8001860: f000 fec8 bl 80025f4 8001864: 4603 mov r3, r0 8001866: 2b00 cmp r3, #0 8001868: d109 bne.n 800187e FAIL(STATUS_BAD_NUMBER_FORMAT); 800186a: f240 4378 movw r3, #1144 ; 0x478 800186e: f2c2 0300 movt r3, #8192 ; 0x2000 8001872: f04f 0201 mov.w r2, #1 8001876: 701a strb r2, [r3, #0] return(0); 8001878: f04f 0300 mov.w r3, #0 800187c: e001 b.n 8001882 }; return(1); 800187e: f04f 0301 mov.w r3, #1 } 8001882: 4618 mov r0, r3 8001884: f107 0710 add.w r7, r7, #16 8001888: 46bd mov sp, r7 800188a: bd80 pop {r7, pc} 0800188c : static void set_step_events_per_minute(uint32_t steps_per_minute); // Stepper state initialization static void st_wake_up() { 800188c: b580 push {r7, lr} 800188e: af00 add r7, sp, #0 // Initialize stepper output bits out_bits = (0) ^ (settings.invert_mask); 8001890: f240 63d8 movw r3, #1752 ; 0x6d8 8001894: f2c2 0300 movt r3, #8192 ; 0x2000 8001898: 8e1b ldrh r3, [r3, #48] ; 0x30 800189a: b2da uxtb r2, r3 800189c: f240 43b4 movw r3, #1204 ; 0x4b4 80018a0: f2c2 0300 movt r3, #8192 ; 0x2000 80018a4: 701a strb r2, [r3, #0] // Enable steppers by resetting the stepper disable port RCC_AHB1PeriphClockCmd((uint32_t)STEPPING_PORT, 1); 80018a6: f44f 6000 mov.w r0, #2048 ; 0x800 80018aa: f2c4 0002 movt r0, #16386 ; 0x4002 80018ae: f04f 0101 mov.w r1, #1 80018b2: f000 fe05 bl 80024c0 // Enable stepper driver interrupt TIM_Cmd(TIM1, 1); 80018b6: f04f 0000 mov.w r0, #0 80018ba: f2c4 0001 movt r0, #16385 ; 0x4001 80018be: f04f 0101 mov.w r1, #1 80018c2: f003 fdcb bl 800545c //TIMSK1 |= (1<: // Stepper shutdown static void st_go_idle() { 80018c8: b580 push {r7, lr} 80018ca: af00 add r7, sp, #0 // Cycle finished. Set flag to false. cycle_start = false; 80018cc: f240 43dc movw r3, #1244 ; 0x4dc 80018d0: f2c2 0300 movt r3, #8192 ; 0x2000 80018d4: f04f 0200 mov.w r2, #0 80018d8: 701a strb r2, [r3, #0] // Disable stepper driver interrupt TIM_Cmd(TIM1, 0); 80018da: f04f 0000 mov.w r0, #0 80018de: f2c4 0001 movt r0, #16385 ; 0x4001 80018e2: f04f 0100 mov.w r1, #0 80018e6: f003 fdb9 bl 800545c //TIMSK1 &= ~(1< #endif // Disable steppers by setting stepper disable RCC_AHB1PeriphClockCmd((uint32_t)STEPPING_PORT, 1); 80018f2: f44f 6000 mov.w r0, #2048 ; 0x800 80018f6: f2c4 0002 movt r0, #16386 ; 0x4002 80018fa: f04f 0101 mov.w r1, #1 80018fe: f000 fddf bl 80024c0 //STEPPERS_DISABLE_PORT |= (1<: // Initializes the trapezoid generator from the current block. Called whenever a new // block begins. static void trapezoid_generator_reset() { 8001904: b580 push {r7, lr} 8001906: af00 add r7, sp, #0 trapezoid_adjusted_rate = current_block->initial_rate; 8001908: f240 43b0 movw r3, #1200 ; 0x4b0 800190c: f2c2 0300 movt r3, #8192 ; 0x2000 8001910: 681b ldr r3, [r3, #0] 8001912: 6bda ldr r2, [r3, #60] ; 0x3c 8001914: f240 43d4 movw r3, #1236 ; 0x4d4 8001918: f2c2 0300 movt r3, #8192 ; 0x2000 800191c: 601a str r2, [r3, #0] min_safe_rate = current_block->rate_delta + (current_block->rate_delta >> 1); // 1.5 x rate_delta 800191e: f240 43b0 movw r3, #1200 ; 0x4b0 8001922: f2c2 0300 movt r3, #8192 ; 0x2000 8001926: 681b ldr r3, [r3, #0] 8001928: 6c5a ldr r2, [r3, #68] ; 0x44 800192a: f240 43b0 movw r3, #1200 ; 0x4b0 800192e: f2c2 0300 movt r3, #8192 ; 0x2000 8001932: 681b ldr r3, [r3, #0] 8001934: 6c5b ldr r3, [r3, #68] ; 0x44 8001936: ea4f 0363 mov.w r3, r3, asr #1 800193a: 18d3 adds r3, r2, r3 800193c: 461a mov r2, r3 800193e: f240 43d8 movw r3, #1240 ; 0x4d8 8001942: f2c2 0300 movt r3, #8192 ; 0x2000 8001946: 601a str r2, [r3, #0] trapezoid_tick_cycle_counter = CYCLES_PER_ACCELERATION_TICK/2; // Start halfway for midpoint rule. 8001948: f240 43d0 movw r3, #1232 ; 0x4d0 800194c: f2c2 0300 movt r3, #8192 ; 0x2000 8001950: f24a 2280 movw r2, #41600 ; 0xa280 8001954: f2c0 0219 movt r2, #25 8001958: 601a str r2, [r3, #0] set_step_events_per_minute(trapezoid_adjusted_rate); // Initialize cycles_per_step_event 800195a: f240 43d4 movw r3, #1236 ; 0x4d4 800195e: f2c2 0300 movt r3, #8192 ; 0x2000 8001962: 681b ldr r3, [r3, #0] 8001964: 4618 mov r0, r3 8001966: f000 fb8b bl 8002080 } 800196a: bd80 pop {r7, pc} 0800196c : // This function determines an acceleration velocity change every CYCLES_PER_ACCELERATION_TICK by // keeping track of the number of elapsed cycles during a de/ac-celeration. The code assumes that // step_events occur significantly more often than the acceleration velocity iterations. static uint8_t iterate_trapezoid_cycle_counter() { 800196c: b480 push {r7} 800196e: af00 add r7, sp, #0 trapezoid_tick_cycle_counter += cycles_per_step_event; 8001970: f240 43d0 movw r3, #1232 ; 0x4d0 8001974: f2c2 0300 movt r3, #8192 ; 0x2000 8001978: 681a ldr r2, [r3, #0] 800197a: f240 43cc movw r3, #1228 ; 0x4cc 800197e: f2c2 0300 movt r3, #8192 ; 0x2000 8001982: 681b ldr r3, [r3, #0] 8001984: 18d2 adds r2, r2, r3 8001986: f240 43d0 movw r3, #1232 ; 0x4d0 800198a: f2c2 0300 movt r3, #8192 ; 0x2000 800198e: 601a str r2, [r3, #0] if(trapezoid_tick_cycle_counter > CYCLES_PER_ACCELERATION_TICK) { 8001990: f240 43d0 movw r3, #1232 ; 0x4d0 8001994: f2c2 0300 movt r3, #8192 ; 0x2000 8001998: 681a ldr r2, [r3, #0] 800199a: f44f 438a mov.w r3, #17664 ; 0x4500 800199e: f2c0 0333 movt r3, #51 ; 0x33 80019a2: 429a cmp r2, r3 80019a4: d910 bls.n 80019c8 trapezoid_tick_cycle_counter -= CYCLES_PER_ACCELERATION_TICK; 80019a6: f240 43d0 movw r3, #1232 ; 0x4d0 80019aa: f2c2 0300 movt r3, #8192 ; 0x2000 80019ae: 681b ldr r3, [r3, #0] 80019b0: f5a3 124c sub.w r2, r3, #3342336 ; 0x330000 80019b4: f5a2 428a sub.w r2, r2, #17664 ; 0x4500 80019b8: f240 43d0 movw r3, #1232 ; 0x4d0 80019bc: f2c2 0300 movt r3, #8192 ; 0x2000 80019c0: 601a str r2, [r3, #0] return(true); 80019c2: f04f 0301 mov.w r3, #1 80019c6: e001 b.n 80019cc } else { return(false); 80019c8: f04f 0300 mov.w r3, #0 } } 80019cc: 4618 mov r0, r3 80019ce: 46bd mov sp, r7 80019d0: bc80 pop {r7} 80019d2: 4770 bx lr 080019d4 : // "The Stepper Driver Interrupt" - This timer interrupt is the workhorse of Grbl. It is executed at the rate set with // config_step_timer. It pops blocks from the block_buffer and executes them by pulsing the stepper pins appropriately. // It is supported by The Stepper Port Reset Interrupt which it uses to reset the stepper port after each pulse. // The bresenham line tracer algorithm controls all three stepper outputs simultaneously with these two interrupts. void TIM2_IRQHandler(void) { 80019d4: b580 push {r7, lr} 80019d6: af00 add r7, sp, #0 if (TIM_GetITStatus(TIM2, TIM_IT_Update) == RESET) return; 80019d8: f04f 4080 mov.w r0, #1073741824 ; 0x40000000 80019dc: f04f 0101 mov.w r1, #1 80019e0: f003 fda0 bl 8005524 80019e4: 4603 mov r3, r0 80019e6: 2b00 cmp r3, #0 80019e8: f000 8255 beq.w 8001e96 TIM_ClearITPendingBit(TIM2, TIM_IT_Update); 80019ec: f04f 4080 mov.w r0, #1073741824 ; 0x40000000 80019f0: f04f 0101 mov.w r1, #1 80019f4: f003 fdc6 bl 8005584 if (busy) { return; } // The busy-flag is used to avoid reentering this interrupt 80019f8: f240 43c8 movw r3, #1224 ; 0x4c8 80019fc: f2c2 0300 movt r3, #8192 ; 0x2000 8001a00: 781b ldrb r3, [r3, #0] 8001a02: b2db uxtb r3, r3 8001a04: 2b00 cmp r3, #0 8001a06: f040 8248 bne.w 8001e9a TCNT2 = -(((settings.pulse_microseconds-2)*TICKS_PER_MICROSECOND) >> 3); // Reload timer counter TCCR2B = (1< // Then pulse the stepping pins set(STEP_MASK); 8001a20: f04f 001c mov.w r0, #28 8001a24: f000 fe12 bl 800264c // Enable step pulse reset timer so that The Stepper Port Reset Interrupt can reset the signal after // exactly settings.pulse_microseconds microseconds, independent of the main Timer1 prescaler. TIM_SetCounter(TIM1, 0); 8001a28: f04f 0000 mov.w r0, #0 8001a2c: f2c4 0001 movt r0, #16385 ; 0x4001 8001a30: f04f 0100 mov.w r1, #0 8001a34: f003 fd04 bl 8005440 TIM_SetCompare1(TIM1,(settings.pulse_microseconds-2)*TICKS_PER_MICROSECOND); 8001a38: f240 63d8 movw r3, #1752 ; 0x6d8 8001a3c: f2c2 0300 movt r3, #8192 ; 0x2000 8001a40: 7e5b ldrb r3, [r3, #25] 8001a42: f04f 02a8 mov.w r2, #168 ; 0xa8 8001a46: fb02 f303 mul.w r3, r2, r3 8001a4a: f5a3 73a8 sub.w r3, r3, #336 ; 0x150 8001a4e: f04f 0000 mov.w r0, #0 8001a52: f2c4 0001 movt r0, #16385 ; 0x4001 8001a56: 4619 mov r1, r3 8001a58: f003 fd20 bl 800549c //TODO Zeit pruefen busy = true; 8001a5c: f240 43c8 movw r3, #1224 ; 0x4c8 8001a60: f2c2 0300 movt r3, #8192 ; 0x2000 8001a64: f04f 0201 mov.w r2, #1 8001a68: 701a strb r2, [r3, #0] // regardless of time in this handler. The following code prepares the stepper driver for the next // step interrupt compare and will always finish before returning to the main program. //sei(); // If there is no current block, attempt to pop one from the buffer if (current_block == NULL) { 8001a6a: f240 43b0 movw r3, #1200 ; 0x4b0 8001a6e: f2c2 0300 movt r3, #8192 ; 0x2000 8001a72: 681b ldr r3, [r3, #0] 8001a74: 2b00 cmp r3, #0 8001a76: d13d bne.n 8001af4 // Anything in the buffer? If so, initialize next motion. current_block = plan_get_current_block(); 8001a78: f002 fc68 bl 800434c 8001a7c: 4602 mov r2, r0 8001a7e: f240 43b0 movw r3, #1200 ; 0x4b0 8001a82: f2c2 0300 movt r3, #8192 ; 0x2000 8001a86: 601a str r2, [r3, #0] if (current_block != NULL) { 8001a88: f240 43b0 movw r3, #1200 ; 0x4b0 8001a8c: f2c2 0300 movt r3, #8192 ; 0x2000 8001a90: 681b ldr r3, [r3, #0] 8001a92: 2b00 cmp r3, #0 8001a94: d02c beq.n 8001af0 trapezoid_generator_reset(); 8001a96: f7ff ff35 bl 8001904 counter_x = -(current_block->step_event_count >> 1); 8001a9a: f240 43b0 movw r3, #1200 ; 0x4b0 8001a9e: f2c2 0300 movt r3, #8192 ; 0x2000 8001aa2: 681b ldr r3, [r3, #0] 8001aa4: 691b ldr r3, [r3, #16] 8001aa6: ea4f 0363 mov.w r3, r3, asr #1 8001aaa: f1c3 0200 rsb r2, r3, #0 8001aae: f240 43b8 movw r3, #1208 ; 0x4b8 8001ab2: f2c2 0300 movt r3, #8192 ; 0x2000 8001ab6: 601a str r2, [r3, #0] counter_y = counter_x; 8001ab8: f240 43b8 movw r3, #1208 ; 0x4b8 8001abc: f2c2 0300 movt r3, #8192 ; 0x2000 8001ac0: 681a ldr r2, [r3, #0] 8001ac2: f240 43bc movw r3, #1212 ; 0x4bc 8001ac6: f2c2 0300 movt r3, #8192 ; 0x2000 8001aca: 601a str r2, [r3, #0] counter_z = counter_x; 8001acc: f240 43b8 movw r3, #1208 ; 0x4b8 8001ad0: f2c2 0300 movt r3, #8192 ; 0x2000 8001ad4: 681a ldr r2, [r3, #0] 8001ad6: f240 43c0 movw r3, #1216 ; 0x4c0 8001ada: f2c2 0300 movt r3, #8192 ; 0x2000 8001ade: 601a str r2, [r3, #0] step_events_completed = 0; 8001ae0: f240 43c4 movw r3, #1220 ; 0x4c4 8001ae4: f2c2 0300 movt r3, #8192 ; 0x2000 8001ae8: f04f 0200 mov.w r2, #0 8001aec: 601a str r2, [r3, #0] 8001aee: e001 b.n 8001af4 } else { st_go_idle(); 8001af0: f7ff feea bl 80018c8 } } if (current_block != NULL) { 8001af4: f240 43b0 movw r3, #1200 ; 0x4b0 8001af8: f2c2 0300 movt r3, #8192 ; 0x2000 8001afc: 681b ldr r3, [r3, #0] 8001afe: 2b00 cmp r3, #0 8001b00: f000 81af beq.w 8001e62 // Execute step displacement profile by bresenham line algorithm out_bits = current_block->direction_bits; 8001b04: f240 43b0 movw r3, #1200 ; 0x4b0 8001b08: f2c2 0300 movt r3, #8192 ; 0x2000 8001b0c: 681b ldr r3, [r3, #0] 8001b0e: 781a ldrb r2, [r3, #0] 8001b10: f240 43b4 movw r3, #1204 ; 0x4b4 8001b14: f2c2 0300 movt r3, #8192 ; 0x2000 8001b18: 701a strb r2, [r3, #0] counter_x += current_block->steps_x; 8001b1a: f240 43b0 movw r3, #1200 ; 0x4b0 8001b1e: f2c2 0300 movt r3, #8192 ; 0x2000 8001b22: 681b ldr r3, [r3, #0] 8001b24: 685a ldr r2, [r3, #4] 8001b26: f240 43b8 movw r3, #1208 ; 0x4b8 8001b2a: f2c2 0300 movt r3, #8192 ; 0x2000 8001b2e: 681b ldr r3, [r3, #0] 8001b30: 18d3 adds r3, r2, r3 8001b32: 461a mov r2, r3 8001b34: f240 43b8 movw r3, #1208 ; 0x4b8 8001b38: f2c2 0300 movt r3, #8192 ; 0x2000 8001b3c: 601a str r2, [r3, #0] if (counter_x > 0) { 8001b3e: f240 43b8 movw r3, #1208 ; 0x4b8 8001b42: f2c2 0300 movt r3, #8192 ; 0x2000 8001b46: 681b ldr r3, [r3, #0] 8001b48: 2b00 cmp r3, #0 8001b4a: dd1d ble.n 8001b88 out_bits |= X_STEP_BIT; 8001b4c: f240 43b4 movw r3, #1204 ; 0x4b4 8001b50: f2c2 0300 movt r3, #8192 ; 0x2000 8001b54: 781b ldrb r3, [r3, #0] 8001b56: f043 0304 orr.w r3, r3, #4 8001b5a: b2da uxtb r2, r3 8001b5c: f240 43b4 movw r3, #1204 ; 0x4b4 8001b60: f2c2 0300 movt r3, #8192 ; 0x2000 8001b64: 701a strb r2, [r3, #0] counter_x -= current_block->step_event_count; 8001b66: f240 43b8 movw r3, #1208 ; 0x4b8 8001b6a: f2c2 0300 movt r3, #8192 ; 0x2000 8001b6e: 681a ldr r2, [r3, #0] 8001b70: f240 43b0 movw r3, #1200 ; 0x4b0 8001b74: f2c2 0300 movt r3, #8192 ; 0x2000 8001b78: 681b ldr r3, [r3, #0] 8001b7a: 691b ldr r3, [r3, #16] 8001b7c: 1ad2 subs r2, r2, r3 8001b7e: f240 43b8 movw r3, #1208 ; 0x4b8 8001b82: f2c2 0300 movt r3, #8192 ; 0x2000 8001b86: 601a str r2, [r3, #0] } counter_y += current_block->steps_y; 8001b88: f240 43b0 movw r3, #1200 ; 0x4b0 8001b8c: f2c2 0300 movt r3, #8192 ; 0x2000 8001b90: 681b ldr r3, [r3, #0] 8001b92: 689a ldr r2, [r3, #8] 8001b94: f240 43bc movw r3, #1212 ; 0x4bc 8001b98: f2c2 0300 movt r3, #8192 ; 0x2000 8001b9c: 681b ldr r3, [r3, #0] 8001b9e: 18d3 adds r3, r2, r3 8001ba0: 461a mov r2, r3 8001ba2: f240 43bc movw r3, #1212 ; 0x4bc 8001ba6: f2c2 0300 movt r3, #8192 ; 0x2000 8001baa: 601a str r2, [r3, #0] if (counter_y > 0) { 8001bac: f240 43bc movw r3, #1212 ; 0x4bc 8001bb0: f2c2 0300 movt r3, #8192 ; 0x2000 8001bb4: 681b ldr r3, [r3, #0] 8001bb6: 2b00 cmp r3, #0 8001bb8: dd1d ble.n 8001bf6 out_bits |= Y_STEP_BIT; 8001bba: f240 43b4 movw r3, #1204 ; 0x4b4 8001bbe: f2c2 0300 movt r3, #8192 ; 0x2000 8001bc2: 781b ldrb r3, [r3, #0] 8001bc4: f043 0308 orr.w r3, r3, #8 8001bc8: b2da uxtb r2, r3 8001bca: f240 43b4 movw r3, #1204 ; 0x4b4 8001bce: f2c2 0300 movt r3, #8192 ; 0x2000 8001bd2: 701a strb r2, [r3, #0] counter_y -= current_block->step_event_count; 8001bd4: f240 43bc movw r3, #1212 ; 0x4bc 8001bd8: f2c2 0300 movt r3, #8192 ; 0x2000 8001bdc: 681a ldr r2, [r3, #0] 8001bde: f240 43b0 movw r3, #1200 ; 0x4b0 8001be2: f2c2 0300 movt r3, #8192 ; 0x2000 8001be6: 681b ldr r3, [r3, #0] 8001be8: 691b ldr r3, [r3, #16] 8001bea: 1ad2 subs r2, r2, r3 8001bec: f240 43bc movw r3, #1212 ; 0x4bc 8001bf0: f2c2 0300 movt r3, #8192 ; 0x2000 8001bf4: 601a str r2, [r3, #0] } counter_z += current_block->steps_z; 8001bf6: f240 43b0 movw r3, #1200 ; 0x4b0 8001bfa: f2c2 0300 movt r3, #8192 ; 0x2000 8001bfe: 681b ldr r3, [r3, #0] 8001c00: 68da ldr r2, [r3, #12] 8001c02: f240 43c0 movw r3, #1216 ; 0x4c0 8001c06: f2c2 0300 movt r3, #8192 ; 0x2000 8001c0a: 681b ldr r3, [r3, #0] 8001c0c: 18d3 adds r3, r2, r3 8001c0e: 461a mov r2, r3 8001c10: f240 43c0 movw r3, #1216 ; 0x4c0 8001c14: f2c2 0300 movt r3, #8192 ; 0x2000 8001c18: 601a str r2, [r3, #0] if (counter_z > 0) { 8001c1a: f240 43c0 movw r3, #1216 ; 0x4c0 8001c1e: f2c2 0300 movt r3, #8192 ; 0x2000 8001c22: 681b ldr r3, [r3, #0] 8001c24: 2b00 cmp r3, #0 8001c26: dd1d ble.n 8001c64 out_bits |= Z_STEP_BIT; 8001c28: f240 43b4 movw r3, #1204 ; 0x4b4 8001c2c: f2c2 0300 movt r3, #8192 ; 0x2000 8001c30: 781b ldrb r3, [r3, #0] 8001c32: f043 0310 orr.w r3, r3, #16 8001c36: b2da uxtb r2, r3 8001c38: f240 43b4 movw r3, #1204 ; 0x4b4 8001c3c: f2c2 0300 movt r3, #8192 ; 0x2000 8001c40: 701a strb r2, [r3, #0] counter_z -= current_block->step_event_count; 8001c42: f240 43c0 movw r3, #1216 ; 0x4c0 8001c46: f2c2 0300 movt r3, #8192 ; 0x2000 8001c4a: 681a ldr r2, [r3, #0] 8001c4c: f240 43b0 movw r3, #1200 ; 0x4b0 8001c50: f2c2 0300 movt r3, #8192 ; 0x2000 8001c54: 681b ldr r3, [r3, #0] 8001c56: 691b ldr r3, [r3, #16] 8001c58: 1ad2 subs r2, r2, r3 8001c5a: f240 43c0 movw r3, #1216 ; 0x4c0 8001c5e: f2c2 0300 movt r3, #8192 ; 0x2000 8001c62: 601a str r2, [r3, #0] } step_events_completed++; // Iterate step events 8001c64: f240 43c4 movw r3, #1220 ; 0x4c4 8001c68: f2c2 0300 movt r3, #8192 ; 0x2000 8001c6c: 681b ldr r3, [r3, #0] 8001c6e: f103 0201 add.w r2, r3, #1 8001c72: f240 43c4 movw r3, #1220 ; 0x4c4 8001c76: f2c2 0300 movt r3, #8192 ; 0x2000 8001c7a: 601a str r2, [r3, #0] // While in block steps, check for de/ac-celeration events and execute them accordingly. if (step_events_completed < current_block->step_event_count) { 8001c7c: f240 43b0 movw r3, #1200 ; 0x4b0 8001c80: f2c2 0300 movt r3, #8192 ; 0x2000 8001c84: 681b ldr r3, [r3, #0] 8001c86: 691b ldr r3, [r3, #16] 8001c88: 461a mov r2, r3 8001c8a: f240 43c4 movw r3, #1220 ; 0x4c4 8001c8e: f2c2 0300 movt r3, #8192 ; 0x2000 8001c92: 681b ldr r3, [r3, #0] 8001c94: 429a cmp r2, r3 8001c96: f240 80db bls.w 8001e50 // the target position and speed. // NOTE: By increasing the ACCELERATION_TICKS_PER_SECOND in config.h, the resolution of the // discrete velocity changes increase and accuracy can increase as well to a point. Numerical // round-off errors can effect this, if set too high. This is important to note if a user has // very high acceleration and/or feedrate requirements for their machine. if (step_events_completed < current_block->accelerate_until) { 8001c9a: f240 43b0 movw r3, #1200 ; 0x4b0 8001c9e: f2c2 0300 movt r3, #8192 ; 0x2000 8001ca2: 681b ldr r3, [r3, #0] 8001ca4: 6c9a ldr r2, [r3, #72] ; 0x48 8001ca6: f240 43c4 movw r3, #1220 ; 0x4c4 8001caa: f2c2 0300 movt r3, #8192 ; 0x2000 8001cae: 681b ldr r3, [r3, #0] 8001cb0: 429a cmp r2, r3 8001cb2: d938 bls.n 8001d26 // Iterate cycle counter and check if speeds need to be increased. if ( iterate_trapezoid_cycle_counter() ) { 8001cb4: f7ff fe5a bl 800196c 8001cb8: 4603 mov r3, r0 8001cba: 2b00 cmp r3, #0 8001cbc: f000 80d1 beq.w 8001e62 trapezoid_adjusted_rate += current_block->rate_delta; 8001cc0: f240 43b0 movw r3, #1200 ; 0x4b0 8001cc4: f2c2 0300 movt r3, #8192 ; 0x2000 8001cc8: 681b ldr r3, [r3, #0] 8001cca: 6c5b ldr r3, [r3, #68] ; 0x44 8001ccc: 461a mov r2, r3 8001cce: f240 43d4 movw r3, #1236 ; 0x4d4 8001cd2: f2c2 0300 movt r3, #8192 ; 0x2000 8001cd6: 681b ldr r3, [r3, #0] 8001cd8: 18d2 adds r2, r2, r3 8001cda: f240 43d4 movw r3, #1236 ; 0x4d4 8001cde: f2c2 0300 movt r3, #8192 ; 0x2000 8001ce2: 601a str r2, [r3, #0] if (trapezoid_adjusted_rate >= current_block->nominal_rate) { 8001ce4: f240 43b0 movw r3, #1200 ; 0x4b0 8001ce8: f2c2 0300 movt r3, #8192 ; 0x2000 8001cec: 681b ldr r3, [r3, #0] 8001cee: 6d1a ldr r2, [r3, #80] ; 0x50 8001cf0: f240 43d4 movw r3, #1236 ; 0x4d4 8001cf4: f2c2 0300 movt r3, #8192 ; 0x2000 8001cf8: 681b ldr r3, [r3, #0] 8001cfa: 429a cmp r2, r3 8001cfc: d80a bhi.n 8001d14 // Reached nominal rate a little early. Cruise at nominal rate until decelerate_after. trapezoid_adjusted_rate = current_block->nominal_rate; 8001cfe: f240 43b0 movw r3, #1200 ; 0x4b0 8001d02: f2c2 0300 movt r3, #8192 ; 0x2000 8001d06: 681b ldr r3, [r3, #0] 8001d08: 6d1a ldr r2, [r3, #80] ; 0x50 8001d0a: f240 43d4 movw r3, #1236 ; 0x4d4 8001d0e: f2c2 0300 movt r3, #8192 ; 0x2000 8001d12: 601a str r2, [r3, #0] } set_step_events_per_minute(trapezoid_adjusted_rate); 8001d14: f240 43d4 movw r3, #1236 ; 0x4d4 8001d18: f2c2 0300 movt r3, #8192 ; 0x2000 8001d1c: 681b ldr r3, [r3, #0] 8001d1e: 4618 mov r0, r3 8001d20: f000 f9ae bl 8002080 8001d24: e09d b.n 8001e62 } } else if (step_events_completed >= current_block->decelerate_after) { 8001d26: f240 43b0 movw r3, #1200 ; 0x4b0 8001d2a: f2c2 0300 movt r3, #8192 ; 0x2000 8001d2e: 681b ldr r3, [r3, #0] 8001d30: 6cda ldr r2, [r3, #76] ; 0x4c 8001d32: f240 43c4 movw r3, #1220 ; 0x4c4 8001d36: f2c2 0300 movt r3, #8192 ; 0x2000 8001d3a: 681b ldr r3, [r3, #0] 8001d3c: 429a cmp r2, r3 8001d3e: d866 bhi.n 8001e0e // Reset trapezoid tick cycle counter to make sure that the deceleration is performed the // same every time. Reset to CYCLES_PER_ACCELERATION_TICK/2 to follow the midpoint rule for // an accurate approximation of the deceleration curve. if (step_events_completed == current_block-> decelerate_after) { 8001d40: f240 43b0 movw r3, #1200 ; 0x4b0 8001d44: f2c2 0300 movt r3, #8192 ; 0x2000 8001d48: 681b ldr r3, [r3, #0] 8001d4a: 6cda ldr r2, [r3, #76] ; 0x4c 8001d4c: f240 43c4 movw r3, #1220 ; 0x4c4 8001d50: f2c2 0300 movt r3, #8192 ; 0x2000 8001d54: 681b ldr r3, [r3, #0] 8001d56: 429a cmp r2, r3 8001d58: d109 bne.n 8001d6e trapezoid_tick_cycle_counter = CYCLES_PER_ACCELERATION_TICK/2; 8001d5a: f240 43d0 movw r3, #1232 ; 0x4d0 8001d5e: f2c2 0300 movt r3, #8192 ; 0x2000 8001d62: f24a 2280 movw r2, #41600 ; 0xa280 8001d66: f2c0 0219 movt r2, #25 8001d6a: 601a str r2, [r3, #0] 8001d6c: e079 b.n 8001e62 } else { // Iterate cycle counter and check if speeds need to be reduced. if ( iterate_trapezoid_cycle_counter() ) { 8001d6e: f7ff fdfd bl 800196c 8001d72: 4603 mov r3, r0 8001d74: 2b00 cmp r3, #0 8001d76: d074 beq.n 8001e62 // CNC acceleration limits, because they will never be greater than rate_delta. This catches // small errors that might leave steps hanging after the last trapezoid tick or a very slow // step rate at the end of a full stop deceleration in certain situations. The half rate // reductions should only be called once or twice per block and create a nice smooth // end deceleration. if (trapezoid_adjusted_rate > min_safe_rate) { 8001d78: f240 43d4 movw r3, #1236 ; 0x4d4 8001d7c: f2c2 0300 movt r3, #8192 ; 0x2000 8001d80: 681a ldr r2, [r3, #0] 8001d82: f240 43d8 movw r3, #1240 ; 0x4d8 8001d86: f2c2 0300 movt r3, #8192 ; 0x2000 8001d8a: 681b ldr r3, [r3, #0] 8001d8c: 429a cmp r2, r3 8001d8e: d911 bls.n 8001db4 trapezoid_adjusted_rate -= current_block->rate_delta; 8001d90: f240 43d4 movw r3, #1236 ; 0x4d4 8001d94: f2c2 0300 movt r3, #8192 ; 0x2000 8001d98: 681a ldr r2, [r3, #0] 8001d9a: f240 43b0 movw r3, #1200 ; 0x4b0 8001d9e: f2c2 0300 movt r3, #8192 ; 0x2000 8001da2: 681b ldr r3, [r3, #0] 8001da4: 6c5b ldr r3, [r3, #68] ; 0x44 8001da6: 1ad2 subs r2, r2, r3 8001da8: f240 43d4 movw r3, #1236 ; 0x4d4 8001dac: f2c2 0300 movt r3, #8192 ; 0x2000 8001db0: 601a str r2, [r3, #0] 8001db2: e00b b.n 8001dcc } else { trapezoid_adjusted_rate >>= 1; // Bit shift divide by 2 8001db4: f240 43d4 movw r3, #1236 ; 0x4d4 8001db8: f2c2 0300 movt r3, #8192 ; 0x2000 8001dbc: 681b ldr r3, [r3, #0] 8001dbe: ea4f 0253 mov.w r2, r3, lsr #1 8001dc2: f240 43d4 movw r3, #1236 ; 0x4d4 8001dc6: f2c2 0300 movt r3, #8192 ; 0x2000 8001dca: 601a str r2, [r3, #0] } if (trapezoid_adjusted_rate < current_block->final_rate) { 8001dcc: f240 43b0 movw r3, #1200 ; 0x4b0 8001dd0: f2c2 0300 movt r3, #8192 ; 0x2000 8001dd4: 681b ldr r3, [r3, #0] 8001dd6: 6c1a ldr r2, [r3, #64] ; 0x40 8001dd8: f240 43d4 movw r3, #1236 ; 0x4d4 8001ddc: f2c2 0300 movt r3, #8192 ; 0x2000 8001de0: 681b ldr r3, [r3, #0] 8001de2: 429a cmp r2, r3 8001de4: d90a bls.n 8001dfc // Reached final rate a little early. Cruise to end of block at final rate. trapezoid_adjusted_rate = current_block->final_rate; 8001de6: f240 43b0 movw r3, #1200 ; 0x4b0 8001dea: f2c2 0300 movt r3, #8192 ; 0x2000 8001dee: 681b ldr r3, [r3, #0] 8001df0: 6c1a ldr r2, [r3, #64] ; 0x40 8001df2: f240 43d4 movw r3, #1236 ; 0x4d4 8001df6: f2c2 0300 movt r3, #8192 ; 0x2000 8001dfa: 601a str r2, [r3, #0] } set_step_events_per_minute(trapezoid_adjusted_rate); 8001dfc: f240 43d4 movw r3, #1236 ; 0x4d4 8001e00: f2c2 0300 movt r3, #8192 ; 0x2000 8001e04: 681b ldr r3, [r3, #0] 8001e06: 4618 mov r0, r3 8001e08: f000 f93a bl 8002080 8001e0c: e029 b.n 8001e62 } } } else { // No accelerations. Make sure we cruise exactly at the nominal rate. if (trapezoid_adjusted_rate != current_block->nominal_rate) { 8001e0e: f240 43b0 movw r3, #1200 ; 0x4b0 8001e12: f2c2 0300 movt r3, #8192 ; 0x2000 8001e16: 681b ldr r3, [r3, #0] 8001e18: 6d1a ldr r2, [r3, #80] ; 0x50 8001e1a: f240 43d4 movw r3, #1236 ; 0x4d4 8001e1e: f2c2 0300 movt r3, #8192 ; 0x2000 8001e22: 681b ldr r3, [r3, #0] 8001e24: 429a cmp r2, r3 8001e26: d01c beq.n 8001e62 trapezoid_adjusted_rate = current_block->nominal_rate; 8001e28: f240 43b0 movw r3, #1200 ; 0x4b0 8001e2c: f2c2 0300 movt r3, #8192 ; 0x2000 8001e30: 681b ldr r3, [r3, #0] 8001e32: 6d1a ldr r2, [r3, #80] ; 0x50 8001e34: f240 43d4 movw r3, #1236 ; 0x4d4 8001e38: f2c2 0300 movt r3, #8192 ; 0x2000 8001e3c: 601a str r2, [r3, #0] set_step_events_per_minute(trapezoid_adjusted_rate); 8001e3e: f240 43d4 movw r3, #1236 ; 0x4d4 8001e42: f2c2 0300 movt r3, #8192 ; 0x2000 8001e46: 681b ldr r3, [r3, #0] 8001e48: 4618 mov r0, r3 8001e4a: f000 f919 bl 8002080 8001e4e: e008 b.n 8001e62 } } } else { // If current block is finished, reset pointer current_block = NULL; 8001e50: f240 43b0 movw r3, #1200 ; 0x4b0 8001e54: f2c2 0300 movt r3, #8192 ; 0x2000 8001e58: f04f 0200 mov.w r2, #0 8001e5c: 601a str r2, [r3, #0] plan_discard_current_block(); 8001e5e: f002 fa53 bl 8004308 } } out_bits ^= settings.invert_mask; // Apply stepper invert mask 8001e62: f240 63d8 movw r3, #1752 ; 0x6d8 8001e66: f2c2 0300 movt r3, #8192 ; 0x2000 8001e6a: 8e1b ldrh r3, [r3, #48] ; 0x30 8001e6c: b2da uxtb r2, r3 8001e6e: f240 43b4 movw r3, #1204 ; 0x4b4 8001e72: f2c2 0300 movt r3, #8192 ; 0x2000 8001e76: 781b ldrb r3, [r3, #0] 8001e78: 4053 eors r3, r2 8001e7a: b2da uxtb r2, r3 8001e7c: f240 43b4 movw r3, #1204 ; 0x4b4 8001e80: f2c2 0300 movt r3, #8192 ; 0x2000 8001e84: 701a strb r2, [r3, #0] busy=false; 8001e86: f240 43c8 movw r3, #1224 ; 0x4c8 8001e8a: f2c2 0300 movt r3, #8192 ; 0x2000 8001e8e: f04f 0200 mov.w r2, #0 8001e92: 701a strb r2, [r3, #0] 8001e94: e002 b.n 8001e9c // config_step_timer. It pops blocks from the block_buffer and executes them by pulsing the stepper pins appropriately. // It is supported by The Stepper Port Reset Interrupt which it uses to reset the stepper port after each pulse. // The bresenham line tracer algorithm controls all three stepper outputs simultaneously with these two interrupts. void TIM2_IRQHandler(void) { if (TIM_GetITStatus(TIM2, TIM_IT_Update) == RESET) return; 8001e96: bf00 nop 8001e98: e000 b.n 8001e9c TIM_ClearITPendingBit(TIM2, TIM_IT_Update); if (busy) { return; } // The busy-flag is used to avoid reentering this interrupt 8001e9a: bf00 nop plan_discard_current_block(); } } out_bits ^= settings.invert_mask; // Apply stepper invert mask busy=false; } 8001e9c: bd80 pop {r7, pc} 8001e9e: bf00 nop 08001ea0 : TCCR2B = 0; // Disable Timer2 to prevent re-entering this interrupt when it's not needed. }*/ // Initialize and start the stepper motor subsystem void st_init() { 8001ea0: b580 push {r7, lr} 8001ea2: b082 sub sp, #8 8001ea4: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStructure; GPIO_InitStructure.GPIO_Pin = X_STEP_BIT | Y_STEP_BIT | Z_STEP_BIT | X_DIRECTION_BIT | Y_DIRECTION_BIT | Y_DIRECTION_BIT; 8001ea6: f04f 037c mov.w r3, #124 ; 0x7c 8001eaa: 603b str r3, [r7, #0] GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; 8001eac: f04f 0301 mov.w r3, #1 8001eb0: 713b strb r3, [r7, #4] GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; 8001eb2: f04f 0300 mov.w r3, #0 8001eb6: 71bb strb r3, [r7, #6] GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; 8001eb8: f04f 0303 mov.w r3, #3 8001ebc: 717b strb r3, [r7, #5] GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; 8001ebe: f04f 0302 mov.w r3, #2 8001ec2: 71fb strb r3, [r7, #7] GPIO_Init(STEPPING_PORT, &GPIO_InitStructure); 8001ec4: 463b mov r3, r7 8001ec6: f44f 6000 mov.w r0, #2048 ; 0x800 8001eca: f2c4 0002 movt r0, #16386 ; 0x4002 8001ece: 4619 mov r1, r3 8001ed0: f000 fe0c bl 8002aec // Configure Timer 2 TCCR2A = 0; // Normal operation TCCR2B = 0; // Disable timer until needed. TIMSK2 |= (1< trapezoid_tick_cycle_counter = 0; 8001edc: f240 43d0 movw r3, #1232 ; 0x4d0 8001ee0: f2c2 0300 movt r3, #8192 ; 0x2000 8001ee4: f04f 0200 mov.w r2, #0 8001ee8: 601a str r2, [r3, #0] current_block = NULL; 8001eea: f240 43b0 movw r3, #1200 ; 0x4b0 8001eee: f2c2 0300 movt r3, #8192 ; 0x2000 8001ef2: f04f 0200 mov.w r2, #0 8001ef6: 601a str r2, [r3, #0] busy = false; 8001ef8: f240 43c8 movw r3, #1224 ; 0x4c8 8001efc: f2c2 0300 movt r3, #8192 ; 0x2000 8001f00: f04f 0200 mov.w r2, #0 8001f04: 701a strb r2, [r3, #0] // Start in the idle state st_go_idle(); 8001f06: f7ff fcdf bl 80018c8 } 8001f0a: f107 0708 add.w r7, r7, #8 8001f0e: 46bd mov sp, r7 8001f10: bd80 pop {r7, pc} 8001f12: bf00 nop 08001f14 : // Block until all buffered steps are executed void st_synchronize() { 8001f14: b580 push {r7, lr} 8001f16: af00 add r7, sp, #0 while(plan_get_current_block()) { sleep_mode(); } 8001f18: e001 b.n 8001f1e 8001f1a: f000 fde1 bl 8002ae0 8001f1e: f002 fa15 bl 800434c 8001f22: 4603 mov r3, r0 8001f24: 2b00 cmp r3, #0 8001f26: d1f8 bne.n 8001f1a } 8001f28: bd80 pop {r7, pc} 8001f2a: bf00 nop 08001f2c : // Configures the prescaler and ceiling of timer 1 to produce the given rate as accurately as possible. // Returns the actual number of cycles per interrupt static uint64_t config_step_timer(uint64_t cycles) { 8001f2c: b580 push {r7, lr} 8001f2e: b086 sub sp, #24 8001f30: af00 add r7, sp, #0 8001f32: e9c7 0100 strd r0, r1, [r7] uint64_t ceiling; uint16_t prescaler; if(cycles <= (uint64_t) 1<<32) 8001f36: e9d7 2300 ldrd r2, r3, [r7] 8001f3a: f04f 0000 mov.w r0, #0 8001f3e: f04f 0101 mov.w r1, #1 8001f42: 4290 cmp r0, r2 8001f44: eb71 0c03 sbcs.w ip, r1, r3 8001f48: d307 bcc.n 8001f5a { ceiling = cycles; 8001f4a: e9d7 2300 ldrd r2, r3, [r7] 8001f4e: e9c7 2304 strd r2, r3, [r7, #16] prescaler = 0; 8001f52: f04f 0300 mov.w r3, #0 8001f56: 81fb strh r3, [r7, #14] 8001f58: e022 b.n 8001fa0 } else if((uint64_t )cycles <= (uint64_t )1<<47){ 8001f5a: e9d7 2300 ldrd r2, r3, [r7] 8001f5e: f04f 0000 mov.w r0, #0 8001f62: f44f 4100 mov.w r1, #32768 ; 0x8000 8001f66: 4290 cmp r0, r2 8001f68: eb71 0c03 sbcs.w ip, r1, r3 8001f6c: d30f bcc.n 8001f8e ceiling= cycles >> 16; 8001f6e: 687b ldr r3, [r7, #4] 8001f70: ea4f 4303 mov.w r3, r3, lsl #16 8001f74: 683a ldr r2, [r7, #0] 8001f76: ea4f 4212 mov.w r2, r2, lsr #16 8001f7a: 4313 orrs r3, r2 8001f7c: 613b str r3, [r7, #16] 8001f7e: 687b ldr r3, [r7, #4] 8001f80: ea4f 4313 mov.w r3, r3, lsr #16 8001f84: 617b str r3, [r7, #20] prescaler = 0xFFFF;//1 << 16; 8001f86: f64f 73ff movw r3, #65535 ; 0xffff 8001f8a: 81fb strh r3, [r7, #14] 8001f8c: e008 b.n 8001fa0 }else{ ceiling=0xFFFFFFFF;//((1<<32) -1); 8001f8e: f04f 32ff mov.w r2, #4294967295 8001f92: f04f 0300 mov.w r3, #0 8001f96: e9c7 2304 strd r2, r3, [r7, #16] prescaler=0xFFFF;//(1<<16) -1; 8001f9a: f64f 73ff movw r3, #65535 ; 0xffff 8001f9e: 81fb strh r3, [r7, #14] } // Set prescaler INTTIM2_Config(ceiling, prescaler); 8001fa0: 693a ldr r2, [r7, #16] 8001fa2: 89fb ldrh r3, [r7, #14] 8001fa4: 4610 mov r0, r2 8001fa6: 4619 mov r1, r3 8001fa8: f000 f81c bl 8001fe4 if(prescaler == 0) prescaler=1; //otherwise the multiplication below would not work 8001fac: 89fb ldrh r3, [r7, #14] 8001fae: 2b00 cmp r3, #0 8001fb0: d102 bne.n 8001fb8 8001fb2: f04f 0301 mov.w r3, #1 8001fb6: 81fb strh r3, [r7, #14] return(ceiling * prescaler); 8001fb8: 89fa ldrh r2, [r7, #14] 8001fba: f04f 0300 mov.w r3, #0 8001fbe: 6939 ldr r1, [r7, #16] 8001fc0: fb03 f001 mul.w r0, r3, r1 8001fc4: 6979 ldr r1, [r7, #20] 8001fc6: fb02 f101 mul.w r1, r2, r1 8001fca: 1841 adds r1, r0, r1 8001fcc: 6938 ldr r0, [r7, #16] 8001fce: fba0 2302 umull r2, r3, r0, r2 8001fd2: 18c9 adds r1, r1, r3 8001fd4: 460b mov r3, r1 } 8001fd6: 4610 mov r0, r2 8001fd8: 4619 mov r1, r3 8001fda: f107 0718 add.w r7, r7, #24 8001fde: 46bd mov sp, r7 8001fe0: bd80 pop {r7, pc} 8001fe2: bf00 nop 08001fe4 : void INTTIM2_Config(uint32_t ceiling, uint16_t prescaler) { 8001fe4: b580 push {r7, lr} 8001fe6: b086 sub sp, #24 8001fe8: af00 add r7, sp, #0 8001fea: 6078 str r0, [r7, #4] 8001fec: 460b mov r3, r1 8001fee: 807b strh r3, [r7, #2] NVIC_InitTypeDef NVIC_InitStructure; /* Enable the TIM2 gloabal Interrupt */ NVIC_InitStructure.NVIC_IRQChannel = TIM2_IRQn; 8001ff0: f04f 031c mov.w r3, #28 8001ff4: 753b strb r3, [r7, #20] NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; 8001ff6: f04f 0300 mov.w r3, #0 8001ffa: 757b strb r3, [r7, #21] NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1; 8001ffc: f04f 0301 mov.w r3, #1 8002000: 75bb strb r3, [r7, #22] NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; 8002002: f04f 0301 mov.w r3, #1 8002006: 75fb strb r3, [r7, #23] NVIC_Init(&NVIC_InitStructure); 8002008: f107 0314 add.w r3, r7, #20 800200c: 4618 mov r0, r3 800200e: f002 fe3b bl 8004c88 /* TIM2 clock enable */ RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE); 8002012: f04f 0001 mov.w r0, #1 8002016: f04f 0101 mov.w r1, #1 800201a: f000 fa7d bl 8002518 /* Time base configuration */ //TODO zeit pruefen !!!! TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; TIM_TimeBaseStructure.TIM_Period = ceiling; 800201e: 687b ldr r3, [r7, #4] 8002020: 60fb str r3, [r7, #12] TIM_TimeBaseStructure.TIM_Prescaler = prescaler; 8002022: 887b ldrh r3, [r7, #2] 8002024: 813b strh r3, [r7, #8] TIM_TimeBaseStructure.TIM_ClockDivision = 0; 8002026: f04f 0300 mov.w r3, #0 800202a: 823b strh r3, [r7, #16] TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; 800202c: f04f 0300 mov.w r3, #0 8002030: 817b strh r3, [r7, #10] TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure); 8002032: f107 0308 add.w r3, r7, #8 8002036: f04f 4080 mov.w r0, #1073741824 ; 0x40000000 800203a: 4619 mov r1, r3 800203c: f003 f968 bl 8005310 /* TIM IT enable */ //TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE); /* TIM2 enable counter */ TIM_ClearFlag(TIM2, TIM_FLAG_Update); //Interrupt Flag von TIM2 löschen 8002040: f04f 4080 mov.w r0, #1073741824 ; 0x40000000 8002044: f04f 0101 mov.w r1, #1 8002048: f003 fa5a bl 8005500 TIM_ITConfig(TIM2, TIM_IT_Update, ENABLE); //Interrupt für TIM2 Aktivieren 800204c: f04f 4080 mov.w r0, #1073741824 ; 0x40000000 8002050: f04f 0101 mov.w r1, #1 8002054: f04f 0201 mov.w r2, #1 8002058: f003 fa2e bl 80054b8 TIM_ClearFlag(TIM2, TIM_FLAG_Update); //Interrupt Flag für TIM2 Löschen 800205c: f04f 4080 mov.w r0, #1073741824 ; 0x40000000 8002060: f04f 0101 mov.w r1, #1 8002064: f003 fa4c bl 8005500 TIM_Cmd(TIM2, ENABLE); 8002068: f04f 4080 mov.w r0, #1073741824 ; 0x40000000 800206c: f04f 0101 mov.w r1, #1 8002070: f003 f9f4 bl 800545c } 8002074: f107 0718 add.w r7, r7, #24 8002078: 46bd mov sp, r7 800207a: bd80 pop {r7, pc} 800207c: 0000 movs r0, r0 ... 08002080 : /* TIM IT enable */ TIM_ITConfig(TIM1, TIM_IT_CC1, ENABLE); } static void set_step_events_per_minute(uint32_t steps_per_minute) { 8002080: b580 push {r7, lr} 8002082: b082 sub sp, #8 8002084: af00 add r7, sp, #0 8002086: 6078 str r0, [r7, #4] if (steps_per_minute < MINIMUM_STEPS_PER_MINUTE) { steps_per_minute = MINIMUM_STEPS_PER_MINUTE; } 8002088: 687a ldr r2, [r7, #4] 800208a: f240 331f movw r3, #799 ; 0x31f 800208e: 429a cmp r2, r3 8002090: d802 bhi.n 8002098 8002092: f44f 7348 mov.w r3, #800 ; 0x320 8002096: 607b str r3, [r7, #4] cycles_per_step_event = config_step_timer(((uint64_t)TICKS_PER_MICROSECOND*1000000*60)/(uint64_t)steps_per_minute); 8002098: 6879 ldr r1, [r7, #4] 800209a: 460a mov r2, r1 800209c: f04f 0300 mov.w r3, #0 80020a0: a10b add r1, pc, #44 ; (adr r1, 80020d0 ) 80020a2: e9d1 0100 ldrd r0, r1, [r1] 80020a6: f007 f8cd bl 8009244 <__aeabi_uldivmod> 80020aa: 4602 mov r2, r0 80020ac: 460b mov r3, r1 80020ae: 4610 mov r0, r2 80020b0: 4619 mov r1, r3 80020b2: f7ff ff3b bl 8001f2c 80020b6: 4602 mov r2, r0 80020b8: 460b mov r3, r1 80020ba: f240 43cc movw r3, #1228 ; 0x4cc 80020be: f2c2 0300 movt r3, #8192 ; 0x2000 80020c2: 601a str r2, [r3, #0] } 80020c4: f107 0708 add.w r7, r7, #8 80020c8: 46bd mov sp, r7 80020ca: bd80 pop {r7, pc} 80020cc: f3af 8000 nop.w 80020d0: 58d09800 .word 0x58d09800 80020d4: 00000002 .word 0x00000002 080020d8 : void st_go_home() { 80020d8: b580 push {r7, lr} 80020da: b082 sub sp, #8 80020dc: af02 add r7, sp, #8 limits_go_home(); 80020de: f003 f867 bl 80051b0 plan_set_current_position(0,0,0); 80020e2: a307 add r3, pc, #28 ; (adr r3, 8002100 ) 80020e4: e9d3 2300 ldrd r2, r3, [r3] 80020e8: e9cd 2300 strd r2, r3, [sp] 80020ec: a104 add r1, pc, #16 ; (adr r1, 8002100 ) 80020ee: e9d1 0100 ldrd r0, r1, [r1] 80020f2: a303 add r3, pc, #12 ; (adr r3, 8002100 ) 80020f4: e9d3 2300 ldrd r2, r3, [r3] 80020f8: f002 fd2e bl 8004b58 } 80020fc: 46bd mov sp, r7 80020fe: bd80 pop {r7, pc} ... 08002108 : // Planner external interface to start stepper interrupt and execute the blocks in queue. void st_cycle_start() { 8002108: b580 push {r7, lr} 800210a: af00 add r7, sp, #0 if (!cycle_start) { 800210c: f240 43dc movw r3, #1244 ; 0x4dc 8002110: f2c2 0300 movt r3, #8192 ; 0x2000 8002114: 781b ldrb r3, [r3, #0] 8002116: 2b00 cmp r3, #0 8002118: d108 bne.n 800212c cycle_start = true; 800211a: f240 43dc movw r3, #1244 ; 0x4dc 800211e: f2c2 0300 movt r3, #8192 ; 0x2000 8002122: f04f 0201 mov.w r2, #1 8002126: 701a strb r2, [r3, #0] st_wake_up(); 8002128: f7ff fbb0 bl 800188c } } 800212c: bd80 pop {r7, pc} 800212e: bf00 nop 08002130 : * supplied main() routine is called. * @param None * @retval None */ void Default_Reset_Handler(void) { 8002130: b580 push {r7, lr} 8002132: b082 sub sp, #8 8002134: af00 add r7, sp, #0 /* Initialize data and bss */ unsigned long *pulSrc, *pulDest; /* Copy the data segment initializers from flash to SRAM */ pulSrc = &_sidata; 8002136: f24b 03e8 movw r3, #45288 ; 0xb0e8 800213a: f6c0 0300 movt r3, #2048 ; 0x800 800213e: 607b str r3, [r7, #4] for(pulDest = &_sdata; pulDest < &_edata; ) 8002140: f240 0300 movw r3, #0 8002144: f2c2 0300 movt r3, #8192 ; 0x2000 8002148: 603b str r3, [r7, #0] 800214a: e00b b.n 8002164 { *(pulDest++) = *(pulSrc++); 800214c: 687b ldr r3, [r7, #4] 800214e: 681a ldr r2, [r3, #0] 8002150: 683b ldr r3, [r7, #0] 8002152: 601a str r2, [r3, #0] 8002154: 683b ldr r3, [r7, #0] 8002156: f103 0304 add.w r3, r3, #4 800215a: 603b str r3, [r7, #0] 800215c: 687b ldr r3, [r7, #4] 800215e: f103 0304 add.w r3, r3, #4 8002162: 607b str r3, [r7, #4] unsigned long *pulSrc, *pulDest; /* Copy the data segment initializers from flash to SRAM */ pulSrc = &_sidata; for(pulDest = &_sdata; pulDest < &_edata; ) 8002164: 683a ldr r2, [r7, #0] 8002166: f240 4340 movw r3, #1088 ; 0x440 800216a: f2c2 0300 movt r3, #8192 ; 0x2000 800216e: 429a cmp r2, r3 8002170: d3ec bcc.n 800214c *(pulDest++) = *(pulSrc++); } /* Zero fill the bss segment. This is done with inline assembly since this will clear the value of pulDest if it is not kept in a register. */ __asm(" ldr r0, =_sbss\n" 8002172: 4807 ldr r0, [pc, #28] ; (8002190 ) 8002174: 4907 ldr r1, [pc, #28] ; (8002194 ) 8002176: f04f 0200 mov.w r2, #0 0800217a : 800217a: 4288 cmp r0, r1 800217c: bfb8 it lt 800217e: f840 2b04 strlt.w r2, [r0], #4 8002182: dbfa blt.n 800217a " it lt\n" " strlt r2, [r0], #4\n" " blt zero_loop"); /* Call the application's entry point.*/ main(); 8002184: f000 f89c bl 80022c0
} 8002188: f107 0708 add.w r7, r7, #8 800218c: 46bd mov sp, r7 800218e: bd80 pop {r7, pc} 8002190: 20000440 .word 0x20000440 8002194: 2000077c .word 0x2000077c 08002198 : * preserving the system state for examination by a debugger. * @param None * @retval None */ static void Default_Handler(void) { 8002198: b480 push {r7} 800219a: af00 add r7, sp, #0 /* Go into an infinite loop. */ while (1) { } 800219c: e7fe b.n 800219c 800219e: bf00 nop 080021a0 <_exit>: char *__env[1] = { 0 }; char **environ = __env; int _write(int file, char *ptr, int len); void _exit(int status) { 80021a0: b580 push {r7, lr} 80021a2: b082 sub sp, #8 80021a4: af00 add r7, sp, #0 80021a6: 6078 str r0, [r7, #4] _write(1, "exit", 4); 80021a8: f04f 0001 mov.w r0, #1 80021ac: f64a 311c movw r1, #43804 ; 0xab1c 80021b0: f6c0 0100 movt r1, #2048 ; 0x800 80021b4: f04f 0204 mov.w r2, #4 80021b8: f000 f81e bl 80021f8 <_write> while (1) { ; } 80021bc: e7fe b.n 80021bc <_exit+0x1c> 80021be: bf00 nop 080021c0 <_getpid>: /* getpid Process-ID; this is sometimes used to generate strings unlikely to conflict with other processes. Minimal implementation, for a system without processes: */ int _getpid() { 80021c0: b480 push {r7} 80021c2: af00 add r7, sp, #0 return 1; 80021c4: f04f 0301 mov.w r3, #1 } 80021c8: 4618 mov r0, r3 80021ca: 46bd mov sp, r7 80021cc: bc80 pop {r7} 80021ce: 4770 bx lr 080021d0 <_kill>: /* kill Send a signal. Minimal implementation: */ int _kill(int pid, int sig) { 80021d0: b480 push {r7} 80021d2: b083 sub sp, #12 80021d4: af00 add r7, sp, #0 80021d6: 6078 str r0, [r7, #4] 80021d8: 6039 str r1, [r7, #0] errno = EINVAL; 80021da: f240 7378 movw r3, #1912 ; 0x778 80021de: f2c2 0300 movt r3, #8192 ; 0x2000 80021e2: f04f 0216 mov.w r2, #22 80021e6: 601a str r2, [r3, #0] return (-1); 80021e8: f04f 33ff mov.w r3, #4294967295 } 80021ec: 4618 mov r0, r3 80021ee: f107 070c add.w r7, r7, #12 80021f2: 46bd mov sp, r7 80021f4: bc80 pop {r7} 80021f6: 4770 bx lr 080021f8 <_write>: /* write Write a character to a file. `libc' subroutines will use this system routine for output to all files, including stdout Returns -1 on error or number of bytes sent */ int _write(int file, char *ptr, int len) { 80021f8: b480 push {r7} 80021fa: b087 sub sp, #28 80021fc: af00 add r7, sp, #0 80021fe: 60f8 str r0, [r7, #12] 8002200: 60b9 str r1, [r7, #8] 8002202: 607a str r2, [r7, #4] int n; switch (file) { 8002204: 68fb ldr r3, [r7, #12] 8002206: 2b01 cmp r3, #1 8002208: d002 beq.n 8002210 <_write+0x18> 800220a: 2b02 cmp r3, #2 800220c: d023 beq.n 8002256 <_write+0x5e> 800220e: e045 b.n 800229c <_write+0xa4> case STDOUT_FILENO: /*stdout*/ for (n = 0; n < len; n++) { 8002210: f04f 0300 mov.w r3, #0 8002214: 617b str r3, [r7, #20] 8002216: e019 b.n 800224c <_write+0x54> #if STDOUT_USART == 1 while ((USART1->SR & USART_FLAG_TC) == (uint16_t)RESET) {} USART1->DR = (*ptr++ & (uint16_t)0x01FF); #elif STDOUT_USART == 2 while ((USART2->SR & USART_FLAG_TC) == (uint16_t) RESET) { 8002218: bf00 nop 800221a: f44f 4388 mov.w r3, #17408 ; 0x4400 800221e: f2c4 0300 movt r3, #16384 ; 0x4000 8002222: 881b ldrh r3, [r3, #0] 8002224: b29b uxth r3, r3 8002226: f003 0340 and.w r3, r3, #64 ; 0x40 800222a: 2b00 cmp r3, #0 800222c: d0f5 beq.n 800221a <_write+0x22> } USART2->DR = (*ptr++ & (uint16_t) 0x01FF); 800222e: f44f 4388 mov.w r3, #17408 ; 0x4400 8002232: f2c4 0300 movt r3, #16384 ; 0x4000 8002236: 68ba ldr r2, [r7, #8] 8002238: 7812 ldrb r2, [r2, #0] 800223a: 809a strh r2, [r3, #4] 800223c: 68bb ldr r3, [r7, #8] 800223e: f103 0301 add.w r3, r3, #1 8002242: 60bb str r3, [r7, #8] */ int _write(int file, char *ptr, int len) { int n; switch (file) { case STDOUT_FILENO: /*stdout*/ for (n = 0; n < len; n++) { 8002244: 697b ldr r3, [r7, #20] 8002246: f103 0301 add.w r3, r3, #1 800224a: 617b str r3, [r7, #20] 800224c: 697a ldr r2, [r7, #20] 800224e: 687b ldr r3, [r7, #4] 8002250: 429a cmp r2, r3 8002252: dbe1 blt.n 8002218 <_write+0x20> #elif STDOUT_USART == 3 while ((USART3->SR & USART_FLAG_TC) == (uint16_t)RESET) {} USART3->DR = (*ptr++ & (uint16_t)0x01FF); #endif } break; 8002254: e02c b.n 80022b0 <_write+0xb8> case STDERR_FILENO: /* stderr */ for (n = 0; n < len; n++) { 8002256: f04f 0300 mov.w r3, #0 800225a: 617b str r3, [r7, #20] 800225c: e019 b.n 8002292 <_write+0x9a> #if STDERR_USART == 1 while ((USART1->SR & USART_FLAG_TC) == (uint16_t)RESET) {} USART1->DR = (*ptr++ & (uint16_t)0x01FF); #elif STDERR_USART == 2 while ((USART2->SR & USART_FLAG_TC) == (uint16_t) RESET) { 800225e: bf00 nop 8002260: f44f 4388 mov.w r3, #17408 ; 0x4400 8002264: f2c4 0300 movt r3, #16384 ; 0x4000 8002268: 881b ldrh r3, [r3, #0] 800226a: b29b uxth r3, r3 800226c: f003 0340 and.w r3, r3, #64 ; 0x40 8002270: 2b00 cmp r3, #0 8002272: d0f5 beq.n 8002260 <_write+0x68> } USART2->DR = (*ptr++ & (uint16_t) 0x01FF); 8002274: f44f 4388 mov.w r3, #17408 ; 0x4400 8002278: f2c4 0300 movt r3, #16384 ; 0x4000 800227c: 68ba ldr r2, [r7, #8] 800227e: 7812 ldrb r2, [r2, #0] 8002280: 809a strh r2, [r3, #4] 8002282: 68bb ldr r3, [r7, #8] 8002284: f103 0301 add.w r3, r3, #1 8002288: 60bb str r3, [r7, #8] USART3->DR = (*ptr++ & (uint16_t)0x01FF); #endif } break; case STDERR_FILENO: /* stderr */ for (n = 0; n < len; n++) { 800228a: 697b ldr r3, [r7, #20] 800228c: f103 0301 add.w r3, r3, #1 8002290: 617b str r3, [r7, #20] 8002292: 697a ldr r2, [r7, #20] 8002294: 687b ldr r3, [r7, #4] 8002296: 429a cmp r2, r3 8002298: dbe1 blt.n 800225e <_write+0x66> #elif STDERR_USART == 3 while ((USART3->SR & USART_FLAG_TC) == (uint16_t)RESET) {} USART3->DR = (*ptr++ & (uint16_t)0x01FF); #endif } break; 800229a: e009 b.n 80022b0 <_write+0xb8> default: errno = EBADF; 800229c: f240 7378 movw r3, #1912 ; 0x778 80022a0: f2c2 0300 movt r3, #8192 ; 0x2000 80022a4: f04f 0209 mov.w r2, #9 80022a8: 601a str r2, [r3, #0] return -1; 80022aa: f04f 33ff mov.w r3, #4294967295 80022ae: e000 b.n 80022b2 <_write+0xba> } return len; 80022b0: 687b ldr r3, [r7, #4] } 80022b2: 4618 mov r0, r3 80022b4: f107 071c add.w r7, r7, #28 80022b8: 46bd mov sp, r7 80022ba: bc80 pop {r7} 80022bc: 4770 bx lr 80022be: bf00 nop 080022c0
: #include "settings.h" #include "serial.h" int main(void) { 80022c0: b580 push {r7, lr} 80022c2: af00 add r7, sp, #0 //sei(); // Enable interrupts serial_init(BAUD_RATE); 80022c4: f44f 5016 mov.w r0, #9600 ; 0x2580 80022c8: f002 fd50 bl 8004d6c protocol_init(); 80022cc: f7fd ffaa bl 8000224 settings_init(); 80022d0: f001 fb86 bl 80039e0 plan_init(); 80022d4: f001 ffc0 bl 8004258 st_init(); 80022d8: f7ff fde2 bl 8001ea0 spindle_init(); 80022dc: f002 ffb2 bl 8005244 gc_init(); 80022e0: f7fe fb62 bl 80009a8 limits_init(); 80022e4: f002 fe8e bl 8005004 while (1) { // sleep_mode(); // Wait for it ... protocol_process(); // ... process the serial protocol 80022e8: f7fd ffd0 bl 800028c } 80022ec: e7fc b.n 80022e8 80022ee: bf00 nop 080022f0 : * configuration based on this function will be incorrect. * * @retval None */ void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) { 80022f0: b480 push {r7} 80022f2: b089 sub sp, #36 ; 0x24 80022f4: af00 add r7, sp, #0 80022f6: 6078 str r0, [r7, #4] uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; 80022f8: f04f 0300 mov.w r3, #0 80022fc: 61bb str r3, [r7, #24] 80022fe: f04f 0300 mov.w r3, #0 8002302: 617b str r3, [r7, #20] 8002304: f04f 0300 mov.w r3, #0 8002308: 61fb str r3, [r7, #28] 800230a: f04f 0302 mov.w r3, #2 800230e: 613b str r3, [r7, #16] 8002310: f04f 0300 mov.w r3, #0 8002314: 60fb str r3, [r7, #12] 8002316: f04f 0302 mov.w r3, #2 800231a: 60bb str r3, [r7, #8] /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; 800231c: f44f 5360 mov.w r3, #14336 ; 0x3800 8002320: f2c4 0302 movt r3, #16386 ; 0x4002 8002324: 689b ldr r3, [r3, #8] 8002326: f003 030c and.w r3, r3, #12 800232a: 61bb str r3, [r7, #24] switch (tmp) 800232c: 69bb ldr r3, [r7, #24] 800232e: 2b04 cmp r3, #4 8002330: d00a beq.n 8002348 8002332: 2b08 cmp r3, #8 8002334: d00f beq.n 8002356 8002336: 2b00 cmp r3, #0 8002338: d162 bne.n 8002400 { case 0x00: /* HSI used as system clock source */ RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; 800233a: 687a ldr r2, [r7, #4] 800233c: f44f 5310 mov.w r3, #9216 ; 0x2400 8002340: f2c0 03f4 movt r3, #244 ; 0xf4 8002344: 6013 str r3, [r2, #0] break; 8002346: e062 b.n 800240e case 0x04: /* HSE used as system clock source */ RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; 8002348: 687a ldr r2, [r7, #4] 800234a: f44f 5390 mov.w r3, #4608 ; 0x1200 800234e: f2c0 037a movt r3, #122 ; 0x7a 8002352: 6013 str r3, [r2, #0] break; 8002354: e05b b.n 800240e case 0x08: /* PLL used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN SYSCLK = PLL_VCO / PLLP */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; 8002356: f44f 5360 mov.w r3, #14336 ; 0x3800 800235a: f2c4 0302 movt r3, #16386 ; 0x4002 800235e: 685b ldr r3, [r3, #4] 8002360: f403 0380 and.w r3, r3, #4194304 ; 0x400000 8002364: ea4f 5393 mov.w r3, r3, lsr #22 8002368: 60fb str r3, [r7, #12] pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; 800236a: f44f 5360 mov.w r3, #14336 ; 0x3800 800236e: f2c4 0302 movt r3, #16386 ; 0x4002 8002372: 685b ldr r3, [r3, #4] 8002374: f003 033f and.w r3, r3, #63 ; 0x3f 8002378: 60bb str r3, [r7, #8] if (pllsource != 0) 800237a: 68fb ldr r3, [r7, #12] 800237c: 2b00 cmp r3, #0 800237e: d015 beq.n 80023ac { /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); 8002380: f44f 5390 mov.w r3, #4608 ; 0x1200 8002384: f2c0 037a movt r3, #122 ; 0x7a 8002388: 68ba ldr r2, [r7, #8] 800238a: fbb3 f2f2 udiv r2, r3, r2 800238e: f44f 5360 mov.w r3, #14336 ; 0x3800 8002392: f2c4 0302 movt r3, #16386 ; 0x4002 8002396: 685b ldr r3, [r3, #4] 8002398: 4619 mov r1, r3 800239a: f647 73c0 movw r3, #32704 ; 0x7fc0 800239e: 400b ands r3, r1 80023a0: ea4f 1393 mov.w r3, r3, lsr #6 80023a4: fb03 f302 mul.w r3, r3, r2 80023a8: 61fb str r3, [r7, #28] 80023aa: e014 b.n 80023d6 } else { /* HSI used as PLL clock source */ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); 80023ac: f44f 5310 mov.w r3, #9216 ; 0x2400 80023b0: f2c0 03f4 movt r3, #244 ; 0xf4 80023b4: 68ba ldr r2, [r7, #8] 80023b6: fbb3 f2f2 udiv r2, r3, r2 80023ba: f44f 5360 mov.w r3, #14336 ; 0x3800 80023be: f2c4 0302 movt r3, #16386 ; 0x4002 80023c2: 685b ldr r3, [r3, #4] 80023c4: 4619 mov r1, r3 80023c6: f647 73c0 movw r3, #32704 ; 0x7fc0 80023ca: 400b ands r3, r1 80023cc: ea4f 1393 mov.w r3, r3, lsr #6 80023d0: fb03 f302 mul.w r3, r3, r2 80023d4: 61fb str r3, [r7, #28] } pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; 80023d6: f44f 5360 mov.w r3, #14336 ; 0x3800 80023da: f2c4 0302 movt r3, #16386 ; 0x4002 80023de: 685b ldr r3, [r3, #4] 80023e0: f403 3340 and.w r3, r3, #196608 ; 0x30000 80023e4: ea4f 4313 mov.w r3, r3, lsr #16 80023e8: f103 0301 add.w r3, r3, #1 80023ec: ea4f 0343 mov.w r3, r3, lsl #1 80023f0: 613b str r3, [r7, #16] RCC_Clocks->SYSCLK_Frequency = pllvco/pllp; 80023f2: 69fa ldr r2, [r7, #28] 80023f4: 693b ldr r3, [r7, #16] 80023f6: fbb2 f2f3 udiv r2, r2, r3 80023fa: 687b ldr r3, [r7, #4] 80023fc: 601a str r2, [r3, #0] break; 80023fe: e006 b.n 800240e default: RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; 8002400: 687a ldr r2, [r7, #4] 8002402: f44f 5310 mov.w r3, #9216 ; 0x2400 8002406: f2c0 03f4 movt r3, #244 ; 0xf4 800240a: 6013 str r3, [r2, #0] break; 800240c: bf00 nop } /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/ /* Get HCLK prescaler */ tmp = RCC->CFGR & RCC_CFGR_HPRE; 800240e: f44f 5360 mov.w r3, #14336 ; 0x3800 8002412: f2c4 0302 movt r3, #16386 ; 0x4002 8002416: 689b ldr r3, [r3, #8] 8002418: f003 03f0 and.w r3, r3, #240 ; 0xf0 800241c: 61bb str r3, [r7, #24] tmp = tmp >> 4; 800241e: 69bb ldr r3, [r7, #24] 8002420: ea4f 1313 mov.w r3, r3, lsr #4 8002424: 61bb str r3, [r7, #24] presc = APBAHBPrescTable[tmp]; 8002426: f240 0300 movw r3, #0 800242a: f2c2 0300 movt r3, #8192 ; 0x2000 800242e: 69ba ldr r2, [r7, #24] 8002430: 189b adds r3, r3, r2 8002432: 781b ldrb r3, [r3, #0] 8002434: b2db uxtb r3, r3 8002436: 617b str r3, [r7, #20] /* HCLK clock frequency */ RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; 8002438: 687b ldr r3, [r7, #4] 800243a: 681a ldr r2, [r3, #0] 800243c: 697b ldr r3, [r7, #20] 800243e: fa22 f203 lsr.w r2, r2, r3 8002442: 687b ldr r3, [r7, #4] 8002444: 605a str r2, [r3, #4] /* Get PCLK1 prescaler */ tmp = RCC->CFGR & RCC_CFGR_PPRE1; 8002446: f44f 5360 mov.w r3, #14336 ; 0x3800 800244a: f2c4 0302 movt r3, #16386 ; 0x4002 800244e: 689b ldr r3, [r3, #8] 8002450: f403 53e0 and.w r3, r3, #7168 ; 0x1c00 8002454: 61bb str r3, [r7, #24] tmp = tmp >> 10; 8002456: 69bb ldr r3, [r7, #24] 8002458: ea4f 2393 mov.w r3, r3, lsr #10 800245c: 61bb str r3, [r7, #24] presc = APBAHBPrescTable[tmp]; 800245e: f240 0300 movw r3, #0 8002462: f2c2 0300 movt r3, #8192 ; 0x2000 8002466: 69ba ldr r2, [r7, #24] 8002468: 189b adds r3, r3, r2 800246a: 781b ldrb r3, [r3, #0] 800246c: b2db uxtb r3, r3 800246e: 617b str r3, [r7, #20] /* PCLK1 clock frequency */ RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; 8002470: 687b ldr r3, [r7, #4] 8002472: 685a ldr r2, [r3, #4] 8002474: 697b ldr r3, [r7, #20] 8002476: fa22 f203 lsr.w r2, r2, r3 800247a: 687b ldr r3, [r7, #4] 800247c: 609a str r2, [r3, #8] /* Get PCLK2 prescaler */ tmp = RCC->CFGR & RCC_CFGR_PPRE2; 800247e: f44f 5360 mov.w r3, #14336 ; 0x3800 8002482: f2c4 0302 movt r3, #16386 ; 0x4002 8002486: 689b ldr r3, [r3, #8] 8002488: f403 4360 and.w r3, r3, #57344 ; 0xe000 800248c: 61bb str r3, [r7, #24] tmp = tmp >> 13; 800248e: 69bb ldr r3, [r7, #24] 8002490: ea4f 3353 mov.w r3, r3, lsr #13 8002494: 61bb str r3, [r7, #24] presc = APBAHBPrescTable[tmp]; 8002496: f240 0300 movw r3, #0 800249a: f2c2 0300 movt r3, #8192 ; 0x2000 800249e: 69ba ldr r2, [r7, #24] 80024a0: 189b adds r3, r3, r2 80024a2: 781b ldrb r3, [r3, #0] 80024a4: b2db uxtb r3, r3 80024a6: 617b str r3, [r7, #20] /* PCLK2 clock frequency */ RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; 80024a8: 687b ldr r3, [r7, #4] 80024aa: 685a ldr r2, [r3, #4] 80024ac: 697b ldr r3, [r7, #20] 80024ae: fa22 f203 lsr.w r2, r2, r3 80024b2: 687b ldr r3, [r7, #4] 80024b4: 60da str r2, [r3, #12] } 80024b6: f107 0724 add.w r7, r7, #36 ; 0x24 80024ba: 46bd mov sp, r7 80024bc: bc80 pop {r7} 80024be: 4770 bx lr 080024c0 : * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) { 80024c0: b480 push {r7} 80024c2: b083 sub sp, #12 80024c4: af00 add r7, sp, #0 80024c6: 6078 str r0, [r7, #4] 80024c8: 460b mov r3, r1 80024ca: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 80024cc: 78fb ldrb r3, [r7, #3] 80024ce: 2b00 cmp r3, #0 80024d0: d00d beq.n 80024ee { RCC->AHB1ENR |= RCC_AHB1Periph; 80024d2: f44f 5360 mov.w r3, #14336 ; 0x3800 80024d6: f2c4 0302 movt r3, #16386 ; 0x4002 80024da: f44f 5260 mov.w r2, #14336 ; 0x3800 80024de: f2c4 0202 movt r2, #16386 ; 0x4002 80024e2: 6b12 ldr r2, [r2, #48] ; 0x30 80024e4: 4611 mov r1, r2 80024e6: 687a ldr r2, [r7, #4] 80024e8: 430a orrs r2, r1 80024ea: 631a str r2, [r3, #48] ; 0x30 80024ec: e00e b.n 800250c } else { RCC->AHB1ENR &= ~RCC_AHB1Periph; 80024ee: f44f 5360 mov.w r3, #14336 ; 0x3800 80024f2: f2c4 0302 movt r3, #16386 ; 0x4002 80024f6: f44f 5260 mov.w r2, #14336 ; 0x3800 80024fa: f2c4 0202 movt r2, #16386 ; 0x4002 80024fe: 6b12 ldr r2, [r2, #48] ; 0x30 8002500: 4611 mov r1, r2 8002502: 687a ldr r2, [r7, #4] 8002504: ea6f 0202 mvn.w r2, r2 8002508: 400a ands r2, r1 800250a: 631a str r2, [r3, #48] ; 0x30 } } 800250c: f107 070c add.w r7, r7, #12 8002510: 46bd mov sp, r7 8002512: bc80 pop {r7} 8002514: 4770 bx lr 8002516: bf00 nop 08002518 : * @param NewState: new state of the specified peripheral clock. * This parameter can be: ENABLE or DISABLE. * @retval None */ void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) { 8002518: b480 push {r7} 800251a: b083 sub sp, #12 800251c: af00 add r7, sp, #0 800251e: 6078 str r0, [r7, #4] 8002520: 460b mov r3, r1 8002522: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 8002524: 78fb ldrb r3, [r7, #3] 8002526: 2b00 cmp r3, #0 8002528: d00d beq.n 8002546 { RCC->APB1ENR |= RCC_APB1Periph; 800252a: f44f 5360 mov.w r3, #14336 ; 0x3800 800252e: f2c4 0302 movt r3, #16386 ; 0x4002 8002532: f44f 5260 mov.w r2, #14336 ; 0x3800 8002536: f2c4 0202 movt r2, #16386 ; 0x4002 800253a: 6c12 ldr r2, [r2, #64] ; 0x40 800253c: 4611 mov r1, r2 800253e: 687a ldr r2, [r7, #4] 8002540: 430a orrs r2, r1 8002542: 641a str r2, [r3, #64] ; 0x40 8002544: e00e b.n 8002564 } else { RCC->APB1ENR &= ~RCC_APB1Periph; 8002546: f44f 5360 mov.w r3, #14336 ; 0x3800 800254a: f2c4 0302 movt r3, #16386 ; 0x4002 800254e: f44f 5260 mov.w r2, #14336 ; 0x3800 8002552: f2c4 0202 movt r2, #16386 ; 0x4002 8002556: 6c12 ldr r2, [r2, #64] ; 0x40 8002558: 4611 mov r1, r2 800255a: 687a ldr r2, [r7, #4] 800255c: ea6f 0202 mvn.w r2, r2 8002560: 400a ands r2, r1 8002562: 641a str r2, [r3, #64] ; 0x40 } } 8002564: f107 070c add.w r7, r7, #12 8002568: 46bd mov sp, r7 800256a: bc80 pop {r7} 800256c: 4770 bx lr 800256e: bf00 nop 08002570 : * @brief This function handles NMI exception. * @param None * @retval None */ void NMI_Handler(void) { 8002570: b480 push {r7} 8002572: af00 add r7, sp, #0 } 8002574: 46bd mov sp, r7 8002576: bc80 pop {r7} 8002578: 4770 bx lr 800257a: bf00 nop 0800257c : * @brief This function handles Hard Fault exception. * @param None * @retval None */ void HardFault_Handler(void) { 800257c: b480 push {r7} 800257e: af00 add r7, sp, #0 /* Go to infinite loop when Hard Fault exception occurs */ while (1) { } 8002580: e7fe b.n 8002580 8002582: bf00 nop 08002584 : * @brief This function handles Memory Manage exception. * @param None * @retval None */ void MemManage_Handler(void) { 8002584: b480 push {r7} 8002586: af00 add r7, sp, #0 /* Go to infinite loop when Memory Manage exception occurs */ while (1) { } 8002588: e7fe b.n 8002588 800258a: bf00 nop 0800258c : * @brief This function handles Bus Fault exception. * @param None * @retval None */ void BusFault_Handler(void) { 800258c: b480 push {r7} 800258e: af00 add r7, sp, #0 /* Go to infinite loop when Bus Fault exception occurs */ while (1) { } 8002590: e7fe b.n 8002590 8002592: bf00 nop 08002594 : * @brief This function handles Usage Fault exception. * @param None * @retval None */ void UsageFault_Handler(void) { 8002594: b480 push {r7} 8002596: af00 add r7, sp, #0 /* Go to infinite loop when Usage Fault exception occurs */ while (1) { } 8002598: e7fe b.n 8002598 800259a: bf00 nop 0800259c : * @brief This function handles SVCall exception. * @param None * @retval None */ void SVC_Handler(void) { 800259c: b480 push {r7} 800259e: af00 add r7, sp, #0 } 80025a0: 46bd mov sp, r7 80025a2: bc80 pop {r7} 80025a4: 4770 bx lr 80025a6: bf00 nop 080025a8 : * @brief This function handles Debug Monitor exception. * @param None * @retval None */ void DebugMon_Handler(void) { 80025a8: b480 push {r7} 80025aa: af00 add r7, sp, #0 } 80025ac: 46bd mov sp, r7 80025ae: bc80 pop {r7} 80025b0: 4770 bx lr 80025b2: bf00 nop 080025b4 : * @brief This function handles PendSVC exception. * @param None * @retval None */ void PendSV_Handler(void) { 80025b4: b480 push {r7} 80025b6: af00 add r7, sp, #0 } 80025b8: 46bd mov sp, r7 80025ba: bc80 pop {r7} 80025bc: 4770 bx lr 80025be: bf00 nop 080025c0 : * @brief This function handles SysTick Handler. * @param None * @retval None */ void SysTick_Handler(void) { 80025c0: b480 push {r7} 80025c2: af00 add r7, sp, #0 if(time!=0) 80025c4: f240 63d0 movw r3, #1744 ; 0x6d0 80025c8: f2c2 0300 movt r3, #8192 ; 0x2000 80025cc: 881b ldrh r3, [r3, #0] 80025ce: 2b00 cmp r3, #0 80025d0: d00c beq.n 80025ec { time--; 80025d2: f240 63d0 movw r3, #1744 ; 0x6d0 80025d6: f2c2 0300 movt r3, #8192 ; 0x2000 80025da: 881b ldrh r3, [r3, #0] 80025dc: f103 33ff add.w r3, r3, #4294967295 80025e0: b29a uxth r2, r3 80025e2: f240 63d0 movw r3, #1744 ; 0x6d0 80025e6: f2c2 0300 movt r3, #8192 ; 0x2000 80025ea: 801a strh r2, [r3, #0] } } 80025ec: 46bd mov sp, r7 80025ee: bc80 pop {r7} 80025f0: 4770 bx lr 80025f2: bf00 nop 080025f4 : #include double strtod2(const char *str, char **endptr); int read_double(char *line, uint8_t *char_counter, double *double_ptr) { 80025f4: b580 push {r7, lr} 80025f6: b086 sub sp, #24 80025f8: af00 add r7, sp, #0 80025fa: 60f8 str r0, [r7, #12] 80025fc: 60b9 str r1, [r7, #8] 80025fe: 607a str r2, [r7, #4] char *start = line + *char_counter; 8002600: 68bb ldr r3, [r7, #8] 8002602: 781b ldrb r3, [r3, #0] 8002604: 68fa ldr r2, [r7, #12] 8002606: 18d3 adds r3, r2, r3 8002608: 617b str r3, [r7, #20] char *end; *double_ptr = strtod2(start, &end); 800260a: f107 0310 add.w r3, r7, #16 800260e: 6978 ldr r0, [r7, #20] 8002610: 4619 mov r1, r3 8002612: f000 f86d bl 80026f0 8002616: 4602 mov r2, r0 8002618: 460b mov r3, r1 800261a: 6879 ldr r1, [r7, #4] 800261c: e9c1 2300 strd r2, r3, [r1] if(end == start) { 8002620: 693a ldr r2, [r7, #16] 8002622: 697b ldr r3, [r7, #20] 8002624: 429a cmp r2, r3 8002626: d102 bne.n 800262e return(false); 8002628: f04f 0300 mov.w r3, #0 800262c: e009 b.n 8002642 }; *char_counter = end - line; 800262e: 693b ldr r3, [r7, #16] 8002630: b2da uxtb r2, r3 8002632: 68fb ldr r3, [r7, #12] 8002634: b2db uxtb r3, r3 8002636: 1ad3 subs r3, r2, r3 8002638: b2da uxtb r2, r3 800263a: 68bb ldr r3, [r7, #8] 800263c: 701a strb r2, [r3, #0] return(true); 800263e: f04f 0301 mov.w r3, #1 } 8002642: 4618 mov r0, r3 8002644: f107 0718 add.w r7, r7, #24 8002648: 46bd mov sp, r7 800264a: bd80 pop {r7, pc} 0800264c : { while ( us-- ) { _delay_us(1); } }*/ void set(uint16_t Pin) { 800264c: b480 push {r7} 800264e: b083 sub sp, #12 8002650: af00 add r7, sp, #0 8002652: 4603 mov r3, r0 8002654: 80fb strh r3, [r7, #6] //Invertieren falls notwendig Pin ^= Pin & settings.invert_mask; 8002656: f240 63d8 movw r3, #1752 ; 0x6d8 800265a: f2c2 0300 movt r3, #8192 ; 0x2000 800265e: 8e1b ldrh r3, [r3, #48] ; 0x30 8002660: ea6f 0303 mvn.w r3, r3 8002664: b29a uxth r2, r3 8002666: 88fb ldrh r3, [r7, #6] 8002668: 4013 ands r3, r2 800266a: 80fb strh r3, [r7, #6] STEPPING_PORT->BSRRL = Pin; 800266c: f44f 6300 mov.w r3, #2048 ; 0x800 8002670: f2c4 0302 movt r3, #16386 ; 0x4002 8002674: 88fa ldrh r2, [r7, #6] 8002676: 831a strh r2, [r3, #24] } 8002678: f107 070c add.w r7, r7, #12 800267c: 46bd mov sp, r7 800267e: bc80 pop {r7} 8002680: 4770 bx lr 8002682: bf00 nop 08002684 : void reset(uint16_t Pin) { 8002684: b480 push {r7} 8002686: b083 sub sp, #12 8002688: af00 add r7, sp, #0 800268a: 4603 mov r3, r0 800268c: 80fb strh r3, [r7, #6] //Invertieren falls notwendig Pin ^= Pin & settings.invert_mask; 800268e: f240 63d8 movw r3, #1752 ; 0x6d8 8002692: f2c2 0300 movt r3, #8192 ; 0x2000 8002696: 8e1b ldrh r3, [r3, #48] ; 0x30 8002698: ea6f 0303 mvn.w r3, r3 800269c: b29a uxth r2, r3 800269e: 88fb ldrh r3, [r7, #6] 80026a0: 4013 ands r3, r2 80026a2: 80fb strh r3, [r7, #6] STEPPING_PORT->BSRRH = Pin; 80026a4: f44f 6300 mov.w r3, #2048 ; 0x800 80026a8: f2c4 0302 movt r3, #16386 ; 0x4002 80026ac: 88fa ldrh r2, [r7, #6] 80026ae: 835a strh r2, [r3, #26] } 80026b0: f107 070c add.w r7, r7, #12 80026b4: 46bd mov sp, r7 80026b6: bc80 pop {r7} 80026b8: 4770 bx lr 80026ba: bf00 nop 080026bc : int isspace2(int c) { 80026bc: b480 push {r7} 80026be: b083 sub sp, #12 80026c0: af00 add r7, sp, #0 80026c2: 6078 str r0, [r7, #4] return ((c>=0x09 && c<=0x0D) || (c==0x20)); 80026c4: 687b ldr r3, [r7, #4] 80026c6: 2b08 cmp r3, #8 80026c8: dd02 ble.n 80026d0 80026ca: 687b ldr r3, [r7, #4] 80026cc: 2b0d cmp r3, #13 80026ce: dd02 ble.n 80026d6 80026d0: 687b ldr r3, [r7, #4] 80026d2: 2b20 cmp r3, #32 80026d4: d102 bne.n 80026dc 80026d6: f04f 0301 mov.w r3, #1 80026da: e001 b.n 80026e0 80026dc: f04f 0300 mov.w r3, #0 } 80026e0: 4618 mov r0, r3 80026e2: f107 070c add.w r7, r7, #12 80026e6: 46bd mov sp, r7 80026e8: bc80 pop {r7} 80026ea: 4770 bx lr 80026ec: 0000 movs r0, r0 ... 080026f0 : double strtod2(const char *str, char **endptr) { 80026f0: b5b0 push {r4, r5, r7, lr} 80026f2: b08e sub sp, #56 ; 0x38 80026f4: af00 add r7, sp, #0 80026f6: 6078 str r0, [r7, #4] 80026f8: 6039 str r1, [r7, #0] double number; int exponent; int negative; char *p = (char *) str; 80026fa: 687b ldr r3, [r7, #4] 80026fc: 627b str r3, [r7, #36] ; 0x24 // Skip leading whitespace //while (isspace(*p)) p++; while(1) { if(isspace2(*p)==0) 80026fe: 6a7b ldr r3, [r7, #36] ; 0x24 8002700: 781b ldrb r3, [r3, #0] 8002702: 4618 mov r0, r3 8002704: f7ff ffda bl 80026bc 8002708: 4603 mov r3, r0 800270a: 2b00 cmp r3, #0 800270c: d004 beq.n 8002718 { break; } p++; 800270e: 6a7b ldr r3, [r7, #36] ; 0x24 8002710: f103 0301 add.w r3, r3, #1 8002714: 627b str r3, [r7, #36] ; 0x24 } 8002716: e7f2 b.n 80026fe //while (isspace(*p)) p++; while(1) { if(isspace2(*p)==0) { break; 8002718: bf00 nop } p++; } // Handle optional sign negative = 0; 800271a: f04f 0300 mov.w r3, #0 800271e: 62bb str r3, [r7, #40] ; 0x28 switch (*p) 8002720: 6a7b ldr r3, [r7, #36] ; 0x24 8002722: 781b ldrb r3, [r3, #0] 8002724: 2b2b cmp r3, #43 ; 0x2b 8002726: d004 beq.n 8002732 8002728: 2b2d cmp r3, #45 ; 0x2d 800272a: d106 bne.n 800273a { case '-': negative = 1; // Fall through to increment position 800272c: f04f 0301 mov.w r3, #1 8002730: 62bb str r3, [r7, #40] ; 0x28 case '+': p++; 8002732: 6a7b ldr r3, [r7, #36] ; 0x24 8002734: f103 0301 add.w r3, r3, #1 8002738: 627b str r3, [r7, #36] ; 0x24 } number = 0.; 800273a: a3a3 add r3, pc, #652 ; (adr r3, 80029c8 ) 800273c: e9d3 2300 ldrd r2, r3, [r3] 8002740: e9c7 230c strd r2, r3, [r7, #48] ; 0x30 exponent = 0; 8002744: f04f 0300 mov.w r3, #0 8002748: 62fb str r3, [r7, #44] ; 0x2c num_digits = 0; 800274a: f04f 0300 mov.w r3, #0 800274e: 613b str r3, [r7, #16] num_decimals = 0; 8002750: f04f 0300 mov.w r3, #0 8002754: 60fb str r3, [r7, #12] // Process string of digits while (isdigit(*p)) 8002756: e023 b.n 80027a0 { number = number * 10. + (*p - '0'); 8002758: e9d7 010c ldrd r0, r1, [r7, #48] ; 0x30 800275c: a39c add r3, pc, #624 ; (adr r3, 80029d0 ) 800275e: e9d3 2300 ldrd r2, r3, [r3] 8002762: f006 fa3d bl 8008be0 <__aeabi_dmul> 8002766: 4602 mov r2, r0 8002768: 460b mov r3, r1 800276a: 4614 mov r4, r2 800276c: 461d mov r5, r3 800276e: 6a7b ldr r3, [r7, #36] ; 0x24 8002770: 781b ldrb r3, [r3, #0] 8002772: f1a3 0330 sub.w r3, r3, #48 ; 0x30 8002776: 4618 mov r0, r3 8002778: f006 f9cc bl 8008b14 <__aeabi_i2d> 800277c: 4602 mov r2, r0 800277e: 460b mov r3, r1 8002780: 4620 mov r0, r4 8002782: 4629 mov r1, r5 8002784: f006 f87a bl 800887c <__adddf3> 8002788: 4602 mov r2, r0 800278a: 460b mov r3, r1 800278c: e9c7 230c strd r2, r3, [r7, #48] ; 0x30 p++; 8002790: 6a7b ldr r3, [r7, #36] ; 0x24 8002792: f103 0301 add.w r3, r3, #1 8002796: 627b str r3, [r7, #36] ; 0x24 num_digits++; 8002798: 693b ldr r3, [r7, #16] 800279a: f103 0301 add.w r3, r3, #1 800279e: 613b str r3, [r7, #16] exponent = 0; num_digits = 0; num_decimals = 0; // Process string of digits while (isdigit(*p)) 80027a0: 6a7b ldr r3, [r7, #36] ; 0x24 80027a2: 781b ldrb r3, [r3, #0] 80027a4: f1a3 0330 sub.w r3, r3, #48 ; 0x30 80027a8: 2b09 cmp r3, #9 80027aa: d9d5 bls.n 8002758 p++; num_digits++; } // Process decimal part if (*p == '.') 80027ac: 6a7b ldr r3, [r7, #36] ; 0x24 80027ae: 781b ldrb r3, [r3, #0] 80027b0: 2b2e cmp r3, #46 ; 0x2e 80027b2: d136 bne.n 8002822 { p++; 80027b4: 6a7b ldr r3, [r7, #36] ; 0x24 80027b6: f103 0301 add.w r3, r3, #1 80027ba: 627b str r3, [r7, #36] ; 0x24 while (isdigit(*p)) 80027bc: e027 b.n 800280e { number = number * 10. + (*p - '0'); 80027be: e9d7 010c ldrd r0, r1, [r7, #48] ; 0x30 80027c2: a383 add r3, pc, #524 ; (adr r3, 80029d0 ) 80027c4: e9d3 2300 ldrd r2, r3, [r3] 80027c8: f006 fa0a bl 8008be0 <__aeabi_dmul> 80027cc: 4602 mov r2, r0 80027ce: 460b mov r3, r1 80027d0: 4614 mov r4, r2 80027d2: 461d mov r5, r3 80027d4: 6a7b ldr r3, [r7, #36] ; 0x24 80027d6: 781b ldrb r3, [r3, #0] 80027d8: f1a3 0330 sub.w r3, r3, #48 ; 0x30 80027dc: 4618 mov r0, r3 80027de: f006 f999 bl 8008b14 <__aeabi_i2d> 80027e2: 4602 mov r2, r0 80027e4: 460b mov r3, r1 80027e6: 4620 mov r0, r4 80027e8: 4629 mov r1, r5 80027ea: f006 f847 bl 800887c <__adddf3> 80027ee: 4602 mov r2, r0 80027f0: 460b mov r3, r1 80027f2: e9c7 230c strd r2, r3, [r7, #48] ; 0x30 p++; 80027f6: 6a7b ldr r3, [r7, #36] ; 0x24 80027f8: f103 0301 add.w r3, r3, #1 80027fc: 627b str r3, [r7, #36] ; 0x24 num_digits++; 80027fe: 693b ldr r3, [r7, #16] 8002800: f103 0301 add.w r3, r3, #1 8002804: 613b str r3, [r7, #16] num_decimals++; 8002806: 68fb ldr r3, [r7, #12] 8002808: f103 0301 add.w r3, r3, #1 800280c: 60fb str r3, [r7, #12] // Process decimal part if (*p == '.') { p++; while (isdigit(*p)) 800280e: 6a7b ldr r3, [r7, #36] ; 0x24 8002810: 781b ldrb r3, [r3, #0] 8002812: f1a3 0330 sub.w r3, r3, #48 ; 0x30 8002816: 2b09 cmp r3, #9 8002818: d9d1 bls.n 80027be p++; num_digits++; num_decimals++; } exponent -= num_decimals; 800281a: 6afa ldr r2, [r7, #44] ; 0x2c 800281c: 68fb ldr r3, [r7, #12] 800281e: 1ad3 subs r3, r2, r3 8002820: 62fb str r3, [r7, #44] ; 0x2c } if (num_digits == 0) 8002822: 693b ldr r3, [r7, #16] 8002824: 2b00 cmp r3, #0 8002826: d109 bne.n 800283c { errno = ERANGE; 8002828: f002 ef58 blx 80056dc <__errno> 800282c: 4603 mov r3, r0 800282e: f04f 0222 mov.w r2, #34 ; 0x22 8002832: 601a str r2, [r3, #0] return 0.0; 8002834: a364 add r3, pc, #400 ; (adr r3, 80029c8 ) 8002836: e9d3 2300 ldrd r2, r3, [r3] 800283a: e0be b.n 80029ba } // Correct for sign if (negative) number = -number; 800283c: 6abb ldr r3, [r7, #40] ; 0x28 800283e: 2b00 cmp r3, #0 8002840: d005 beq.n 800284e 8002842: 6b3b ldr r3, [r7, #48] ; 0x30 8002844: 633b str r3, [r7, #48] ; 0x30 8002846: 6b7b ldr r3, [r7, #52] ; 0x34 8002848: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 800284c: 637b str r3, [r7, #52] ; 0x34 // Process an exponent string if (*p == 'e' || *p == 'E') 800284e: 6a7b ldr r3, [r7, #36] ; 0x24 8002850: 781b ldrb r3, [r3, #0] 8002852: 2b65 cmp r3, #101 ; 0x65 8002854: d003 beq.n 800285e 8002856: 6a7b ldr r3, [r7, #36] ; 0x24 8002858: 781b ldrb r3, [r3, #0] 800285a: 2b45 cmp r3, #69 ; 0x45 800285c: d13b bne.n 80028d6 { // Handle optional sign negative = 0; 800285e: f04f 0300 mov.w r3, #0 8002862: 62bb str r3, [r7, #40] ; 0x28 switch (*++p) 8002864: 6a7b ldr r3, [r7, #36] ; 0x24 8002866: f103 0301 add.w r3, r3, #1 800286a: 627b str r3, [r7, #36] ; 0x24 800286c: 6a7b ldr r3, [r7, #36] ; 0x24 800286e: 781b ldrb r3, [r3, #0] 8002870: 2b2b cmp r3, #43 ; 0x2b 8002872: d004 beq.n 800287e 8002874: 2b2d cmp r3, #45 ; 0x2d 8002876: d106 bne.n 8002886 { case '-': negative = 1; // Fall through to increment pos 8002878: f04f 0301 mov.w r3, #1 800287c: 62bb str r3, [r7, #40] ; 0x28 case '+': p++; 800287e: 6a7b ldr r3, [r7, #36] ; 0x24 8002880: f103 0301 add.w r3, r3, #1 8002884: 627b str r3, [r7, #36] ; 0x24 } // Process string of digits n = 0; 8002886: f04f 0300 mov.w r3, #0 800288a: 617b str r3, [r7, #20] while (isdigit(*p)) 800288c: e011 b.n 80028b2 { n = n * 10 + (*p - '0'); 800288e: 697a ldr r2, [r7, #20] 8002890: 4613 mov r3, r2 8002892: ea4f 0383 mov.w r3, r3, lsl #2 8002896: 189b adds r3, r3, r2 8002898: ea4f 0343 mov.w r3, r3, lsl #1 800289c: 461a mov r2, r3 800289e: 6a7b ldr r3, [r7, #36] ; 0x24 80028a0: 781b ldrb r3, [r3, #0] 80028a2: f1a3 0330 sub.w r3, r3, #48 ; 0x30 80028a6: 18d3 adds r3, r2, r3 80028a8: 617b str r3, [r7, #20] p++; 80028aa: 6a7b ldr r3, [r7, #36] ; 0x24 80028ac: f103 0301 add.w r3, r3, #1 80028b0: 627b str r3, [r7, #36] ; 0x24 case '+': p++; } // Process string of digits n = 0; while (isdigit(*p)) 80028b2: 6a7b ldr r3, [r7, #36] ; 0x24 80028b4: 781b ldrb r3, [r3, #0] 80028b6: f1a3 0330 sub.w r3, r3, #48 ; 0x30 80028ba: 2b09 cmp r3, #9 80028bc: d9e7 bls.n 800288e { n = n * 10 + (*p - '0'); p++; } if (negative) 80028be: 6abb ldr r3, [r7, #40] ; 0x28 80028c0: 2b00 cmp r3, #0 80028c2: d004 beq.n 80028ce exponent -= n; 80028c4: 6afa ldr r2, [r7, #44] ; 0x2c 80028c6: 697b ldr r3, [r7, #20] 80028c8: 1ad3 subs r3, r2, r3 80028ca: 62fb str r3, [r7, #44] ; 0x2c 80028cc: e003 b.n 80028d6 else exponent += n; 80028ce: 6afa ldr r2, [r7, #44] ; 0x2c 80028d0: 697b ldr r3, [r7, #20] 80028d2: 18d3 adds r3, r2, r3 80028d4: 62fb str r3, [r7, #44] ; 0x2c } if (exponent < DBL_MIN_EXP || exponent > DBL_MAX_EXP) 80028d6: 6afa ldr r2, [r7, #44] ; 0x2c 80028d8: f46f 737f mvn.w r3, #1020 ; 0x3fc 80028dc: 429a cmp r2, r3 80028de: db03 blt.n 80028e8 80028e0: 6afb ldr r3, [r7, #44] ; 0x2c 80028e2: f5b3 6f80 cmp.w r3, #1024 ; 0x400 80028e6: dd09 ble.n 80028fc { errno = ERANGE; 80028e8: f002 eef8 blx 80056dc <__errno> 80028ec: 4603 mov r3, r0 80028ee: f04f 0222 mov.w r2, #34 ; 0x22 80028f2: 601a str r2, [r3, #0] return HUGE_VAL; 80028f4: a338 add r3, pc, #224 ; (adr r3, 80029d8 ) 80028f6: e9d3 2300 ldrd r2, r3, [r3] 80028fa: e05e b.n 80029ba } // Scale the result p10 = 10.; 80028fc: a334 add r3, pc, #208 ; (adr r3, 80029d0 ) 80028fe: e9d3 2300 ldrd r2, r3, [r3] 8002902: e9c7 2306 strd r2, r3, [r7, #24] n = exponent; 8002906: 6afb ldr r3, [r7, #44] ; 0x2c 8002908: 617b str r3, [r7, #20] if (n < 0) n = -n; 800290a: 697b ldr r3, [r7, #20] 800290c: 2b00 cmp r3, #0 800290e: da30 bge.n 8002972 8002910: 697b ldr r3, [r7, #20] 8002912: f1c3 0300 rsb r3, r3, #0 8002916: 617b str r3, [r7, #20] while (n) 8002918: e02b b.n 8002972 { if (n & 1) 800291a: 697b ldr r3, [r7, #20] 800291c: f003 0301 and.w r3, r3, #1 8002920: b2db uxtb r3, r3 8002922: 2b00 cmp r3, #0 8002924: d017 beq.n 8002956 { if (exponent < 0) 8002926: 6afb ldr r3, [r7, #44] ; 0x2c 8002928: 2b00 cmp r3, #0 800292a: da0a bge.n 8002942 number /= p10; 800292c: e9d7 010c ldrd r0, r1, [r7, #48] ; 0x30 8002930: e9d7 2306 ldrd r2, r3, [r7, #24] 8002934: f006 fa7e bl 8008e34 <__aeabi_ddiv> 8002938: 4602 mov r2, r0 800293a: 460b mov r3, r1 800293c: e9c7 230c strd r2, r3, [r7, #48] ; 0x30 8002940: e009 b.n 8002956 else number *= p10; 8002942: e9d7 010c ldrd r0, r1, [r7, #48] ; 0x30 8002946: e9d7 2306 ldrd r2, r3, [r7, #24] 800294a: f006 f949 bl 8008be0 <__aeabi_dmul> 800294e: 4602 mov r2, r0 8002950: 460b mov r3, r1 8002952: e9c7 230c strd r2, r3, [r7, #48] ; 0x30 } n >>= 1; 8002956: 697b ldr r3, [r7, #20] 8002958: ea4f 0363 mov.w r3, r3, asr #1 800295c: 617b str r3, [r7, #20] p10 *= p10; 800295e: e9d7 0106 ldrd r0, r1, [r7, #24] 8002962: e9d7 2306 ldrd r2, r3, [r7, #24] 8002966: f006 f93b bl 8008be0 <__aeabi_dmul> 800296a: 4602 mov r2, r0 800296c: 460b mov r3, r1 800296e: e9c7 2306 strd r2, r3, [r7, #24] // Scale the result p10 = 10.; n = exponent; if (n < 0) n = -n; while (n) 8002972: 697b ldr r3, [r7, #20] 8002974: 2b00 cmp r3, #0 8002976: d1d0 bne.n 800291a } n >>= 1; p10 *= p10; } if (number == HUGE_VAL) errno = ERANGE; 8002978: f04f 0301 mov.w r3, #1 800297c: 461c mov r4, r3 800297e: e9d7 010c ldrd r0, r1, [r7, #48] ; 0x30 8002982: a317 add r3, pc, #92 ; (adr r3, 80029e0 ) 8002984: e9d3 2300 ldrd r2, r3, [r3] 8002988: f006 fbba bl 8009100 <__aeabi_dcmpgt> 800298c: 4603 mov r3, r0 800298e: 2b00 cmp r3, #0 8002990: d102 bne.n 8002998 8002992: f04f 0300 mov.w r3, #0 8002996: 461c mov r4, r3 8002998: b2e3 uxtb r3, r4 800299a: 2b00 cmp r3, #0 800299c: d005 beq.n 80029aa 800299e: f002 ee9e blx 80056dc <__errno> 80029a2: 4603 mov r3, r0 80029a4: f04f 0222 mov.w r2, #34 ; 0x22 80029a8: 601a str r2, [r3, #0] if (endptr) *endptr = p; 80029aa: 683b ldr r3, [r7, #0] 80029ac: 2b00 cmp r3, #0 80029ae: d002 beq.n 80029b6 80029b0: 683b ldr r3, [r7, #0] 80029b2: 6a7a ldr r2, [r7, #36] ; 0x24 80029b4: 601a str r2, [r3, #0] return number; 80029b6: e9d7 230c ldrd r2, r3, [r7, #48] ; 0x30 } 80029ba: 4610 mov r0, r2 80029bc: 4619 mov r1, r3 80029be: f107 0738 add.w r7, r7, #56 ; 0x38 80029c2: 46bd mov sp, r7 80029c4: bdb0 pop {r4, r5, r7, pc} 80029c6: bf00 nop ... 80029d4: 40240000 .word 0x40240000 80029d8: 00000000 .word 0x00000000 80029dc: 7ff00000 .word 0x7ff00000 80029e0: ffffffff .word 0xffffffff 80029e4: 7fefffff .word 0x7fefffff 080029e8 : uint16_t time; /* set TIM5 to run at DELAY_TIM_FREQUENCY */ void delay_init( uint32_t frequency ) { 80029e8: b580 push {r7, lr} 80029ea: b086 sub sp, #24 80029ec: af00 add r7, sp, #0 80029ee: 6078 str r0, [r7, #4] /* Enable timer clock - use TIMER5 */ RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM5, ENABLE); 80029f0: f04f 0008 mov.w r0, #8 80029f4: f04f 0101 mov.w r1, #1 80029f8: f7ff fd8e bl 8002518 /* Time base configuration */ TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; TIM_TimeBaseStructInit(&TIM_TimeBaseStructure); 80029fc: f107 030c add.w r3, r7, #12 8002a00: 4618 mov r0, r3 8002a02: f002 fcff bl 8005404 TIM_TimeBaseStructure.TIM_Prescaler = (168000000 / frequency) - 1; 8002a06: f44f 43f4 mov.w r3, #31232 ; 0x7a00 8002a0a: f6c0 2303 movt r3, #2563 ; 0xa03 8002a0e: 687a ldr r2, [r7, #4] 8002a10: fbb3 f3f2 udiv r3, r3, r2 8002a14: b29b uxth r3, r3 8002a16: f103 33ff add.w r3, r3, #4294967295 8002a1a: b29b uxth r3, r3 8002a1c: 81bb strh r3, [r7, #12] TIM_TimeBaseStructure.TIM_Period = UINT16_MAX; 8002a1e: f64f 73ff movw r3, #65535 ; 0xffff 8002a22: 613b str r3, [r7, #16] TIM_TimeBaseStructure.TIM_ClockDivision = 0; 8002a24: f04f 0300 mov.w r3, #0 8002a28: 82bb strh r3, [r7, #20] TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; 8002a2a: f04f 0300 mov.w r3, #0 8002a2e: 81fb strh r3, [r7, #14] TIM_TimeBaseInit(TIM5, &TIM_TimeBaseStructure); 8002a30: f107 030c add.w r3, r7, #12 8002a34: f44f 6040 mov.w r0, #3072 ; 0xc00 8002a38: f2c4 0000 movt r0, #16384 ; 0x4000 8002a3c: 4619 mov r1, r3 8002a3e: f002 fc67 bl 8005310 /* Enable counter */ TIM_Cmd(TIM5, ENABLE); 8002a42: f44f 6040 mov.w r0, #3072 ; 0xc00 8002a46: f2c4 0000 movt r0, #16384 ; 0x4000 8002a4a: f04f 0101 mov.w r1, #1 8002a4e: f002 fd05 bl 800545c } 8002a52: f107 0718 add.w r7, r7, #24 8002a56: 46bd mov sp, r7 8002a58: bd80 pop {r7, pc} 8002a5a: bf00 nop 08002a5c : void delay_ms(uint16_t ms) { 8002a5c: b580 push {r7, lr} 8002a5e: b084 sub sp, #16 8002a60: af00 add r7, sp, #0 8002a62: 4603 mov r3, r0 8002a64: 80fb strh r3, [r7, #6] delay_init(1000); //1kHz --> 1ms 8002a66: f44f 707a mov.w r0, #1000 ; 0x3e8 8002a6a: f7ff ffbd bl 80029e8 uint16_t start = TIM5->CNT; 8002a6e: f44f 6340 mov.w r3, #3072 ; 0xc00 8002a72: f2c4 0300 movt r3, #16384 ; 0x4000 8002a76: 6a5b ldr r3, [r3, #36] ; 0x24 8002a78: 81fb strh r3, [r7, #14] /* use 16 bit count wrap around */ while((uint16_t)(TIM5->CNT - start) <= ms); 8002a7a: bf00 nop 8002a7c: f44f 6340 mov.w r3, #3072 ; 0xc00 8002a80: f2c4 0300 movt r3, #16384 ; 0x4000 8002a84: 6a5b ldr r3, [r3, #36] ; 0x24 8002a86: b29a uxth r2, r3 8002a88: 89fb ldrh r3, [r7, #14] 8002a8a: 1ad3 subs r3, r2, r3 8002a8c: b29b uxth r3, r3 8002a8e: 88fa ldrh r2, [r7, #6] 8002a90: 429a cmp r2, r3 8002a92: d2f3 bcs.n 8002a7c } 8002a94: f107 0710 add.w r7, r7, #16 8002a98: 46bd mov sp, r7 8002a9a: bd80 pop {r7, pc} 08002a9c : void delay_us(uint16_t us) { 8002a9c: b580 push {r7, lr} 8002a9e: b084 sub sp, #16 8002aa0: af00 add r7, sp, #0 8002aa2: 4603 mov r3, r0 8002aa4: 80fb strh r3, [r7, #6] delay_init(1000000); //1MHz --> 1us 8002aa6: f244 2040 movw r0, #16960 ; 0x4240 8002aaa: f2c0 000f movt r0, #15 8002aae: f7ff ff9b bl 80029e8 uint16_t start = TIM5->CNT; 8002ab2: f44f 6340 mov.w r3, #3072 ; 0xc00 8002ab6: f2c4 0300 movt r3, #16384 ; 0x4000 8002aba: 6a5b ldr r3, [r3, #36] ; 0x24 8002abc: 81fb strh r3, [r7, #14] /* use 16 bit count wrap around */ while((uint16_t)(TIM5->CNT - start) <= us); 8002abe: bf00 nop 8002ac0: f44f 6340 mov.w r3, #3072 ; 0xc00 8002ac4: f2c4 0300 movt r3, #16384 ; 0x4000 8002ac8: 6a5b ldr r3, [r3, #36] ; 0x24 8002aca: b29a uxth r2, r3 8002acc: 89fb ldrh r3, [r7, #14] 8002ace: 1ad3 subs r3, r2, r3 8002ad0: b29b uxth r3, r3 8002ad2: 88fa ldrh r2, [r7, #6] 8002ad4: 429a cmp r2, r3 8002ad6: d2f3 bcs.n 8002ac0 } 8002ad8: f107 0710 add.w r7, r7, #16 8002adc: 46bd mov sp, r7 8002ade: bd80 pop {r7, pc} 08002ae0 : time--; } } void sleep_mode() { 8002ae0: b480 push {r7} 8002ae2: af00 add r7, sp, #0 Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. */ __attribute__( ( always_inline ) ) static __INLINE void __WFI(void) { __ASM volatile ("wfi"); 8002ae4: bf30 wfi __WFI(); } 8002ae6: 46bd mov sp, r7 8002ae8: bc80 pop {r7} 8002aea: 4770 bx lr 08002aec : * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) { 8002aec: b480 push {r7} 8002aee: b087 sub sp, #28 8002af0: af00 add r7, sp, #0 8002af2: 6078 str r0, [r7, #4] 8002af4: 6039 str r1, [r7, #0] uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00; 8002af6: f04f 0300 mov.w r3, #0 8002afa: 617b str r3, [r7, #20] 8002afc: f04f 0300 mov.w r3, #0 8002b00: 613b str r3, [r7, #16] 8002b02: f04f 0300 mov.w r3, #0 8002b06: 60fb str r3, [r7, #12] assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); /* -------------------------Configure the port pins---------------- */ /*-- GPIO Mode Configuration --*/ for (pinpos = 0x00; pinpos < 0x10; pinpos++) 8002b08: f04f 0300 mov.w r3, #0 8002b0c: 617b str r3, [r7, #20] 8002b0e: e08e b.n 8002c2e { pos = ((uint32_t)0x01) << pinpos; 8002b10: 697b ldr r3, [r7, #20] 8002b12: f04f 0201 mov.w r2, #1 8002b16: fa02 f303 lsl.w r3, r2, r3 8002b1a: 613b str r3, [r7, #16] /* Get the port pins position */ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; 8002b1c: 683b ldr r3, [r7, #0] 8002b1e: 681a ldr r2, [r3, #0] 8002b20: 693b ldr r3, [r7, #16] 8002b22: 4013 ands r3, r2 8002b24: 60fb str r3, [r7, #12] if (currentpin == pos) 8002b26: 68fa ldr r2, [r7, #12] 8002b28: 693b ldr r3, [r7, #16] 8002b2a: 429a cmp r2, r3 8002b2c: d17b bne.n 8002c26 { GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); 8002b2e: 687b ldr r3, [r7, #4] 8002b30: 681b ldr r3, [r3, #0] 8002b32: 461a mov r2, r3 8002b34: 697b ldr r3, [r7, #20] 8002b36: ea4f 0343 mov.w r3, r3, lsl #1 8002b3a: f04f 0103 mov.w r1, #3 8002b3e: fa01 f303 lsl.w r3, r1, r3 8002b42: ea6f 0303 mvn.w r3, r3 8002b46: 401a ands r2, r3 8002b48: 687b ldr r3, [r7, #4] 8002b4a: 601a str r2, [r3, #0] GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); 8002b4c: 687b ldr r3, [r7, #4] 8002b4e: 681b ldr r3, [r3, #0] 8002b50: 461a mov r2, r3 8002b52: 683b ldr r3, [r7, #0] 8002b54: 791b ldrb r3, [r3, #4] 8002b56: 4619 mov r1, r3 8002b58: 697b ldr r3, [r7, #20] 8002b5a: ea4f 0343 mov.w r3, r3, lsl #1 8002b5e: fa01 f303 lsl.w r3, r1, r3 8002b62: 431a orrs r2, r3 8002b64: 687b ldr r3, [r7, #4] 8002b66: 601a str r2, [r3, #0] if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) 8002b68: 683b ldr r3, [r7, #0] 8002b6a: 791b ldrb r3, [r3, #4] 8002b6c: 2b01 cmp r3, #1 8002b6e: d003 beq.n 8002b78 8002b70: 683b ldr r3, [r7, #0] 8002b72: 791b ldrb r3, [r3, #4] 8002b74: 2b02 cmp r3, #2 8002b76: d138 bne.n 8002bea { /* Check Speed mode parameters */ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); /* Speed mode configuration */ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2)); 8002b78: 687b ldr r3, [r7, #4] 8002b7a: 689b ldr r3, [r3, #8] 8002b7c: 461a mov r2, r3 8002b7e: 697b ldr r3, [r7, #20] 8002b80: ea4f 0343 mov.w r3, r3, lsl #1 8002b84: f04f 0103 mov.w r1, #3 8002b88: fa01 f303 lsl.w r3, r1, r3 8002b8c: ea6f 0303 mvn.w r3, r3 8002b90: 401a ands r2, r3 8002b92: 687b ldr r3, [r7, #4] 8002b94: 609a str r2, [r3, #8] GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); 8002b96: 687b ldr r3, [r7, #4] 8002b98: 689b ldr r3, [r3, #8] 8002b9a: 461a mov r2, r3 8002b9c: 683b ldr r3, [r7, #0] 8002b9e: 795b ldrb r3, [r3, #5] 8002ba0: 4619 mov r1, r3 8002ba2: 697b ldr r3, [r7, #20] 8002ba4: ea4f 0343 mov.w r3, r3, lsl #1 8002ba8: fa01 f303 lsl.w r3, r1, r3 8002bac: 431a orrs r2, r3 8002bae: 687b ldr r3, [r7, #4] 8002bb0: 609a str r2, [r3, #8] /* Check Output mode parameters */ assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); /* Output mode configuration*/ GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ; 8002bb2: 687b ldr r3, [r7, #4] 8002bb4: 685b ldr r3, [r3, #4] 8002bb6: 461a mov r2, r3 8002bb8: 697b ldr r3, [r7, #20] 8002bba: b29b uxth r3, r3 8002bbc: f04f 0101 mov.w r1, #1 8002bc0: fa01 f303 lsl.w r3, r1, r3 8002bc4: ea6f 0303 mvn.w r3, r3 8002bc8: 401a ands r2, r3 8002bca: 687b ldr r3, [r7, #4] 8002bcc: 605a str r2, [r3, #4] GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); 8002bce: 687b ldr r3, [r7, #4] 8002bd0: 685b ldr r3, [r3, #4] 8002bd2: 461a mov r2, r3 8002bd4: 683b ldr r3, [r7, #0] 8002bd6: 799b ldrb r3, [r3, #6] 8002bd8: 4619 mov r1, r3 8002bda: 697b ldr r3, [r7, #20] 8002bdc: b29b uxth r3, r3 8002bde: fa01 f303 lsl.w r3, r1, r3 8002be2: b29b uxth r3, r3 8002be4: 431a orrs r2, r3 8002be6: 687b ldr r3, [r7, #4] 8002be8: 605a str r2, [r3, #4] } /* Pull-up Pull down resistor configuration*/ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); 8002bea: 687b ldr r3, [r7, #4] 8002bec: 68db ldr r3, [r3, #12] 8002bee: 461a mov r2, r3 8002bf0: 697b ldr r3, [r7, #20] 8002bf2: b29b uxth r3, r3 8002bf4: ea4f 0343 mov.w r3, r3, lsl #1 8002bf8: f04f 0103 mov.w r1, #3 8002bfc: fa01 f303 lsl.w r3, r1, r3 8002c00: ea6f 0303 mvn.w r3, r3 8002c04: 401a ands r2, r3 8002c06: 687b ldr r3, [r7, #4] 8002c08: 60da str r2, [r3, #12] GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); 8002c0a: 687b ldr r3, [r7, #4] 8002c0c: 68db ldr r3, [r3, #12] 8002c0e: 461a mov r2, r3 8002c10: 683b ldr r3, [r7, #0] 8002c12: 79db ldrb r3, [r3, #7] 8002c14: 4619 mov r1, r3 8002c16: 697b ldr r3, [r7, #20] 8002c18: ea4f 0343 mov.w r3, r3, lsl #1 8002c1c: fa01 f303 lsl.w r3, r1, r3 8002c20: 431a orrs r2, r3 8002c22: 687b ldr r3, [r7, #4] 8002c24: 60da str r2, [r3, #12] assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); /* -------------------------Configure the port pins---------------- */ /*-- GPIO Mode Configuration --*/ for (pinpos = 0x00; pinpos < 0x10; pinpos++) 8002c26: 697b ldr r3, [r7, #20] 8002c28: f103 0301 add.w r3, r3, #1 8002c2c: 617b str r3, [r7, #20] 8002c2e: 697b ldr r3, [r7, #20] 8002c30: 2b0f cmp r3, #15 8002c32: f67f af6d bls.w 8002b10 /* Pull-up Pull down resistor configuration*/ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); } } } 8002c36: f107 071c add.w r7, r7, #28 8002c3a: 46bd mov sp, r7 8002c3c: bc80 pop {r7} 8002c3e: 4770 bx lr 08002c40 : * @arg GPIO_AF_DCMI: Connect DCMI pins to AF13 * @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15 * @retval None */ void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) { 8002c40: b480 push {r7} 8002c42: b085 sub sp, #20 8002c44: af00 add r7, sp, #0 8002c46: 6078 str r0, [r7, #4] 8002c48: 4613 mov r3, r2 8002c4a: 460a mov r2, r1 8002c4c: 807a strh r2, [r7, #2] 8002c4e: 707b strb r3, [r7, #1] uint32_t temp = 0x00; 8002c50: f04f 0300 mov.w r3, #0 8002c54: 60fb str r3, [r7, #12] uint32_t temp_2 = 0x00; 8002c56: f04f 0300 mov.w r3, #0 8002c5a: 60bb str r3, [r7, #8] /* Check the parameters */ assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); assert_param(IS_GPIO_AF(GPIO_AF)); temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; 8002c5c: 787a ldrb r2, [r7, #1] 8002c5e: 887b ldrh r3, [r7, #2] 8002c60: f003 0307 and.w r3, r3, #7 8002c64: ea4f 0383 mov.w r3, r3, lsl #2 8002c68: fa02 f303 lsl.w r3, r2, r3 8002c6c: 60fb str r3, [r7, #12] GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ; 8002c6e: 887b ldrh r3, [r7, #2] 8002c70: ea4f 03d3 mov.w r3, r3, lsr #3 8002c74: b29b uxth r3, r3 8002c76: 461a mov r2, r3 8002c78: 887b ldrh r3, [r7, #2] 8002c7a: ea4f 03d3 mov.w r3, r3, lsr #3 8002c7e: b29b uxth r3, r3 8002c80: 4619 mov r1, r3 8002c82: 687b ldr r3, [r7, #4] 8002c84: f101 0108 add.w r1, r1, #8 8002c88: f853 3021 ldr.w r3, [r3, r1, lsl #2] 8002c8c: 4619 mov r1, r3 8002c8e: 887b ldrh r3, [r7, #2] 8002c90: f003 0307 and.w r3, r3, #7 8002c94: ea4f 0383 mov.w r3, r3, lsl #2 8002c98: f04f 000f mov.w r0, #15 8002c9c: fa00 f303 lsl.w r3, r0, r3 8002ca0: ea6f 0303 mvn.w r3, r3 8002ca4: 4019 ands r1, r3 8002ca6: 687b ldr r3, [r7, #4] 8002ca8: f102 0208 add.w r2, r2, #8 8002cac: f843 1022 str.w r1, [r3, r2, lsl #2] temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; 8002cb0: 887b ldrh r3, [r7, #2] 8002cb2: ea4f 03d3 mov.w r3, r3, lsr #3 8002cb6: b29b uxth r3, r3 8002cb8: 461a mov r2, r3 8002cba: 687b ldr r3, [r7, #4] 8002cbc: f102 0208 add.w r2, r2, #8 8002cc0: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8002cc4: 461a mov r2, r3 8002cc6: 68fb ldr r3, [r7, #12] 8002cc8: 4313 orrs r3, r2 8002cca: 60bb str r3, [r7, #8] GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; 8002ccc: 887b ldrh r3, [r7, #2] 8002cce: ea4f 03d3 mov.w r3, r3, lsr #3 8002cd2: b29b uxth r3, r3 8002cd4: 461a mov r2, r3 8002cd6: 687b ldr r3, [r7, #4] 8002cd8: f102 0208 add.w r2, r2, #8 8002cdc: 68b9 ldr r1, [r7, #8] 8002cde: f843 1022 str.w r1, [r3, r2, lsl #2] } 8002ce2: f107 0714 add.w r7, r7, #20 8002ce6: 46bd mov sp, r7 8002ce8: bc80 pop {r7} 8002cea: 4770 bx lr 8002cec: 0000 movs r0, r0 ... 08002cf0 : #include "stepper.h" #include "planner.h" // Execute dwell in seconds. Maximum time delay is > 18 hours, more than enough for any application. void mc_dwell(double seconds) { 8002cf0: b580 push {r7, lr} 8002cf2: b084 sub sp, #16 8002cf4: af00 add r7, sp, #0 8002cf6: e9c7 0100 strd r0, r1, [r7] uint16_t i = floor(seconds); 8002cfa: e9d7 0100 ldrd r0, r1, [r7] 8002cfe: f002 ee80 blx 8005a00 8002d02: 4602 mov r2, r0 8002d04: 460b mov r3, r1 8002d06: 4610 mov r0, r2 8002d08: 4619 mov r1, r3 8002d0a: f006 fa2b bl 8009164 <__aeabi_d2uiz> 8002d0e: 4603 mov r3, r0 8002d10: 81fb strh r3, [r7, #14] st_synchronize(); 8002d12: f7ff f8ff bl 8001f14 delay_ms(floor(1000*(seconds-i))); // Delay millisecond remainder 8002d16: 89fb ldrh r3, [r7, #14] 8002d18: 4618 mov r0, r3 8002d1a: f005 fefb bl 8008b14 <__aeabi_i2d> 8002d1e: 4602 mov r2, r0 8002d20: 460b mov r3, r1 8002d22: e9d7 0100 ldrd r0, r1, [r7] 8002d26: f005 fda7 bl 8008878 <__aeabi_dsub> 8002d2a: 4602 mov r2, r0 8002d2c: 460b mov r3, r1 8002d2e: 4610 mov r0, r2 8002d30: 4619 mov r1, r3 8002d32: a313 add r3, pc, #76 ; (adr r3, 8002d80 ) 8002d34: e9d3 2300 ldrd r2, r3, [r3] 8002d38: f005 ff52 bl 8008be0 <__aeabi_dmul> 8002d3c: 4602 mov r2, r0 8002d3e: 460b mov r3, r1 8002d40: 4610 mov r0, r2 8002d42: 4619 mov r1, r3 8002d44: f002 ee5c blx 8005a00 8002d48: 4602 mov r2, r0 8002d4a: 460b mov r3, r1 8002d4c: 4610 mov r0, r2 8002d4e: 4619 mov r1, r3 8002d50: f006 fa08 bl 8009164 <__aeabi_d2uiz> 8002d54: 4603 mov r3, r0 8002d56: b29b uxth r3, r3 8002d58: 4618 mov r0, r3 8002d5a: f7ff fe7f bl 8002a5c while (i > 0) { 8002d5e: e007 b.n 8002d70 delay_ms(1000); // Delay one second 8002d60: f44f 707a mov.w r0, #1000 ; 0x3e8 8002d64: f7ff fe7a bl 8002a5c i--; 8002d68: 89fb ldrh r3, [r7, #14] 8002d6a: f103 33ff add.w r3, r3, #4294967295 8002d6e: 81fb strh r3, [r7, #14] void mc_dwell(double seconds) { uint16_t i = floor(seconds); st_synchronize(); delay_ms(floor(1000*(seconds-i))); // Delay millisecond remainder while (i > 0) { 8002d70: 89fb ldrh r3, [r7, #14] 8002d72: 2b00 cmp r3, #0 8002d74: d1f4 bne.n 8002d60 delay_ms(1000); // Delay one second i--; } } 8002d76: f107 0710 add.w r7, r7, #16 8002d7a: 46bd mov sp, r7 8002d7c: bd80 pop {r7, pc} 8002d7e: bf00 nop 8002d80: 00000000 .word 0x00000000 8002d84: 408f4000 .word 0x408f4000 08002d88 : // The arc is approximated by generating a huge number of tiny, linear segments. The length of each // segment is configured in settings.mm_per_arc_segment. void mc_arc(double *position, double *target, double *offset, uint8_t axis_0, uint8_t axis_1, uint8_t axis_linear, double feed_rate, uint8_t invert_feed_rate, double radius, uint8_t isclockwise) { 8002d88: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8002d8c: b0b7 sub sp, #220 ; 0xdc 8002d8e: af06 add r7, sp, #24 8002d90: 6178 str r0, [r7, #20] 8002d92: 6139 str r1, [r7, #16] 8002d94: 60fa str r2, [r7, #12] 8002d96: 72fb strb r3, [r7, #11] double center_axis0 = position[axis_0] + offset[axis_0]; 8002d98: 7afb ldrb r3, [r7, #11] 8002d9a: ea4f 03c3 mov.w r3, r3, lsl #3 8002d9e: 697a ldr r2, [r7, #20] 8002da0: 18d3 adds r3, r2, r3 8002da2: e9d3 0100 ldrd r0, r1, [r3] 8002da6: 7afb ldrb r3, [r7, #11] 8002da8: ea4f 03c3 mov.w r3, r3, lsl #3 8002dac: 68fa ldr r2, [r7, #12] 8002dae: 18d3 adds r3, r2, r3 8002db0: e9d3 2300 ldrd r2, r3, [r3] 8002db4: f005 fd62 bl 800887c <__adddf3> 8002db8: 4602 mov r2, r0 8002dba: 460b mov r3, r1 8002dbc: e9c7 2326 strd r2, r3, [r7, #152] ; 0x98 double center_axis1 = position[axis_1] + offset[axis_1]; 8002dc0: f897 30e8 ldrb.w r3, [r7, #232] ; 0xe8 8002dc4: ea4f 03c3 mov.w r3, r3, lsl #3 8002dc8: 697a ldr r2, [r7, #20] 8002dca: 18d3 adds r3, r2, r3 8002dcc: e9d3 0100 ldrd r0, r1, [r3] 8002dd0: f897 30e8 ldrb.w r3, [r7, #232] ; 0xe8 8002dd4: ea4f 03c3 mov.w r3, r3, lsl #3 8002dd8: 68fa ldr r2, [r7, #12] 8002dda: 18d3 adds r3, r2, r3 8002ddc: e9d3 2300 ldrd r2, r3, [r3] 8002de0: f005 fd4c bl 800887c <__adddf3> 8002de4: 4602 mov r2, r0 8002de6: 460b mov r3, r1 8002de8: e9c7 2324 strd r2, r3, [r7, #144] ; 0x90 double linear_travel = target[axis_linear] - position[axis_linear]; 8002dec: f897 30ec ldrb.w r3, [r7, #236] ; 0xec 8002df0: ea4f 03c3 mov.w r3, r3, lsl #3 8002df4: 693a ldr r2, [r7, #16] 8002df6: 18d3 adds r3, r2, r3 8002df8: e9d3 0100 ldrd r0, r1, [r3] 8002dfc: f897 30ec ldrb.w r3, [r7, #236] ; 0xec 8002e00: ea4f 03c3 mov.w r3, r3, lsl #3 8002e04: 697a ldr r2, [r7, #20] 8002e06: 18d3 adds r3, r2, r3 8002e08: e9d3 2300 ldrd r2, r3, [r3] 8002e0c: f005 fd34 bl 8008878 <__aeabi_dsub> 8002e10: 4602 mov r2, r0 8002e12: 460b mov r3, r1 8002e14: e9c7 2322 strd r2, r3, [r7, #136] ; 0x88 double r_axis0 = -offset[axis_0]; // Radius vector from center to current location 8002e18: 7afb ldrb r3, [r7, #11] 8002e1a: ea4f 03c3 mov.w r3, r3, lsl #3 8002e1e: 68fa ldr r2, [r7, #12] 8002e20: 18d3 adds r3, r2, r3 8002e22: e9d3 2300 ldrd r2, r3, [r3] 8002e26: 4611 mov r1, r2 8002e28: f8c7 10b8 str.w r1, [r7, #184] ; 0xb8 8002e2c: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 8002e30: f8c7 30bc str.w r3, [r7, #188] ; 0xbc double r_axis1 = -offset[axis_1]; 8002e34: f897 30e8 ldrb.w r3, [r7, #232] ; 0xe8 8002e38: ea4f 03c3 mov.w r3, r3, lsl #3 8002e3c: 68fa ldr r2, [r7, #12] 8002e3e: 18d3 adds r3, r2, r3 8002e40: e9d3 2300 ldrd r2, r3, [r3] 8002e44: 4611 mov r1, r2 8002e46: f8c7 10b0 str.w r1, [r7, #176] ; 0xb0 8002e4a: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 8002e4e: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 double rt_axis0 = target[axis_0] - center_axis0; 8002e52: 7afb ldrb r3, [r7, #11] 8002e54: ea4f 03c3 mov.w r3, r3, lsl #3 8002e58: 693a ldr r2, [r7, #16] 8002e5a: 18d3 adds r3, r2, r3 8002e5c: e9d3 2300 ldrd r2, r3, [r3] 8002e60: 4610 mov r0, r2 8002e62: 4619 mov r1, r3 8002e64: e9d7 2326 ldrd r2, r3, [r7, #152] ; 0x98 8002e68: f005 fd06 bl 8008878 <__aeabi_dsub> 8002e6c: 4602 mov r2, r0 8002e6e: 460b mov r3, r1 8002e70: e9c7 2320 strd r2, r3, [r7, #128] ; 0x80 double rt_axis1 = target[axis_1] - center_axis1; 8002e74: f897 30e8 ldrb.w r3, [r7, #232] ; 0xe8 8002e78: ea4f 03c3 mov.w r3, r3, lsl #3 8002e7c: 693a ldr r2, [r7, #16] 8002e7e: 18d3 adds r3, r2, r3 8002e80: e9d3 2300 ldrd r2, r3, [r3] 8002e84: 4610 mov r0, r2 8002e86: 4619 mov r1, r3 8002e88: e9d7 2324 ldrd r2, r3, [r7, #144] ; 0x90 8002e8c: f005 fcf4 bl 8008878 <__aeabi_dsub> 8002e90: 4602 mov r2, r0 8002e92: 460b mov r3, r1 8002e94: e9c7 231e strd r2, r3, [r7, #120] ; 0x78 // CCW angle between position and target from circle center. Only one atan2() trig computation required. double angular_travel = atan2(r_axis0*rt_axis1-r_axis1*rt_axis0, r_axis0*rt_axis0+r_axis1*rt_axis1); 8002e98: e9d7 012e ldrd r0, r1, [r7, #184] ; 0xb8 8002e9c: e9d7 231e ldrd r2, r3, [r7, #120] ; 0x78 8002ea0: f005 fe9e bl 8008be0 <__aeabi_dmul> 8002ea4: 4602 mov r2, r0 8002ea6: 460b mov r3, r1 8002ea8: 4692 mov sl, r2 8002eaa: 469b mov fp, r3 8002eac: e9d7 012c ldrd r0, r1, [r7, #176] ; 0xb0 8002eb0: e9d7 2320 ldrd r2, r3, [r7, #128] ; 0x80 8002eb4: f005 fe94 bl 8008be0 <__aeabi_dmul> 8002eb8: 4602 mov r2, r0 8002eba: 460b mov r3, r1 8002ebc: 4650 mov r0, sl 8002ebe: 4659 mov r1, fp 8002ec0: f005 fcda bl 8008878 <__aeabi_dsub> 8002ec4: 4602 mov r2, r0 8002ec6: 460b mov r3, r1 8002ec8: 4692 mov sl, r2 8002eca: 469b mov fp, r3 8002ecc: e9d7 012e ldrd r0, r1, [r7, #184] ; 0xb8 8002ed0: e9d7 2320 ldrd r2, r3, [r7, #128] ; 0x80 8002ed4: f005 fe84 bl 8008be0 <__aeabi_dmul> 8002ed8: 4602 mov r2, r0 8002eda: 460b mov r3, r1 8002edc: e9c7 2300 strd r2, r3, [r7] 8002ee0: e9d7 012c ldrd r0, r1, [r7, #176] ; 0xb0 8002ee4: e9d7 231e ldrd r2, r3, [r7, #120] ; 0x78 8002ee8: f005 fe7a bl 8008be0 <__aeabi_dmul> 8002eec: 4602 mov r2, r0 8002eee: 460b mov r3, r1 8002ef0: e9d7 0100 ldrd r0, r1, [r7] 8002ef4: f005 fcc2 bl 800887c <__adddf3> 8002ef8: 4602 mov r2, r0 8002efa: 460b mov r3, r1 8002efc: 4650 mov r0, sl 8002efe: 4659 mov r1, fp 8002f00: f003 e826 blx 8005f50 8002f04: 4602 mov r2, r0 8002f06: 460b mov r3, r1 8002f08: e9c7 232a strd r2, r3, [r7, #168] ; 0xa8 if (angular_travel < 0) { angular_travel += 2*M_PI; } 8002f0c: f04f 0301 mov.w r3, #1 8002f10: 461e mov r6, r3 8002f12: e9d7 012a ldrd r0, r1, [r7, #168] ; 0xa8 8002f16: f20f 4330 addw r3, pc, #1072 ; 0x430 8002f1a: e9d3 2300 ldrd r2, r3, [r3] 8002f1e: f006 f8d1 bl 80090c4 <__aeabi_dcmplt> 8002f22: 4603 mov r3, r0 8002f24: 2b00 cmp r3, #0 8002f26: d102 bne.n 8002f2e 8002f28: f04f 0300 mov.w r3, #0 8002f2c: 461e mov r6, r3 8002f2e: b2f3 uxtb r3, r6 8002f30: 2b00 cmp r3, #0 8002f32: d00b beq.n 8002f4c 8002f34: e9d7 012a ldrd r0, r1, [r7, #168] ; 0xa8 8002f38: f20f 4314 addw r3, pc, #1044 ; 0x414 8002f3c: e9d3 2300 ldrd r2, r3, [r3] 8002f40: f005 fc9c bl 800887c <__adddf3> 8002f44: 4602 mov r2, r0 8002f46: 460b mov r3, r1 8002f48: e9c7 232a strd r2, r3, [r7, #168] ; 0xa8 if (isclockwise) { angular_travel -= 2*M_PI; } 8002f4c: f897 3108 ldrb.w r3, [r7, #264] ; 0x108 8002f50: 2b00 cmp r3, #0 8002f52: d00a beq.n 8002f6a 8002f54: e9d7 012a ldrd r0, r1, [r7, #168] ; 0xa8 8002f58: a3fd add r3, pc, #1012 ; (adr r3, 8003350 ) 8002f5a: e9d3 2300 ldrd r2, r3, [r3] 8002f5e: f005 fc8b bl 8008878 <__aeabi_dsub> 8002f62: 4602 mov r2, r0 8002f64: 460b mov r3, r1 8002f66: e9c7 232a strd r2, r3, [r7, #168] ; 0xa8 double millimeters_of_travel = hypot(angular_travel*radius, fabs(linear_travel)); 8002f6a: e9d7 012a ldrd r0, r1, [r7, #168] ; 0xa8 8002f6e: e9d7 2340 ldrd r2, r3, [r7, #256] ; 0x100 8002f72: f005 fe35 bl 8008be0 <__aeabi_dmul> 8002f76: 4602 mov r2, r0 8002f78: 460b mov r3, r1 8002f7a: 4610 mov r0, r2 8002f7c: 4619 mov r1, r3 8002f7e: e9d7 2322 ldrd r2, r3, [r7, #136] ; 0x88 8002f82: f002 efee blx 8005f60 8002f86: 4602 mov r2, r0 8002f88: 460b mov r3, r1 8002f8a: e9c7 231c strd r2, r3, [r7, #112] ; 0x70 if (millimeters_of_travel == 0.0) { return; } 8002f8e: e9d7 011c ldrd r0, r1, [r7, #112] ; 0x70 8002f92: a3ed add r3, pc, #948 ; (adr r3, 8003348 ) 8002f94: e9d3 2300 ldrd r2, r3, [r3] 8002f98: f006 f88a bl 80090b0 <__aeabi_dcmpeq> 8002f9c: 4603 mov r3, r0 8002f9e: 2b00 cmp r3, #0 8002fa0: f040 81cb bne.w 800333a uint16_t segments = floor(millimeters_of_travel/settings.mm_per_arc_segment); 8002fa4: f240 63d8 movw r3, #1752 ; 0x6d8 8002fa8: f2c2 0300 movt r3, #8192 ; 0x2000 8002fac: e9d3 230e ldrd r2, r3, [r3, #56] ; 0x38 8002fb0: e9d7 011c ldrd r0, r1, [r7, #112] ; 0x70 8002fb4: f005 ff3e bl 8008e34 <__aeabi_ddiv> 8002fb8: 4602 mov r2, r0 8002fba: 460b mov r3, r1 8002fbc: 4610 mov r0, r2 8002fbe: 4619 mov r1, r3 8002fc0: f002 ed1e blx 8005a00 8002fc4: 4602 mov r2, r0 8002fc6: 460b mov r3, r1 8002fc8: 4610 mov r0, r2 8002fca: 4619 mov r1, r3 8002fcc: f006 f8ca bl 8009164 <__aeabi_d2uiz> 8002fd0: 4603 mov r3, r0 8002fd2: f8a7 306e strh.w r3, [r7, #110] ; 0x6e // Multiply inverse feed_rate to compensate for the fact that this movement is approximated // by a number of discrete segments. The inverse feed_rate should be correct for the sum of // all segments. if (invert_feed_rate) { feed_rate *= segments; } 8002fd6: f897 30f8 ldrb.w r3, [r7, #248] ; 0xf8 8002fda: 2b00 cmp r3, #0 8002fdc: d00e beq.n 8002ffc 8002fde: f8b7 306e ldrh.w r3, [r7, #110] ; 0x6e 8002fe2: 4618 mov r0, r3 8002fe4: f005 fd96 bl 8008b14 <__aeabi_i2d> 8002fe8: 4602 mov r2, r0 8002fea: 460b mov r3, r1 8002fec: e9d7 013c ldrd r0, r1, [r7, #240] ; 0xf0 8002ff0: f005 fdf6 bl 8008be0 <__aeabi_dmul> 8002ff4: 4602 mov r2, r0 8002ff6: 460b mov r3, r1 8002ff8: e9c7 233c strd r2, r3, [r7, #240] ; 0xf0 double theta_per_segment = angular_travel/segments; 8002ffc: f8b7 306e ldrh.w r3, [r7, #110] ; 0x6e 8003000: 4618 mov r0, r3 8003002: f005 fd87 bl 8008b14 <__aeabi_i2d> 8003006: 4602 mov r2, r0 8003008: 460b mov r3, r1 800300a: e9d7 012a ldrd r0, r1, [r7, #168] ; 0xa8 800300e: f005 ff11 bl 8008e34 <__aeabi_ddiv> 8003012: 4602 mov r2, r0 8003014: 460b mov r3, r1 8003016: e9c7 2318 strd r2, r3, [r7, #96] ; 0x60 double linear_per_segment = linear_travel/segments; 800301a: f8b7 306e ldrh.w r3, [r7, #110] ; 0x6e 800301e: 4618 mov r0, r3 8003020: f005 fd78 bl 8008b14 <__aeabi_i2d> 8003024: 4602 mov r2, r0 8003026: 460b mov r3, r1 8003028: e9d7 0122 ldrd r0, r1, [r7, #136] ; 0x88 800302c: f005 ff02 bl 8008e34 <__aeabi_ddiv> 8003030: 4602 mov r2, r0 8003032: 460b mov r3, r1 8003034: e9c7 2316 strd r2, r3, [r7, #88] ; 0x58 without the initial overhead of computing cos() or sin(). By the time the arc needs to be applied a correction, the planner should have caught up to the lag caused by the initial mc_arc overhead. This is important when there are successive arc motions. */ // Vector rotation matrix values double cos_T = 1-0.5*theta_per_segment*theta_per_segment; // Small angle approximation 8003038: e9d7 0118 ldrd r0, r1, [r7, #96] ; 0x60 800303c: a3c6 add r3, pc, #792 ; (adr r3, 8003358 ) 800303e: e9d3 2300 ldrd r2, r3, [r3] 8003042: f005 fdcd bl 8008be0 <__aeabi_dmul> 8003046: 4602 mov r2, r0 8003048: 460b mov r3, r1 800304a: 4610 mov r0, r2 800304c: 4619 mov r1, r3 800304e: e9d7 2318 ldrd r2, r3, [r7, #96] ; 0x60 8003052: f005 fdc5 bl 8008be0 <__aeabi_dmul> 8003056: 4602 mov r2, r0 8003058: 460b mov r3, r1 800305a: a1c1 add r1, pc, #772 ; (adr r1, 8003360 ) 800305c: e9d1 0100 ldrd r0, r1, [r1] 8003060: f005 fc0a bl 8008878 <__aeabi_dsub> 8003064: 4602 mov r2, r0 8003066: 460b mov r3, r1 8003068: e9c7 2314 strd r2, r3, [r7, #80] ; 0x50 double sin_T = theta_per_segment; 800306c: e9d7 2318 ldrd r2, r3, [r7, #96] ; 0x60 8003070: e9c7 2312 strd r2, r3, [r7, #72] ; 0x48 double arc_target[3]; double sin_Ti; double cos_Ti; double r_axisi; uint16_t i; int8_t count = 0; 8003074: f04f 0300 mov.w r3, #0 8003078: f887 30a5 strb.w r3, [r7, #165] ; 0xa5 // Initialize the linear axis arc_target[axis_linear] = position[axis_linear]; 800307c: f897 10ec ldrb.w r1, [r7, #236] ; 0xec 8003080: f897 30ec ldrb.w r3, [r7, #236] ; 0xec 8003084: ea4f 03c3 mov.w r3, r3, lsl #3 8003088: 697a ldr r2, [r7, #20] 800308a: 18d3 adds r3, r2, r3 800308c: e9d3 2300 ldrd r2, r3, [r3] 8003090: ea4f 01c1 mov.w r1, r1, lsl #3 8003094: f107 00c0 add.w r0, r7, #192 ; 0xc0 8003098: 1841 adds r1, r0, r1 800309a: f1a1 01a8 sub.w r1, r1, #168 ; 0xa8 800309e: e9c1 2300 strd r2, r3, [r1] for (i = 1; i if (count < N_ARC_CORRECTION) { 80030ac: f997 30a5 ldrsb.w r3, [r7, #165] ; 0xa5 80030b0: 2b18 cmp r3, #24 80030b2: dc3e bgt.n 8003132 // Apply vector rotation matrix r_axisi = r_axis0*sin_T + r_axis1*cos_T; 80030b4: e9d7 012e ldrd r0, r1, [r7, #184] ; 0xb8 80030b8: e9d7 2312 ldrd r2, r3, [r7, #72] ; 0x48 80030bc: f005 fd90 bl 8008be0 <__aeabi_dmul> 80030c0: 4602 mov r2, r0 80030c2: 460b mov r3, r1 80030c4: 4692 mov sl, r2 80030c6: 469b mov fp, r3 80030c8: e9d7 012c ldrd r0, r1, [r7, #176] ; 0xb0 80030cc: e9d7 2314 ldrd r2, r3, [r7, #80] ; 0x50 80030d0: f005 fd86 bl 8008be0 <__aeabi_dmul> 80030d4: 4602 mov r2, r0 80030d6: 460b mov r3, r1 80030d8: 4650 mov r0, sl 80030da: 4659 mov r1, fp 80030dc: f005 fbce bl 800887c <__adddf3> 80030e0: 4602 mov r2, r0 80030e2: 460b mov r3, r1 80030e4: e9c7 2310 strd r2, r3, [r7, #64] ; 0x40 r_axis0 = r_axis0*cos_T - r_axis1*sin_T; 80030e8: e9d7 012e ldrd r0, r1, [r7, #184] ; 0xb8 80030ec: e9d7 2314 ldrd r2, r3, [r7, #80] ; 0x50 80030f0: f005 fd76 bl 8008be0 <__aeabi_dmul> 80030f4: 4602 mov r2, r0 80030f6: 460b mov r3, r1 80030f8: 4692 mov sl, r2 80030fa: 469b mov fp, r3 80030fc: e9d7 012c ldrd r0, r1, [r7, #176] ; 0xb0 8003100: e9d7 2312 ldrd r2, r3, [r7, #72] ; 0x48 8003104: f005 fd6c bl 8008be0 <__aeabi_dmul> 8003108: 4602 mov r2, r0 800310a: 460b mov r3, r1 800310c: 4650 mov r0, sl 800310e: 4659 mov r1, fp 8003110: f005 fbb2 bl 8008878 <__aeabi_dsub> 8003114: 4602 mov r2, r0 8003116: 460b mov r3, r1 8003118: e9c7 232e strd r2, r3, [r7, #184] ; 0xb8 r_axis1 = r_axisi; 800311c: e9d7 2310 ldrd r2, r3, [r7, #64] ; 0x40 8003120: e9c7 232c strd r2, r3, [r7, #176] ; 0xb0 count++; 8003124: f897 30a5 ldrb.w r3, [r7, #165] ; 0xa5 8003128: f103 0301 add.w r3, r3, #1 800312c: f887 30a5 strb.w r3, [r7, #165] ; 0xa5 8003130: e089 b.n 8003246 } else { // Arc correction to radius vector. Computed only every N_ARC_CORRECTION increments. // Compute exact location by applying transformation matrix from initial radius vector(=-offset). cos_Ti = cos(i*theta_per_segment); 8003132: f8b7 30a6 ldrh.w r3, [r7, #166] ; 0xa6 8003136: 4618 mov r0, r3 8003138: f005 fcec bl 8008b14 <__aeabi_i2d> 800313c: 4602 mov r2, r0 800313e: 460b mov r3, r1 8003140: 4610 mov r0, r2 8003142: 4619 mov r1, r3 8003144: e9d7 2318 ldrd r2, r3, [r7, #96] ; 0x60 8003148: f005 fd4a bl 8008be0 <__aeabi_dmul> 800314c: 4602 mov r2, r0 800314e: 460b mov r3, r1 8003150: 4610 mov r0, r2 8003152: 4619 mov r1, r3 8003154: f002 ebd8 blx 8005908 8003158: 4602 mov r2, r0 800315a: 460b mov r3, r1 800315c: e9c7 230e strd r2, r3, [r7, #56] ; 0x38 sin_Ti = sin(i*theta_per_segment); 8003160: f8b7 30a6 ldrh.w r3, [r7, #166] ; 0xa6 8003164: 4618 mov r0, r3 8003166: f005 fcd5 bl 8008b14 <__aeabi_i2d> 800316a: 4602 mov r2, r0 800316c: 460b mov r3, r1 800316e: 4610 mov r0, r2 8003170: 4619 mov r1, r3 8003172: e9d7 2318 ldrd r2, r3, [r7, #96] ; 0x60 8003176: f005 fd33 bl 8008be0 <__aeabi_dmul> 800317a: 4602 mov r2, r0 800317c: 460b mov r3, r1 800317e: 4610 mov r0, r2 8003180: 4619 mov r1, r3 8003182: f002 ee00 blx 8005d84 8003186: 4602 mov r2, r0 8003188: 460b mov r3, r1 800318a: e9c7 230c strd r2, r3, [r7, #48] ; 0x30 r_axis0 = -offset[axis_0]*cos_Ti + offset[axis_1]*sin_Ti; 800318e: 7afb ldrb r3, [r7, #11] 8003190: ea4f 03c3 mov.w r3, r3, lsl #3 8003194: 68fa ldr r2, [r7, #12] 8003196: 18d3 adds r3, r2, r3 8003198: e9d3 2300 ldrd r2, r3, [r3] 800319c: 4614 mov r4, r2 800319e: f083 4500 eor.w r5, r3, #2147483648 ; 0x80000000 80031a2: 4620 mov r0, r4 80031a4: 4629 mov r1, r5 80031a6: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38 80031aa: f005 fd19 bl 8008be0 <__aeabi_dmul> 80031ae: 4602 mov r2, r0 80031b0: 460b mov r3, r1 80031b2: 4692 mov sl, r2 80031b4: 469b mov fp, r3 80031b6: f897 30e8 ldrb.w r3, [r7, #232] ; 0xe8 80031ba: ea4f 03c3 mov.w r3, r3, lsl #3 80031be: 68fa ldr r2, [r7, #12] 80031c0: 18d3 adds r3, r2, r3 80031c2: e9d3 2300 ldrd r2, r3, [r3] 80031c6: 4610 mov r0, r2 80031c8: 4619 mov r1, r3 80031ca: e9d7 230c ldrd r2, r3, [r7, #48] ; 0x30 80031ce: f005 fd07 bl 8008be0 <__aeabi_dmul> 80031d2: 4602 mov r2, r0 80031d4: 460b mov r3, r1 80031d6: 4650 mov r0, sl 80031d8: 4659 mov r1, fp 80031da: f005 fb4f bl 800887c <__adddf3> 80031de: 4602 mov r2, r0 80031e0: 460b mov r3, r1 80031e2: e9c7 232e strd r2, r3, [r7, #184] ; 0xb8 r_axis1 = -offset[axis_0]*sin_Ti - offset[axis_1]*cos_Ti; 80031e6: 7afb ldrb r3, [r7, #11] 80031e8: ea4f 03c3 mov.w r3, r3, lsl #3 80031ec: 68fa ldr r2, [r7, #12] 80031ee: 18d3 adds r3, r2, r3 80031f0: e9d3 2300 ldrd r2, r3, [r3] 80031f4: 4690 mov r8, r2 80031f6: f083 4900 eor.w r9, r3, #2147483648 ; 0x80000000 80031fa: 4640 mov r0, r8 80031fc: 4649 mov r1, r9 80031fe: e9d7 230c ldrd r2, r3, [r7, #48] ; 0x30 8003202: f005 fced bl 8008be0 <__aeabi_dmul> 8003206: 4602 mov r2, r0 8003208: 460b mov r3, r1 800320a: 4692 mov sl, r2 800320c: 469b mov fp, r3 800320e: f897 30e8 ldrb.w r3, [r7, #232] ; 0xe8 8003212: ea4f 03c3 mov.w r3, r3, lsl #3 8003216: 68fa ldr r2, [r7, #12] 8003218: 18d3 adds r3, r2, r3 800321a: e9d3 2300 ldrd r2, r3, [r3] 800321e: 4610 mov r0, r2 8003220: 4619 mov r1, r3 8003222: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38 8003226: f005 fcdb bl 8008be0 <__aeabi_dmul> 800322a: 4602 mov r2, r0 800322c: 460b mov r3, r1 800322e: 4650 mov r0, sl 8003230: 4659 mov r1, fp 8003232: f005 fb21 bl 8008878 <__aeabi_dsub> 8003236: 4602 mov r2, r0 8003238: 460b mov r3, r1 800323a: e9c7 232c strd r2, r3, [r7, #176] ; 0xb0 count = 0; 800323e: f04f 0300 mov.w r3, #0 8003242: f887 30a5 strb.w r3, [r7, #165] ; 0xa5 } // Update arc_target location arc_target[axis_0] = center_axis0 + r_axis0; 8003246: 7afe ldrb r6, [r7, #11] 8003248: e9d7 0126 ldrd r0, r1, [r7, #152] ; 0x98 800324c: e9d7 232e ldrd r2, r3, [r7, #184] ; 0xb8 8003250: f005 fb14 bl 800887c <__adddf3> 8003254: 4602 mov r2, r0 8003256: 460b mov r3, r1 8003258: ea4f 01c6 mov.w r1, r6, lsl #3 800325c: f107 00c0 add.w r0, r7, #192 ; 0xc0 8003260: 1841 adds r1, r0, r1 8003262: f1a1 01a8 sub.w r1, r1, #168 ; 0xa8 8003266: e9c1 2300 strd r2, r3, [r1] arc_target[axis_1] = center_axis1 + r_axis1; 800326a: f897 60e8 ldrb.w r6, [r7, #232] ; 0xe8 800326e: e9d7 0124 ldrd r0, r1, [r7, #144] ; 0x90 8003272: e9d7 232c ldrd r2, r3, [r7, #176] ; 0xb0 8003276: f005 fb01 bl 800887c <__adddf3> 800327a: 4602 mov r2, r0 800327c: 460b mov r3, r1 800327e: ea4f 01c6 mov.w r1, r6, lsl #3 8003282: f107 00c0 add.w r0, r7, #192 ; 0xc0 8003286: 1841 adds r1, r0, r1 8003288: f1a1 01a8 sub.w r1, r1, #168 ; 0xa8 800328c: e9c1 2300 strd r2, r3, [r1] arc_target[axis_linear] += linear_per_segment; 8003290: f897 60ec ldrb.w r6, [r7, #236] ; 0xec 8003294: f897 30ec ldrb.w r3, [r7, #236] ; 0xec 8003298: ea4f 03c3 mov.w r3, r3, lsl #3 800329c: f107 02c0 add.w r2, r7, #192 ; 0xc0 80032a0: 18d3 adds r3, r2, r3 80032a2: f1a3 03a8 sub.w r3, r3, #168 ; 0xa8 80032a6: e9d3 2300 ldrd r2, r3, [r3] 80032aa: 4610 mov r0, r2 80032ac: 4619 mov r1, r3 80032ae: e9d7 2316 ldrd r2, r3, [r7, #88] ; 0x58 80032b2: f005 fae3 bl 800887c <__adddf3> 80032b6: 4602 mov r2, r0 80032b8: 460b mov r3, r1 80032ba: ea4f 01c6 mov.w r1, r6, lsl #3 80032be: f107 00c0 add.w r0, r7, #192 ; 0xc0 80032c2: 1841 adds r1, r0, r1 80032c4: f1a1 01a8 sub.w r1, r1, #168 ; 0xa8 80032c8: e9c1 2300 strd r2, r3, [r1] plan_buffer_line(arc_target[X_AXIS], arc_target[Y_AXIS], arc_target[Z_AXIS], feed_rate, invert_feed_rate); 80032cc: e9d7 0106 ldrd r0, r1, [r7, #24] 80032d0: e9d7 2308 ldrd r2, r3, [r7, #32] 80032d4: e9d7 ab0a ldrd sl, fp, [r7, #40] ; 0x28 80032d8: e9cd ab00 strd sl, fp, [sp] 80032dc: e9d7 ab3c ldrd sl, fp, [r7, #240] ; 0xf0 80032e0: e9cd ab02 strd sl, fp, [sp, #8] 80032e4: f897 60f8 ldrb.w r6, [r7, #248] ; 0xf8 80032e8: 9604 str r6, [sp, #16] 80032ea: f001 f855 bl 8004398 int8_t count = 0; // Initialize the linear axis arc_target[axis_linear] = position[axis_linear]; for (i = 1; i arc_target[axis_linear] += linear_per_segment; plan_buffer_line(arc_target[X_AXIS], arc_target[Y_AXIS], arc_target[Z_AXIS], feed_rate, invert_feed_rate); } // Ensure last segment arrives at target location. plan_buffer_line(target[X_AXIS], target[Y_AXIS], target[Z_AXIS], feed_rate, invert_feed_rate); 8003308: 693b ldr r3, [r7, #16] 800330a: e9d3 0100 ldrd r0, r1, [r3] 800330e: 693b ldr r3, [r7, #16] 8003310: f103 0308 add.w r3, r3, #8 8003314: e9d3 2300 ldrd r2, r3, [r3] 8003318: 693c ldr r4, [r7, #16] 800331a: f104 0410 add.w r4, r4, #16 800331e: e9d4 4500 ldrd r4, r5, [r4] 8003322: e9cd 4500 strd r4, r5, [sp] 8003326: e9d7 453c ldrd r4, r5, [r7, #240] ; 0xf0 800332a: e9cd 4502 strd r4, r5, [sp, #8] 800332e: f897 40f8 ldrb.w r4, [r7, #248] ; 0xf8 8003332: 9404 str r4, [sp, #16] 8003334: f001 f830 bl 8004398 8003338: e000 b.n 800333c double angular_travel = atan2(r_axis0*rt_axis1-r_axis1*rt_axis0, r_axis0*rt_axis0+r_axis1*rt_axis1); if (angular_travel < 0) { angular_travel += 2*M_PI; } if (isclockwise) { angular_travel -= 2*M_PI; } double millimeters_of_travel = hypot(angular_travel*radius, fabs(linear_travel)); if (millimeters_of_travel == 0.0) { return; } 800333a: bf00 nop plan_buffer_line(arc_target[X_AXIS], arc_target[Y_AXIS], arc_target[Z_AXIS], feed_rate, invert_feed_rate); } // Ensure last segment arrives at target location. plan_buffer_line(target[X_AXIS], target[Y_AXIS], target[Z_AXIS], feed_rate, invert_feed_rate); } 800333c: f107 07c4 add.w r7, r7, #196 ; 0xc4 8003340: 46bd mov sp, r7 8003342: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8003346: bf00 nop ... 8003350: 54442d18 .word 0x54442d18 8003354: 401921fb .word 0x401921fb 8003358: 00000000 .word 0x00000000 800335c: 3fe00000 .word 0x3fe00000 8003360: 00000000 .word 0x00000000 8003364: 3ff00000 .word 0x3ff00000 08003368 : void mc_go_home() { 8003368: b580 push {r7, lr} 800336a: af00 add r7, sp, #0 st_go_home(); 800336c: f7fe feb4 bl 80020d8 } 8003370: bd80 pop {r7, pc} 8003372: bf00 nop 8003374: 0000 movs r0, r0 ... 08003378 : #define DEFAULT_FEEDRATE 500.0 #define DEFAULT_ACCELERATION (DEFAULT_FEEDRATE*60*60/10.0) // mm/min^2 #define DEFAULT_JUNCTION_DEVIATION 0.05 // mm #define DEFAULT_STEPPING_INVERT_MASK ((1<) 8003386: e9d1 0100 ldrd r0, r1, [r1] 800338a: e9c3 0100 strd r0, r1, [r3] settings.steps_per_mm[Y_AXIS] = DEFAULT_Y_STEPS_PER_MM; 800338e: f240 63d8 movw r3, #1752 ; 0x6d8 8003392: f2c2 0300 movt r3, #8192 ; 0x2000 8003396: a126 add r1, pc, #152 ; (adr r1, 8003430 ) 8003398: e9d1 0100 ldrd r0, r1, [r1] 800339c: e9c3 0102 strd r0, r1, [r3, #8] settings.steps_per_mm[Z_AXIS] = DEFAULT_Z_STEPS_PER_MM; 80033a0: f240 63d8 movw r3, #1752 ; 0x6d8 80033a4: f2c2 0300 movt r3, #8192 ; 0x2000 80033a8: a121 add r1, pc, #132 ; (adr r1, 8003430 ) 80033aa: e9d1 0100 ldrd r0, r1, [r1] 80033ae: e9c3 0104 strd r0, r1, [r3, #16] settings.pulse_microseconds = DEFAULT_STEP_PULSE_MICROSECONDS; 80033b2: f240 63d8 movw r3, #1752 ; 0x6d8 80033b6: f2c2 0300 movt r3, #8192 ; 0x2000 80033ba: f04f 021e mov.w r2, #30 80033be: 765a strb r2, [r3, #25] settings.default_feed_rate = DEFAULT_FEEDRATE; 80033c0: f240 63d8 movw r3, #1752 ; 0x6d8 80033c4: f2c2 0300 movt r3, #8192 ; 0x2000 80033c8: a11b add r1, pc, #108 ; (adr r1, 8003438 ) 80033ca: e9d1 0100 ldrd r0, r1, [r1] 80033ce: e9c3 0108 strd r0, r1, [r3, #32] settings.default_seek_rate = DEFAULT_RAPID_FEEDRATE; 80033d2: f240 63d8 movw r3, #1752 ; 0x6d8 80033d6: f2c2 0300 movt r3, #8192 ; 0x2000 80033da: a117 add r1, pc, #92 ; (adr r1, 8003438 ) 80033dc: e9d1 0100 ldrd r0, r1, [r1] 80033e0: e9c3 010a strd r0, r1, [r3, #40] ; 0x28 settings.acceleration = DEFAULT_ACCELERATION; 80033e4: f240 63d8 movw r3, #1752 ; 0x6d8 80033e8: f2c2 0300 movt r3, #8192 ; 0x2000 80033ec: a114 add r1, pc, #80 ; (adr r1, 8003440 ) 80033ee: e9d1 0100 ldrd r0, r1, [r1] 80033f2: e9c3 0110 strd r0, r1, [r3, #64] ; 0x40 settings.mm_per_arc_segment = DEFAULT_MM_PER_ARC_SEGMENT; 80033f6: f240 63d8 movw r3, #1752 ; 0x6d8 80033fa: f2c2 0300 movt r3, #8192 ; 0x2000 80033fe: a112 add r1, pc, #72 ; (adr r1, 8003448 ) 8003400: e9d1 0100 ldrd r0, r1, [r1] 8003404: e9c3 010e strd r0, r1, [r3, #56] ; 0x38 settings.invert_mask = DEFAULT_STEPPING_INVERT_MASK; 8003408: f240 63d8 movw r3, #1752 ; 0x6d8 800340c: f2c2 0300 movt r3, #8192 ; 0x2000 8003410: f44f 7288 mov.w r2, #272 ; 0x110 8003414: 861a strh r2, [r3, #48] ; 0x30 settings.junction_deviation = DEFAULT_JUNCTION_DEVIATION; 8003416: f240 63d8 movw r3, #1752 ; 0x6d8 800341a: f2c2 0300 movt r3, #8192 ; 0x2000 800341e: a10c add r1, pc, #48 ; (adr r1, 8003450 ) 8003420: e9d1 0100 ldrd r0, r1, [r1] 8003424: e9c3 0112 strd r0, r1, [r3, #72] ; 0x48 } 8003428: 46bd mov sp, r7 800342a: bc80 pop {r7} 800342c: 4770 bx lr 800342e: bf00 nop 8003430: 7cf9f3eb .word 0x7cf9f3eb 8003434: 40879f3e .word 0x40879f3e 8003438: 00000000 .word 0x00000000 800343c: 407f4000 .word 0x407f4000 8003440: 00000000 .word 0x00000000 8003444: 4105f900 .word 0x4105f900 8003448: 9999999a .word 0x9999999a 800344c: 3fb99999 .word 0x3fb99999 8003450: 9999999a .word 0x9999999a 8003454: 3fa99999 .word 0x3fa99999 08003458 : void settings_dump() { 8003458: b580 push {r7, lr} 800345a: af00 add r7, sp, #0 printPgmString("$0 = "); printFloat(settings.steps_per_mm[X_AXIS]); 800345c: f64a 3040 movw r0, #43840 ; 0xab40 8003460: f6c0 0000 movt r0, #2048 ; 0x800 8003464: f7fd f95a bl 800071c 8003468: f240 63d8 movw r3, #1752 ; 0x6d8 800346c: f2c2 0300 movt r3, #8192 ; 0x2000 8003470: e9d3 2300 ldrd r2, r3, [r3] 8003474: 4610 mov r0, r2 8003476: 4619 mov r1, r3 8003478: f7fd f9e2 bl 8000840 printPgmString(" (steps/mm x)\r\n$1 = "); printFloat(settings.steps_per_mm[Y_AXIS]); 800347c: f64a 3048 movw r0, #43848 ; 0xab48 8003480: f6c0 0000 movt r0, #2048 ; 0x800 8003484: f7fd f94a bl 800071c 8003488: f240 63d8 movw r3, #1752 ; 0x6d8 800348c: f2c2 0300 movt r3, #8192 ; 0x2000 8003490: e9d3 2302 ldrd r2, r3, [r3, #8] 8003494: 4610 mov r0, r2 8003496: 4619 mov r1, r3 8003498: f7fd f9d2 bl 8000840 printPgmString(" (steps/mm y)\r\n$2 = "); printFloat(settings.steps_per_mm[Z_AXIS]); 800349c: f64a 3060 movw r0, #43872 ; 0xab60 80034a0: f6c0 0000 movt r0, #2048 ; 0x800 80034a4: f7fd f93a bl 800071c 80034a8: f240 63d8 movw r3, #1752 ; 0x6d8 80034ac: f2c2 0300 movt r3, #8192 ; 0x2000 80034b0: e9d3 2304 ldrd r2, r3, [r3, #16] 80034b4: 4610 mov r0, r2 80034b6: 4619 mov r1, r3 80034b8: f7fd f9c2 bl 8000840 printPgmString(" (steps/mm z)\r\n$3 = "); printInteger(settings.pulse_microseconds); 80034bc: f64a 3078 movw r0, #43896 ; 0xab78 80034c0: f6c0 0000 movt r0, #2048 ; 0x800 80034c4: f7fd f92a bl 800071c 80034c8: f240 63d8 movw r3, #1752 ; 0x6d8 80034cc: f2c2 0300 movt r3, #8192 ; 0x2000 80034d0: 7e5b ldrb r3, [r3, #25] 80034d2: 4618 mov r0, r3 80034d4: f7fd f998 bl 8000808 printPgmString(" (microseconds step pulse)\r\n$4 = "); printFloat(settings.default_feed_rate); 80034d8: f64a 3090 movw r0, #43920 ; 0xab90 80034dc: f6c0 0000 movt r0, #2048 ; 0x800 80034e0: f7fd f91c bl 800071c 80034e4: f240 63d8 movw r3, #1752 ; 0x6d8 80034e8: f2c2 0300 movt r3, #8192 ; 0x2000 80034ec: e9d3 2308 ldrd r2, r3, [r3, #32] 80034f0: 4610 mov r0, r2 80034f2: 4619 mov r1, r3 80034f4: f7fd f9a4 bl 8000840 printPgmString(" (mm/min default feed rate)\r\n$5 = "); printFloat(settings.default_seek_rate); 80034f8: f64a 30b4 movw r0, #43956 ; 0xabb4 80034fc: f6c0 0000 movt r0, #2048 ; 0x800 8003500: f7fd f90c bl 800071c 8003504: f240 63d8 movw r3, #1752 ; 0x6d8 8003508: f2c2 0300 movt r3, #8192 ; 0x2000 800350c: e9d3 230a ldrd r2, r3, [r3, #40] ; 0x28 8003510: 4610 mov r0, r2 8003512: 4619 mov r1, r3 8003514: f7fd f994 bl 8000840 printPgmString(" (mm/min default seek rate)\r\n$6 = "); printFloat(settings.mm_per_arc_segment); 8003518: f64a 30d8 movw r0, #43992 ; 0xabd8 800351c: f6c0 0000 movt r0, #2048 ; 0x800 8003520: f7fd f8fc bl 800071c 8003524: f240 63d8 movw r3, #1752 ; 0x6d8 8003528: f2c2 0300 movt r3, #8192 ; 0x2000 800352c: e9d3 230e ldrd r2, r3, [r3, #56] ; 0x38 8003530: 4610 mov r0, r2 8003532: 4619 mov r1, r3 8003534: f7fd f984 bl 8000840 printPgmString(" (mm/arc segment)\r\n$7 = "); printInteger(settings.invert_mask); 8003538: f64a 30fc movw r0, #44028 ; 0xabfc 800353c: f6c0 0000 movt r0, #2048 ; 0x800 8003540: f7fd f8ec bl 800071c 8003544: f240 63d8 movw r3, #1752 ; 0x6d8 8003548: f2c2 0300 movt r3, #8192 ; 0x2000 800354c: 8e1b ldrh r3, [r3, #48] ; 0x30 800354e: 4618 mov r0, r3 8003550: f7fd f95a bl 8000808 printPgmString(" (step port invert mask. binary = "); printIntegerInBase(settings.invert_mask, 2); 8003554: f64a 4018 movw r0, #44056 ; 0xac18 8003558: f6c0 0000 movt r0, #2048 ; 0x800 800355c: f7fd f8de bl 800071c 8003560: f240 63d8 movw r3, #1752 ; 0x6d8 8003564: f2c2 0300 movt r3, #8192 ; 0x2000 8003568: 8e1b ldrh r3, [r3, #48] ; 0x30 800356a: 4618 mov r0, r3 800356c: f04f 0102 mov.w r1, #2 8003570: f7fd f8f0 bl 8000754 printPgmString(")\r\n$8 = "); printFloat(settings.acceleration/(60*60)); // Convert from mm/min^2 for human readability 8003574: f64a 403c movw r0, #44092 ; 0xac3c 8003578: f6c0 0000 movt r0, #2048 ; 0x800 800357c: f7fd f8ce bl 800071c 8003580: f240 63d8 movw r3, #1752 ; 0x6d8 8003584: f2c2 0300 movt r3, #8192 ; 0x2000 8003588: e9d3 2310 ldrd r2, r3, [r3, #64] ; 0x40 800358c: 4610 mov r0, r2 800358e: 4619 mov r1, r3 8003590: a313 add r3, pc, #76 ; (adr r3, 80035e0 ) 8003592: e9d3 2300 ldrd r2, r3, [r3] 8003596: f005 fc4d bl 8008e34 <__aeabi_ddiv> 800359a: 4602 mov r2, r0 800359c: 460b mov r3, r1 800359e: 4610 mov r0, r2 80035a0: 4619 mov r1, r3 80035a2: f7fd f94d bl 8000840 printPgmString(" (acceleration in mm/sec^2)\r\n$9 = "); printFloat(settings.junction_deviation); 80035a6: f64a 4048 movw r0, #44104 ; 0xac48 80035aa: f6c0 0000 movt r0, #2048 ; 0x800 80035ae: f7fd f8b5 bl 800071c 80035b2: f240 63d8 movw r3, #1752 ; 0x6d8 80035b6: f2c2 0300 movt r3, #8192 ; 0x2000 80035ba: e9d3 2312 ldrd r2, r3, [r3, #72] ; 0x48 80035be: 4610 mov r0, r2 80035c0: 4619 mov r1, r3 80035c2: f7fd f93d bl 8000840 printPgmString(" (cornering junction deviation in mm)"); 80035c6: f64a 406c movw r0, #44140 ; 0xac6c 80035ca: f6c0 0000 movt r0, #2048 ; 0x800 80035ce: f7fd f8a5 bl 800071c printPgmString("\r\n'$x=value' to set parameter or just '$' to dump current settings\r\n"); 80035d2: f64a 4094 movw r0, #44180 ; 0xac94 80035d6: f6c0 0000 movt r0, #2048 ; 0x800 80035da: f7fd f89f bl 800071c } 80035de: bd80 pop {r7, pc} 80035e0: 00000000 .word 0x00000000 80035e4: 40ac2000 .word 0x40ac2000 080035e8 : // Parameter lines are on the form '$4=374.3' or '$' to dump current settings uint8_t settings_execute_line(char *line) { 80035e8: b580 push {r7, lr} 80035ea: b088 sub sp, #32 80035ec: af00 add r7, sp, #0 80035ee: 6078 str r0, [r7, #4] uint8_t char_counter = 1; 80035f0: f04f 0301 mov.w r3, #1 80035f4: 77fb strb r3, [r7, #31] double parameter, value; if(line[0] != '$') { 80035f6: 687b ldr r3, [r7, #4] 80035f8: 781b ldrb r3, [r3, #0] 80035fa: 2b24 cmp r3, #36 ; 0x24 80035fc: d002 beq.n 8003604 return(STATUS_UNSUPPORTED_STATEMENT); 80035fe: f04f 0303 mov.w r3, #3 8003602: e052 b.n 80036aa } if(line[char_counter] == 0) { 8003604: 7ffb ldrb r3, [r7, #31] 8003606: 687a ldr r2, [r7, #4] 8003608: 18d3 adds r3, r2, r3 800360a: 781b ldrb r3, [r3, #0] 800360c: 2b00 cmp r3, #0 800360e: d104 bne.n 800361a settings_dump(); return(STATUS_OK); 8003610: f7ff ff22 bl 8003458 8003614: f04f 0300 mov.w r3, #0 8003618: e047 b.n 80036aa } if(!read_double(line, &char_counter, ¶meter)) { 800361a: f107 021f add.w r2, r7, #31 800361e: f107 0310 add.w r3, r7, #16 8003622: 6878 ldr r0, [r7, #4] 8003624: 4611 mov r1, r2 8003626: 461a mov r2, r3 8003628: f7fe ffe4 bl 80025f4 800362c: 4603 mov r3, r0 800362e: 2b00 cmp r3, #0 8003630: d102 bne.n 8003638 return(STATUS_BAD_NUMBER_FORMAT); 8003632: f04f 0301 mov.w r3, #1 8003636: e038 b.n 80036aa }; if(line[char_counter++] != '=') { 8003638: 7ffb ldrb r3, [r7, #31] 800363a: 461a mov r2, r3 800363c: 6879 ldr r1, [r7, #4] 800363e: 188a adds r2, r1, r2 8003640: 7812 ldrb r2, [r2, #0] 8003642: 2a3d cmp r2, #61 ; 0x3d 8003644: bf0c ite eq 8003646: 2200 moveq r2, #0 8003648: 2201 movne r2, #1 800364a: b2d2 uxtb r2, r2 800364c: f103 0301 add.w r3, r3, #1 8003650: b2db uxtb r3, r3 8003652: 77fb strb r3, [r7, #31] 8003654: 2a00 cmp r2, #0 8003656: d002 beq.n 800365e return(STATUS_UNSUPPORTED_STATEMENT); 8003658: f04f 0303 mov.w r3, #3 800365c: e025 b.n 80036aa } if(!read_double(line, &char_counter, &value)) { 800365e: f107 021f add.w r2, r7, #31 8003662: f107 0308 add.w r3, r7, #8 8003666: 6878 ldr r0, [r7, #4] 8003668: 4611 mov r1, r2 800366a: 461a mov r2, r3 800366c: f7fe ffc2 bl 80025f4 8003670: 4603 mov r3, r0 8003672: 2b00 cmp r3, #0 8003674: d102 bne.n 800367c return(STATUS_BAD_NUMBER_FORMAT); 8003676: f04f 0301 mov.w r3, #1 800367a: e016 b.n 80036aa } if(line[char_counter] != 0) { 800367c: 7ffb ldrb r3, [r7, #31] 800367e: 687a ldr r2, [r7, #4] 8003680: 18d3 adds r3, r2, r3 8003682: 781b ldrb r3, [r3, #0] 8003684: 2b00 cmp r3, #0 8003686: d002 beq.n 800368e return(STATUS_UNSUPPORTED_STATEMENT); 8003688: f04f 0303 mov.w r3, #3 800368c: e00d b.n 80036aa } settings_store_setting(parameter, value); 800368e: e9d7 2304 ldrd r2, r3, [r7, #16] 8003692: 4610 mov r0, r2 8003694: 4619 mov r1, r3 8003696: f005 fd3d bl 8009114 <__aeabi_d2iz> 800369a: 4601 mov r1, r0 800369c: e9d7 2302 ldrd r2, r3, [r7, #8] 80036a0: 4608 mov r0, r1 80036a2: f000 f8b5 bl 8003810 return(STATUS_OK); 80036a6: f04f 0300 mov.w r3, #0 } 80036aa: 4618 mov r0, r3 80036ac: f107 0720 add.w r7, r7, #32 80036b0: 46bd mov sp, r7 80036b2: bd80 pop {r7, pc} 080036b4 : void write_settings() { 80036b4: b580 push {r7, lr} 80036b6: af00 add r7, sp, #0 eeprom_put_char(0, SETTINGS_VERSION); 80036b8: f04f 0000 mov.w r0, #0 80036bc: f04f 0104 mov.w r1, #4 80036c0: f001 ff7e bl 80055c0 memcpy_to_eeprom_with_checksum(1, (char*)&settings, sizeof(settings_t)); 80036c4: f04f 0001 mov.w r0, #1 80036c8: f240 61d8 movw r1, #1752 ; 0x6d8 80036cc: f2c2 0100 movt r1, #8192 ; 0x2000 80036d0: f04f 0250 mov.w r2, #80 ; 0x50 80036d4: f001 ff80 bl 80055d8 } 80036d8: bd80 pop {r7, pc} 80036da: bf00 nop 80036dc: 0000 movs r0, r0 ... 080036e0 : int read_settings() { 80036e0: b580 push {r7, lr} 80036e2: b082 sub sp, #8 80036e4: af00 add r7, sp, #0 // Check version-byte of eeprom uint8_t version = eeprom_get_char(0); 80036e6: f04f 0000 mov.w r0, #0 80036ea: f001 ff5d bl 80055a8 80036ee: 4603 mov r3, r0 80036f0: 71fb strb r3, [r7, #7] if (version == SETTINGS_VERSION) { 80036f2: 79fb ldrb r3, [r7, #7] 80036f4: 2b04 cmp r3, #4 80036f6: d10f bne.n 8003718 // Read settings-record and check checksum if (!(memcpy_from_eeprom_with_checksum((char*)&settings, 1, sizeof(settings_t)))) { 80036f8: f240 60d8 movw r0, #1752 ; 0x6d8 80036fc: f2c2 0000 movt r0, #8192 ; 0x2000 8003700: f04f 0101 mov.w r1, #1 8003704: f04f 0250 mov.w r2, #80 ; 0x50 8003708: f001 ffa4 bl 8005654 800370c: 4603 mov r3, r0 800370e: 2b00 cmp r3, #0 8003710: d169 bne.n 80037e6 return(false); 8003712: f04f 0300 mov.w r3, #0 8003716: e068 b.n 80037ea } } else if (version == 1) { 8003718: 79fb ldrb r3, [r7, #7] 800371a: 2b01 cmp r3, #1 800371c: d124 bne.n 8003768 // Migrate from settings version 1 if (!(memcpy_from_eeprom_with_checksum((char*)&settings, 1, sizeof(settings_v1_t)))) { 800371e: f240 60d8 movw r0, #1752 ; 0x6d8 8003722: f2c2 0000 movt r0, #8192 ; 0x2000 8003726: f04f 0101 mov.w r1, #1 800372a: f04f 0240 mov.w r2, #64 ; 0x40 800372e: f001 ff91 bl 8005654 8003732: 4603 mov r3, r0 8003734: 2b00 cmp r3, #0 8003736: d102 bne.n 800373e return(false); 8003738: f04f 0300 mov.w r3, #0 800373c: e055 b.n 80037ea } settings.acceleration = DEFAULT_ACCELERATION; 800373e: f240 63d8 movw r3, #1752 ; 0x6d8 8003742: f2c2 0300 movt r3, #8192 ; 0x2000 8003746: a12c add r1, pc, #176 ; (adr r1, 80037f8 ) 8003748: e9d1 0100 ldrd r0, r1, [r1] 800374c: e9c3 0110 strd r0, r1, [r3, #64] ; 0x40 settings.junction_deviation = DEFAULT_JUNCTION_DEVIATION; 8003750: f240 63d8 movw r3, #1752 ; 0x6d8 8003754: f2c2 0300 movt r3, #8192 ; 0x2000 8003758: a129 add r1, pc, #164 ; (adr r1, 8003800 ) 800375a: e9d1 0100 ldrd r0, r1, [r1] 800375e: e9c3 0112 strd r0, r1, [r3, #72] ; 0x48 write_settings(); 8003762: f7ff ffa7 bl 80036b4 8003766: e03e b.n 80037e6 } else if ((version == 2) || (version == 3)) { 8003768: 79fb ldrb r3, [r7, #7] 800376a: 2b02 cmp r3, #2 800376c: d002 beq.n 8003774 800376e: 79fb ldrb r3, [r7, #7] 8003770: 2b03 cmp r3, #3 8003772: d135 bne.n 80037e0 // Migrate from settings version 2 and 3 if (!(memcpy_from_eeprom_with_checksum((char*)&settings, 1, sizeof(settings_t)))) { 8003774: f240 60d8 movw r0, #1752 ; 0x6d8 8003778: f2c2 0000 movt r0, #8192 ; 0x2000 800377c: f04f 0101 mov.w r1, #1 8003780: f04f 0250 mov.w r2, #80 ; 0x50 8003784: f001 ff66 bl 8005654 8003788: 4603 mov r3, r0 800378a: 2b00 cmp r3, #0 800378c: d102 bne.n 8003794 return(false); 800378e: f04f 0300 mov.w r3, #0 8003792: e02a b.n 80037ea } if (version == 2) { settings.junction_deviation = DEFAULT_JUNCTION_DEVIATION; } 8003794: 79fb ldrb r3, [r7, #7] 8003796: 2b02 cmp r3, #2 8003798: d108 bne.n 80037ac 800379a: f240 63d8 movw r3, #1752 ; 0x6d8 800379e: f2c2 0300 movt r3, #8192 ; 0x2000 80037a2: a117 add r1, pc, #92 ; (adr r1, 8003800 ) 80037a4: e9d1 0100 ldrd r0, r1, [r1] 80037a8: e9c3 0112 strd r0, r1, [r3, #72] ; 0x48 settings.acceleration *= 3600; // Convert to mm/min^2 from mm/sec^2 80037ac: f240 63d8 movw r3, #1752 ; 0x6d8 80037b0: f2c2 0300 movt r3, #8192 ; 0x2000 80037b4: e9d3 2310 ldrd r2, r3, [r3, #64] ; 0x40 80037b8: 4610 mov r0, r2 80037ba: 4619 mov r1, r3 80037bc: a312 add r3, pc, #72 ; (adr r3, 8003808 ) 80037be: e9d3 2300 ldrd r2, r3, [r3] 80037c2: f005 fa0d bl 8008be0 <__aeabi_dmul> 80037c6: 4602 mov r2, r0 80037c8: 460b mov r3, r1 80037ca: 4610 mov r0, r2 80037cc: 4619 mov r1, r3 80037ce: f240 63d8 movw r3, #1752 ; 0x6d8 80037d2: f2c2 0300 movt r3, #8192 ; 0x2000 80037d6: e9c3 0110 strd r0, r1, [r3, #64] ; 0x40 write_settings(); 80037da: f7ff ff6b bl 80036b4 80037de: e002 b.n 80037e6 } else { return(false); 80037e0: f04f 0300 mov.w r3, #0 80037e4: e001 b.n 80037ea } return(true); 80037e6: f04f 0301 mov.w r3, #1 } 80037ea: 4618 mov r0, r3 80037ec: f107 0708 add.w r7, r7, #8 80037f0: 46bd mov sp, r7 80037f2: bd80 pop {r7, pc} 80037f4: f3af 8000 nop.w 80037f8: 00000000 .word 0x00000000 80037fc: 4105f900 .word 0x4105f900 8003800: 9999999a .word 0x9999999a 8003804: 3fa99999 .word 0x3fa99999 8003808: 00000000 .word 0x00000000 800380c: 40ac2000 .word 0x40ac2000 08003810 : // A helper method to set settings from command line void settings_store_setting(int parameter, double value) { 8003810: b5b0 push {r4, r5, r7, lr} 8003812: b084 sub sp, #16 8003814: af00 add r7, sp, #0 8003816: 60f8 str r0, [r7, #12] 8003818: e9c7 2300 strd r2, r3, [r7] switch(parameter) { 800381c: 68fb ldr r3, [r7, #12] 800381e: 2b09 cmp r3, #9 8003820: f200 80be bhi.w 80039a0 8003824: a201 add r2, pc, #4 ; (adr r2, 800382c ) 8003826: f852 f023 ldr.w pc, [r2, r3, lsl #2] 800382a: bf00 nop 800382c: 08003855 .word 0x08003855 8003830: 08003855 .word 0x08003855 8003834: 08003855 .word 0x08003855 8003838: 080038a3 .word 0x080038a3 800383c: 080038fb .word 0x080038fb 8003840: 0800390d .word 0x0800390d 8003844: 0800391f .word 0x0800391f 8003848: 08003931 .word 0x08003931 800384c: 08003955 .word 0x08003955 8003850: 0800398b .word 0x0800398b case 0: case 1: case 2: if (value <= 0.0) { 8003854: f04f 0301 mov.w r3, #1 8003858: 461c mov r4, r3 800385a: e9d7 0100 ldrd r0, r1, [r7] 800385e: a35a add r3, pc, #360 ; (adr r3, 80039c8 ) 8003860: e9d3 2300 ldrd r2, r3, [r3] 8003864: f005 fc38 bl 80090d8 <__aeabi_dcmple> 8003868: 4603 mov r3, r0 800386a: 2b00 cmp r3, #0 800386c: d102 bne.n 8003874 800386e: f04f 0300 mov.w r3, #0 8003872: 461c mov r4, r3 8003874: b2e3 uxtb r3, r4 8003876: 2b00 cmp r3, #0 8003878: d006 beq.n 8003888 printPgmString("Steps/mm must be > 0.0\r\n"); 800387a: f64a 40dc movw r0, #44252 ; 0xacdc 800387e: f6c0 0000 movt r0, #2048 ; 0x800 8003882: f7fc ff4b bl 800071c return; 8003886: e09a b.n 80039be } settings.steps_per_mm[parameter] = value; break; 8003888: f240 63d8 movw r3, #1752 ; 0x6d8 800388c: f2c2 0300 movt r3, #8192 ; 0x2000 8003890: 68fa ldr r2, [r7, #12] 8003892: ea4f 02c2 mov.w r2, r2, lsl #3 8003896: 1899 adds r1, r3, r2 8003898: e9d7 2300 ldrd r2, r3, [r7] 800389c: e9c1 2300 strd r2, r3, [r1] 80038a0: e085 b.n 80039ae case 3: if (value < 3) { 80038a2: f04f 0301 mov.w r3, #1 80038a6: 461c mov r4, r3 80038a8: e9d7 0100 ldrd r0, r1, [r7] 80038ac: a348 add r3, pc, #288 ; (adr r3, 80039d0 ) 80038ae: e9d3 2300 ldrd r2, r3, [r3] 80038b2: f005 fc07 bl 80090c4 <__aeabi_dcmplt> 80038b6: 4603 mov r3, r0 80038b8: 2b00 cmp r3, #0 80038ba: d102 bne.n 80038c2 80038bc: f04f 0300 mov.w r3, #0 80038c0: 461c mov r4, r3 80038c2: b2e3 uxtb r3, r4 80038c4: 2b00 cmp r3, #0 80038c6: d006 beq.n 80038d6 printPgmString("Step pulse must be >= 3 microseconds\r\n"); 80038c8: f64a 40f8 movw r0, #44280 ; 0xacf8 80038cc: f6c0 0000 movt r0, #2048 ; 0x800 80038d0: f7fc ff24 bl 800071c return; 80038d4: e073 b.n 80039be } settings.pulse_microseconds = round(value); break; 80038d6: e9d7 0100 ldrd r0, r1, [r7] 80038da: f002 e9d6 blx 8005c88 80038de: 4602 mov r2, r0 80038e0: 460b mov r3, r1 80038e2: 4610 mov r0, r2 80038e4: 4619 mov r1, r3 80038e6: f005 fc3d bl 8009164 <__aeabi_d2uiz> 80038ea: 4603 mov r3, r0 80038ec: b2da uxtb r2, r3 80038ee: f240 63d8 movw r3, #1752 ; 0x6d8 80038f2: f2c2 0300 movt r3, #8192 ; 0x2000 80038f6: 765a strb r2, [r3, #25] 80038f8: e059 b.n 80039ae case 4: settings.default_feed_rate = value; break; 80038fa: f240 63d8 movw r3, #1752 ; 0x6d8 80038fe: f2c2 0300 movt r3, #8192 ; 0x2000 8003902: e9d7 0100 ldrd r0, r1, [r7] 8003906: e9c3 0108 strd r0, r1, [r3, #32] 800390a: e050 b.n 80039ae case 5: settings.default_seek_rate = value; break; 800390c: f240 63d8 movw r3, #1752 ; 0x6d8 8003910: f2c2 0300 movt r3, #8192 ; 0x2000 8003914: e9d7 0100 ldrd r0, r1, [r7] 8003918: e9c3 010a strd r0, r1, [r3, #40] ; 0x28 800391c: e047 b.n 80039ae case 6: settings.mm_per_arc_segment = value; break; 800391e: f240 63d8 movw r3, #1752 ; 0x6d8 8003922: f2c2 0300 movt r3, #8192 ; 0x2000 8003926: e9d7 0100 ldrd r0, r1, [r7] 800392a: e9c3 010e strd r0, r1, [r3, #56] ; 0x38 800392e: e03e b.n 80039ae case 7: settings.invert_mask = trunc(value); break; 8003930: e9d7 0100 ldrd r0, r1, [r7] 8003934: f002 eab6 blx 8005ea4 8003938: 4602 mov r2, r0 800393a: 460b mov r3, r1 800393c: 4610 mov r0, r2 800393e: 4619 mov r1, r3 8003940: f005 fc10 bl 8009164 <__aeabi_d2uiz> 8003944: 4603 mov r3, r0 8003946: b29a uxth r2, r3 8003948: f240 63d8 movw r3, #1752 ; 0x6d8 800394c: f2c2 0300 movt r3, #8192 ; 0x2000 8003950: 861a strh r2, [r3, #48] ; 0x30 8003952: e02c b.n 80039ae case 8: settings.acceleration = value*60*60; break; // Convert to mm/min^2 for grbl internal use. 8003954: e9d7 0100 ldrd r0, r1, [r7] 8003958: a31f add r3, pc, #124 ; (adr r3, 80039d8 ) 800395a: e9d3 2300 ldrd r2, r3, [r3] 800395e: f005 f93f bl 8008be0 <__aeabi_dmul> 8003962: 4602 mov r2, r0 8003964: 460b mov r3, r1 8003966: 4610 mov r0, r2 8003968: 4619 mov r1, r3 800396a: a31b add r3, pc, #108 ; (adr r3, 80039d8 ) 800396c: e9d3 2300 ldrd r2, r3, [r3] 8003970: f005 f936 bl 8008be0 <__aeabi_dmul> 8003974: 4602 mov r2, r0 8003976: 460b mov r3, r1 8003978: 4610 mov r0, r2 800397a: 4619 mov r1, r3 800397c: f240 63d8 movw r3, #1752 ; 0x6d8 8003980: f2c2 0300 movt r3, #8192 ; 0x2000 8003984: e9c3 0110 strd r0, r1, [r3, #64] ; 0x40 8003988: e011 b.n 80039ae case 9: settings.junction_deviation = fabs(value); break; 800398a: 683c ldr r4, [r7, #0] 800398c: 687b ldr r3, [r7, #4] 800398e: f023 4500 bic.w r5, r3, #2147483648 ; 0x80000000 8003992: f240 63d8 movw r3, #1752 ; 0x6d8 8003996: f2c2 0300 movt r3, #8192 ; 0x2000 800399a: e9c3 4512 strd r4, r5, [r3, #72] ; 0x48 800399e: e006 b.n 80039ae default: printPgmString("Unknown parameter\r\n"); 80039a0: f64a 5020 movw r0, #44320 ; 0xad20 80039a4: f6c0 0000 movt r0, #2048 ; 0x800 80039a8: f7fc feb8 bl 800071c return; 80039ac: e007 b.n 80039be } write_settings(); 80039ae: f7ff fe81 bl 80036b4 printPgmString("Stored new setting\r\n"); 80039b2: f64a 5034 movw r0, #44340 ; 0xad34 80039b6: f6c0 0000 movt r0, #2048 ; 0x800 80039ba: f7fc feaf bl 800071c } 80039be: f107 0710 add.w r7, r7, #16 80039c2: 46bd mov sp, r7 80039c4: bdb0 pop {r4, r5, r7, pc} 80039c6: bf00 nop ... 80039d4: 40080000 .word 0x40080000 80039d8: 00000000 .word 0x00000000 80039dc: 404e0000 .word 0x404e0000 080039e0 : // Initialize the config subsystem void settings_init() { 80039e0: b580 push {r7, lr} 80039e2: af00 add r7, sp, #0 if(read_settings()) { 80039e4: f7ff fe7c bl 80036e0 80039e8: 4603 mov r3, r0 80039ea: 2b00 cmp r3, #0 80039ec: d006 beq.n 80039fc printPgmString("'$' to dump current settings\r\n"); 80039ee: f64a 504c movw r0, #44364 ; 0xad4c 80039f2: f6c0 0000 movt r0, #2048 ; 0x800 80039f6: f7fc fe91 bl 800071c 80039fa: e00b b.n 8003a14 } else { printPgmString("Warning: Failed to read EEPROM settings. Using defaults.\r\n"); 80039fc: f64a 506c movw r0, #44396 ; 0xad6c 8003a00: f6c0 0000 movt r0, #2048 ; 0x800 8003a04: f7fc fe8a bl 800071c settings_reset(); 8003a08: f7ff fcb6 bl 8003378 write_settings(); 8003a0c: f7ff fe52 bl 80036b4 settings_dump(); 8003a10: f7ff fd22 bl 8003458 } } 8003a14: bd80 pop {r7, pc} 8003a16: bf00 nop 08003a18 : // Returns the index of the next block in the ring buffer // NOTE: Removed modulo (%) operator, which uses an expensive divide and multiplication. static uint8_t next_block_index(uint8_t block_index) { 8003a18: b480 push {r7} 8003a1a: b083 sub sp, #12 8003a1c: af00 add r7, sp, #0 8003a1e: 4603 mov r3, r0 8003a20: 71fb strb r3, [r7, #7] block_index++; 8003a22: 79fb ldrb r3, [r7, #7] 8003a24: f103 0301 add.w r3, r3, #1 8003a28: 71fb strb r3, [r7, #7] if (block_index == BLOCK_BUFFER_SIZE) { block_index = 0; } 8003a2a: 79fb ldrb r3, [r7, #7] 8003a2c: 2b05 cmp r3, #5 8003a2e: d102 bne.n 8003a36 8003a30: f04f 0300 mov.w r3, #0 8003a34: 71fb strb r3, [r7, #7] return(block_index); 8003a36: 79fb ldrb r3, [r7, #7] } 8003a38: 4618 mov r0, r3 8003a3a: f107 070c add.w r7, r7, #12 8003a3e: 46bd mov sp, r7 8003a40: bc80 pop {r7} 8003a42: 4770 bx lr 08003a44 : // Returns the index of the previous block in the ring buffer static uint8_t prev_block_index(uint8_t block_index) { 8003a44: b480 push {r7} 8003a46: b083 sub sp, #12 8003a48: af00 add r7, sp, #0 8003a4a: 4603 mov r3, r0 8003a4c: 71fb strb r3, [r7, #7] if (block_index == 0) { block_index = BLOCK_BUFFER_SIZE; } 8003a4e: 79fb ldrb r3, [r7, #7] 8003a50: 2b00 cmp r3, #0 8003a52: d102 bne.n 8003a5a 8003a54: f04f 0305 mov.w r3, #5 8003a58: 71fb strb r3, [r7, #7] block_index--; 8003a5a: 79fb ldrb r3, [r7, #7] 8003a5c: f103 33ff add.w r3, r3, #4294967295 8003a60: 71fb strb r3, [r7, #7] return(block_index); 8003a62: 79fb ldrb r3, [r7, #7] } 8003a64: 4618 mov r0, r3 8003a66: f107 070c add.w r7, r7, #12 8003a6a: 46bd mov sp, r7 8003a6c: bc80 pop {r7} 8003a6e: 4770 bx lr 08003a70 : // Calculates the distance (not time) it takes to accelerate from initial_rate to target_rate using the // given acceleration: static double estimate_acceleration_distance(double initial_rate, double target_rate, double acceleration) { 8003a70: b5b0 push {r4, r5, r7, lr} 8003a72: b084 sub sp, #16 8003a74: af00 add r7, sp, #0 8003a76: e9c7 0102 strd r0, r1, [r7, #8] 8003a7a: e9c7 2300 strd r2, r3, [r7] return( (target_rate*target_rate-initial_rate*initial_rate)/(2*acceleration) ); 8003a7e: e9d7 0100 ldrd r0, r1, [r7] 8003a82: e9d7 2300 ldrd r2, r3, [r7] 8003a86: f005 f8ab bl 8008be0 <__aeabi_dmul> 8003a8a: 4602 mov r2, r0 8003a8c: 460b mov r3, r1 8003a8e: 4614 mov r4, r2 8003a90: 461d mov r5, r3 8003a92: e9d7 0102 ldrd r0, r1, [r7, #8] 8003a96: e9d7 2302 ldrd r2, r3, [r7, #8] 8003a9a: f005 f8a1 bl 8008be0 <__aeabi_dmul> 8003a9e: 4602 mov r2, r0 8003aa0: 460b mov r3, r1 8003aa2: 4620 mov r0, r4 8003aa4: 4629 mov r1, r5 8003aa6: f004 fee7 bl 8008878 <__aeabi_dsub> 8003aaa: 4602 mov r2, r0 8003aac: 460b mov r3, r1 8003aae: 4614 mov r4, r2 8003ab0: 461d mov r5, r3 8003ab2: e9d7 2308 ldrd r2, r3, [r7, #32] 8003ab6: 4610 mov r0, r2 8003ab8: 4619 mov r1, r3 8003aba: f004 fedf bl 800887c <__adddf3> 8003abe: 4602 mov r2, r0 8003ac0: 460b mov r3, r1 8003ac2: 4620 mov r0, r4 8003ac4: 4629 mov r1, r5 8003ac6: f005 f9b5 bl 8008e34 <__aeabi_ddiv> 8003aca: 4602 mov r2, r0 8003acc: 460b mov r3, r1 } 8003ace: 4610 mov r0, r2 8003ad0: 4619 mov r1, r3 8003ad2: f107 0710 add.w r7, r7, #16 8003ad6: 46bd mov sp, r7 8003ad8: bdb0 pop {r4, r5, r7, pc} 8003ada: bf00 nop 8003adc: 0000 movs r0, r0 ... 08003ae0 : // This function gives you the point at which you must start braking (at the rate of -acceleration) if // you started at speed initial_rate and accelerated until this point and want to end at the final_rate after // a total travel of distance. This can be used to compute the intersection point between acceleration and // deceleration in the cases where the trapezoid has no plateau (i.e. never reaches maximum speed) static double intersection_distance(double initial_rate, double final_rate, double acceleration, double distance) { 8003ae0: b5b0 push {r4, r5, r7, lr} 8003ae2: b084 sub sp, #16 8003ae4: af00 add r7, sp, #0 8003ae6: e9c7 0102 strd r0, r1, [r7, #8] 8003aea: e9c7 2300 strd r2, r3, [r7] return( (2*acceleration*distance-initial_rate*initial_rate+final_rate*final_rate)/(4*acceleration) ); 8003aee: e9d7 2308 ldrd r2, r3, [r7, #32] 8003af2: 4610 mov r0, r2 8003af4: 4619 mov r1, r3 8003af6: f004 fec1 bl 800887c <__adddf3> 8003afa: 4602 mov r2, r0 8003afc: 460b mov r3, r1 8003afe: 4610 mov r0, r2 8003b00: 4619 mov r1, r3 8003b02: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28 8003b06: f005 f86b bl 8008be0 <__aeabi_dmul> 8003b0a: 4602 mov r2, r0 8003b0c: 460b mov r3, r1 8003b0e: 4614 mov r4, r2 8003b10: 461d mov r5, r3 8003b12: e9d7 0102 ldrd r0, r1, [r7, #8] 8003b16: e9d7 2302 ldrd r2, r3, [r7, #8] 8003b1a: f005 f861 bl 8008be0 <__aeabi_dmul> 8003b1e: 4602 mov r2, r0 8003b20: 460b mov r3, r1 8003b22: 4620 mov r0, r4 8003b24: 4629 mov r1, r5 8003b26: f004 fea7 bl 8008878 <__aeabi_dsub> 8003b2a: 4602 mov r2, r0 8003b2c: 460b mov r3, r1 8003b2e: 4614 mov r4, r2 8003b30: 461d mov r5, r3 8003b32: e9d7 0100 ldrd r0, r1, [r7] 8003b36: e9d7 2300 ldrd r2, r3, [r7] 8003b3a: f005 f851 bl 8008be0 <__aeabi_dmul> 8003b3e: 4602 mov r2, r0 8003b40: 460b mov r3, r1 8003b42: 4620 mov r0, r4 8003b44: 4629 mov r1, r5 8003b46: f004 fe99 bl 800887c <__adddf3> 8003b4a: 4602 mov r2, r0 8003b4c: 460b mov r3, r1 8003b4e: 4614 mov r4, r2 8003b50: 461d mov r5, r3 8003b52: e9d7 0108 ldrd r0, r1, [r7, #32] 8003b56: a30a add r3, pc, #40 ; (adr r3, 8003b80 ) 8003b58: e9d3 2300 ldrd r2, r3, [r3] 8003b5c: f005 f840 bl 8008be0 <__aeabi_dmul> 8003b60: 4602 mov r2, r0 8003b62: 460b mov r3, r1 8003b64: 4620 mov r0, r4 8003b66: 4629 mov r1, r5 8003b68: f005 f964 bl 8008e34 <__aeabi_ddiv> 8003b6c: 4602 mov r2, r0 8003b6e: 460b mov r3, r1 } 8003b70: 4610 mov r0, r2 8003b72: 4619 mov r1, r3 8003b74: f107 0710 add.w r7, r7, #16 8003b78: 46bd mov sp, r7 8003b7a: bdb0 pop {r4, r5, r7, pc} 8003b7c: f3af 8000 nop.w 8003b80: 00000000 .word 0x00000000 8003b84: 40100000 .word 0x40100000 08003b88 : // using the acceleration within the allotted distance. // NOTE: sqrt() reimplimented here from prior version due to improved planner logic. Increases speed // in time critical computations, i.e. arcs or rapid short lines from curves. Guaranteed to not exceed // BLOCK_BUFFER_SIZE calls per planner cycle. static double max_allowable_speed(double acceleration, double target_velocity, double distance) { 8003b88: b5b0 push {r4, r5, r7, lr} 8003b8a: b084 sub sp, #16 8003b8c: af00 add r7, sp, #0 8003b8e: e9c7 0102 strd r0, r1, [r7, #8] 8003b92: e9c7 2300 strd r2, r3, [r7] return( sqrt(target_velocity*target_velocity-2*acceleration*distance) ); 8003b96: e9d7 0100 ldrd r0, r1, [r7] 8003b9a: e9d7 2300 ldrd r2, r3, [r7] 8003b9e: f005 f81f bl 8008be0 <__aeabi_dmul> 8003ba2: 4602 mov r2, r0 8003ba4: 460b mov r3, r1 8003ba6: 4614 mov r4, r2 8003ba8: 461d mov r5, r3 8003baa: e9d7 2302 ldrd r2, r3, [r7, #8] 8003bae: 4610 mov r0, r2 8003bb0: 4619 mov r1, r3 8003bb2: f004 fe63 bl 800887c <__adddf3> 8003bb6: 4602 mov r2, r0 8003bb8: 460b mov r3, r1 8003bba: 4610 mov r0, r2 8003bbc: 4619 mov r1, r3 8003bbe: e9d7 2308 ldrd r2, r3, [r7, #32] 8003bc2: f005 f80d bl 8008be0 <__aeabi_dmul> 8003bc6: 4602 mov r2, r0 8003bc8: 460b mov r3, r1 8003bca: 4620 mov r0, r4 8003bcc: 4629 mov r1, r5 8003bce: f004 fe53 bl 8008878 <__aeabi_dsub> 8003bd2: 4602 mov r2, r0 8003bd4: 460b mov r3, r1 8003bd6: 4610 mov r0, r2 8003bd8: 4619 mov r1, r3 8003bda: f002 ea58 blx 800608c 8003bde: 4602 mov r2, r0 8003be0: 460b mov r3, r1 } 8003be2: 4610 mov r0, r2 8003be4: 4619 mov r1, r3 8003be6: f107 0710 add.w r7, r7, #16 8003bea: 46bd mov sp, r7 8003bec: bdb0 pop {r4, r5, r7, pc} 8003bee: bf00 nop 08003bf0 : // The kernel called by planner_recalculate() when scanning the plan from last to first entry. static void planner_reverse_pass_kernel(block_t *previous, block_t *current, block_t *next) { 8003bf0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8003bf4: b087 sub sp, #28 8003bf6: af02 add r7, sp, #8 8003bf8: 60f8 str r0, [r7, #12] 8003bfa: 60b9 str r1, [r7, #8] 8003bfc: 607a str r2, [r7, #4] if (!current) { return; } // Cannot operate on nothing. 8003bfe: 68bb ldr r3, [r7, #8] 8003c00: 2b00 cmp r3, #0 8003c02: d07a beq.n 8003cfa if (next) { 8003c04: 687b ldr r3, [r7, #4] 8003c06: 2b00 cmp r3, #0 8003c08: d078 beq.n 8003cfc // If entry speed is already at the maximum entry speed, no need to recheck. Block is cruising. // If not, block in state of acceleration or deceleration. Reset entry speed to maximum and // check for maximum allowable speed reductions to ensure maximum possible planned speed. if (current->entry_speed != current->max_entry_speed) { 8003c0a: 68bb ldr r3, [r7, #8] 8003c0c: e9d3 0108 ldrd r0, r1, [r3, #32] 8003c10: 68bb ldr r3, [r7, #8] 8003c12: e9d3 230a ldrd r2, r3, [r3, #40] ; 0x28 8003c16: f005 fa4b bl 80090b0 <__aeabi_dcmpeq> 8003c1a: 4603 mov r3, r0 8003c1c: 2b00 cmp r3, #0 8003c1e: d16d bne.n 8003cfc // If nominal length true, max junction speed is guaranteed to be reached. Only compute // for max allowable speed if block is decelerating and nominal length is false. if ((!current->nominal_length_flag) && (current->max_entry_speed > next->entry_speed)) { 8003c20: 68bb ldr r3, [r7, #8] 8003c22: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 8003c26: 2b00 cmp r3, #0 8003c28: d15b bne.n 8003ce2 8003c2a: 68bb ldr r3, [r7, #8] 8003c2c: e9d3 010a ldrd r0, r1, [r3, #40] ; 0x28 8003c30: 687b ldr r3, [r7, #4] 8003c32: e9d3 2308 ldrd r2, r3, [r3, #32] 8003c36: f04f 0601 mov.w r6, #1 8003c3a: f005 fa61 bl 8009100 <__aeabi_dcmpgt> 8003c3e: 4603 mov r3, r0 8003c40: 2b00 cmp r3, #0 8003c42: d102 bne.n 8003c4a 8003c44: f04f 0300 mov.w r3, #0 8003c48: 461e mov r6, r3 8003c4a: b2f3 uxtb r3, r6 8003c4c: 2b00 cmp r3, #0 8003c4e: d048 beq.n 8003ce2 current->entry_speed = min( current->max_entry_speed, 8003c50: 68bb ldr r3, [r7, #8] 8003c52: e9d3 ab0a ldrd sl, fp, [r3, #40] ; 0x28 8003c56: f240 63d8 movw r3, #1752 ; 0x6d8 8003c5a: f2c2 0300 movt r3, #8192 ; 0x2000 8003c5e: e9d3 2310 ldrd r2, r3, [r3, #64] ; 0x40 8003c62: 4690 mov r8, r2 8003c64: f083 4900 eor.w r9, r3, #2147483648 ; 0x80000000 8003c68: 687b ldr r3, [r7, #4] 8003c6a: e9d3 2308 ldrd r2, r3, [r3, #32] 8003c6e: 68b9 ldr r1, [r7, #8] 8003c70: e9d1 010c ldrd r0, r1, [r1, #48] ; 0x30 8003c74: e9cd 0100 strd r0, r1, [sp] 8003c78: 4640 mov r0, r8 8003c7a: 4649 mov r1, r9 8003c7c: f7ff ff84 bl 8003b88 8003c80: 4602 mov r2, r0 8003c82: 460b mov r3, r1 8003c84: f04f 0101 mov.w r1, #1 8003c88: 460e mov r6, r1 8003c8a: 4650 mov r0, sl 8003c8c: 4659 mov r1, fp 8003c8e: f005 fa19 bl 80090c4 <__aeabi_dcmplt> 8003c92: 4603 mov r3, r0 8003c94: 2b00 cmp r3, #0 8003c96: d102 bne.n 8003c9e 8003c98: f04f 0300 mov.w r3, #0 8003c9c: 461e mov r6, r3 8003c9e: b2f3 uxtb r3, r6 8003ca0: 2b00 cmp r3, #0 8003ca2: d003 beq.n 8003cac 8003ca4: 68bb ldr r3, [r7, #8] 8003ca6: e9d3 230a ldrd r2, r3, [r3, #40] ; 0x28 8003caa: e016 b.n 8003cda 8003cac: f240 63d8 movw r3, #1752 ; 0x6d8 8003cb0: f2c2 0300 movt r3, #8192 ; 0x2000 8003cb4: e9d3 2310 ldrd r2, r3, [r3, #64] ; 0x40 8003cb8: 4614 mov r4, r2 8003cba: f083 4500 eor.w r5, r3, #2147483648 ; 0x80000000 8003cbe: 687b ldr r3, [r7, #4] 8003cc0: e9d3 2308 ldrd r2, r3, [r3, #32] 8003cc4: 68b9 ldr r1, [r7, #8] 8003cc6: e9d1 010c ldrd r0, r1, [r1, #48] ; 0x30 8003cca: e9cd 0100 strd r0, r1, [sp] 8003cce: 4620 mov r0, r4 8003cd0: 4629 mov r1, r5 8003cd2: f7ff ff59 bl 8003b88 8003cd6: 4602 mov r2, r0 8003cd8: 460b mov r3, r1 8003cda: 68b9 ldr r1, [r7, #8] 8003cdc: e9c1 2308 strd r2, r3, [r1, #32] 8003ce0: e005 b.n 8003cee max_allowable_speed(-settings.acceleration,next->entry_speed,current->millimeters)); } else { current->entry_speed = current->max_entry_speed; 8003ce2: 68bb ldr r3, [r7, #8] 8003ce4: e9d3 230a ldrd r2, r3, [r3, #40] ; 0x28 8003ce8: 68b9 ldr r1, [r7, #8] 8003cea: e9c1 2308 strd r2, r3, [r1, #32] } current->recalculate_flag = true; 8003cee: 68bb ldr r3, [r7, #8] 8003cf0: f04f 0201 mov.w r2, #1 8003cf4: f883 2038 strb.w r2, [r3, #56] ; 0x38 8003cf8: e000 b.n 8003cfc // The kernel called by planner_recalculate() when scanning the plan from last to first entry. static void planner_reverse_pass_kernel(block_t *previous, block_t *current, block_t *next) { if (!current) { return; } // Cannot operate on nothing. 8003cfa: bf00 nop } current->recalculate_flag = true; } } // Skip last block. Already initialized and set for recalculation. } 8003cfc: f107 0714 add.w r7, r7, #20 8003d00: 46bd mov sp, r7 8003d02: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8003d06: bf00 nop 08003d08 : // planner_recalculate() needs to go over the current plan twice. Once in reverse and once forward. This // implements the reverse pass. static void planner_reverse_pass() { 8003d08: b580 push {r7, lr} 8003d0a: b084 sub sp, #16 8003d0c: af00 add r7, sp, #0 uint8_t block_index = block_buffer_head; 8003d0e: f240 6398 movw r3, #1688 ; 0x698 8003d12: f2c2 0300 movt r3, #8192 ; 0x2000 8003d16: 781b ldrb r3, [r3, #0] 8003d18: 73fb strb r3, [r7, #15] block_t *block[3] = {NULL, NULL, NULL}; 8003d1a: f04f 0300 mov.w r3, #0 8003d1e: 603b str r3, [r7, #0] 8003d20: f04f 0300 mov.w r3, #0 8003d24: 607b str r3, [r7, #4] 8003d26: f04f 0300 mov.w r3, #0 8003d2a: 60bb str r3, [r7, #8] while(block_index != block_buffer_tail) { 8003d2c: e01c b.n 8003d68 block_index = prev_block_index( block_index ); 8003d2e: 7bfb ldrb r3, [r7, #15] 8003d30: 4618 mov r0, r3 8003d32: f7ff fe87 bl 8003a44 8003d36: 4603 mov r3, r0 8003d38: 73fb strb r3, [r7, #15] block[2]= block[1]; 8003d3a: 687b ldr r3, [r7, #4] 8003d3c: 60bb str r3, [r7, #8] block[1]= block[0]; 8003d3e: 683b ldr r3, [r7, #0] 8003d40: 607b str r3, [r7, #4] block[0] = &block_buffer[block_index]; 8003d42: 7bfb ldrb r3, [r7, #15] 8003d44: f04f 0258 mov.w r2, #88 ; 0x58 8003d48: fb02 f203 mul.w r2, r2, r3 8003d4c: f240 43e0 movw r3, #1248 ; 0x4e0 8003d50: f2c2 0300 movt r3, #8192 ; 0x2000 8003d54: 18d3 adds r3, r2, r3 8003d56: 603b str r3, [r7, #0] planner_reverse_pass_kernel(block[0], block[1], block[2]); 8003d58: 6839 ldr r1, [r7, #0] 8003d5a: 687a ldr r2, [r7, #4] 8003d5c: 68bb ldr r3, [r7, #8] 8003d5e: 4608 mov r0, r1 8003d60: 4611 mov r1, r2 8003d62: 461a mov r2, r3 8003d64: f7ff ff44 bl 8003bf0 // implements the reverse pass. static void planner_reverse_pass() { uint8_t block_index = block_buffer_head; block_t *block[3] = {NULL, NULL, NULL}; while(block_index != block_buffer_tail) { 8003d68: f240 6399 movw r3, #1689 ; 0x699 8003d6c: f2c2 0300 movt r3, #8192 ; 0x2000 8003d70: 781b ldrb r3, [r3, #0] 8003d72: b2db uxtb r3, r3 8003d74: 7bfa ldrb r2, [r7, #15] 8003d76: 429a cmp r2, r3 8003d78: d1d9 bne.n 8003d2e block[1]= block[0]; block[0] = &block_buffer[block_index]; planner_reverse_pass_kernel(block[0], block[1], block[2]); } // Skip buffer tail/first block to prevent over-writing the initial entry speed. } 8003d7a: f107 0710 add.w r7, r7, #16 8003d7e: 46bd mov sp, r7 8003d80: bd80 pop {r7, pc} 8003d82: bf00 nop 08003d84 : // The kernel called by planner_recalculate() when scanning the plan from first to last entry. static void planner_forward_pass_kernel(block_t *previous, block_t *current, block_t *next) { 8003d84: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8003d88: b089 sub sp, #36 ; 0x24 8003d8a: af02 add r7, sp, #8 8003d8c: 60f8 str r0, [r7, #12] 8003d8e: 60b9 str r1, [r7, #8] 8003d90: 607a str r2, [r7, #4] if(!previous) { return; } // Begin planning after buffer_tail 8003d92: 68fb ldr r3, [r7, #12] 8003d94: 2b00 cmp r3, #0 8003d96: d075 beq.n 8003e84 // If the previous block is an acceleration block, but it is not long enough to complete the // full speed change within the block, we need to adjust the entry speed accordingly. Entry // speeds have already been reset, maximized, and reverse planned by reverse planner. // If nominal length is true, max junction speed is guaranteed to be reached. No need to recheck. if (!previous->nominal_length_flag) { 8003d98: 68fb ldr r3, [r7, #12] 8003d9a: f893 3039 ldrb.w r3, [r3, #57] ; 0x39 8003d9e: 2b00 cmp r3, #0 8003da0: d171 bne.n 8003e86 if (previous->entry_speed < current->entry_speed) { 8003da2: 68fb ldr r3, [r7, #12] 8003da4: e9d3 0108 ldrd r0, r1, [r3, #32] 8003da8: 68bb ldr r3, [r7, #8] 8003daa: e9d3 2308 ldrd r2, r3, [r3, #32] 8003dae: f04f 0601 mov.w r6, #1 8003db2: f005 f987 bl 80090c4 <__aeabi_dcmplt> 8003db6: 4603 mov r3, r0 8003db8: 2b00 cmp r3, #0 8003dba: d102 bne.n 8003dc2 8003dbc: f04f 0300 mov.w r3, #0 8003dc0: 461e mov r6, r3 8003dc2: b2f3 uxtb r3, r6 8003dc4: 2b00 cmp r3, #0 8003dc6: d05e beq.n 8003e86 double entry_speed = min( current->entry_speed, 8003dc8: 68bb ldr r3, [r7, #8] 8003dca: e9d3 ab08 ldrd sl, fp, [r3, #32] 8003dce: f240 63d8 movw r3, #1752 ; 0x6d8 8003dd2: f2c2 0300 movt r3, #8192 ; 0x2000 8003dd6: e9d3 2310 ldrd r2, r3, [r3, #64] ; 0x40 8003dda: 4690 mov r8, r2 8003ddc: f083 4900 eor.w r9, r3, #2147483648 ; 0x80000000 8003de0: 68fb ldr r3, [r7, #12] 8003de2: e9d3 2308 ldrd r2, r3, [r3, #32] 8003de6: 68f9 ldr r1, [r7, #12] 8003de8: e9d1 010c ldrd r0, r1, [r1, #48] ; 0x30 8003dec: e9cd 0100 strd r0, r1, [sp] 8003df0: 4640 mov r0, r8 8003df2: 4649 mov r1, r9 8003df4: f7ff fec8 bl 8003b88 8003df8: 4602 mov r2, r0 8003dfa: 460b mov r3, r1 8003dfc: f04f 0101 mov.w r1, #1 8003e00: 460e mov r6, r1 8003e02: 4650 mov r0, sl 8003e04: 4659 mov r1, fp 8003e06: f005 f95d bl 80090c4 <__aeabi_dcmplt> 8003e0a: 4603 mov r3, r0 8003e0c: 2b00 cmp r3, #0 8003e0e: d102 bne.n 8003e16 8003e10: f04f 0300 mov.w r3, #0 8003e14: 461e mov r6, r3 8003e16: b2f3 uxtb r3, r6 8003e18: 2b00 cmp r3, #0 8003e1a: d003 beq.n 8003e24 8003e1c: 68bb ldr r3, [r7, #8] 8003e1e: e9d3 2308 ldrd r2, r3, [r3, #32] 8003e22: e016 b.n 8003e52 8003e24: f240 63d8 movw r3, #1752 ; 0x6d8 8003e28: f2c2 0300 movt r3, #8192 ; 0x2000 8003e2c: e9d3 2310 ldrd r2, r3, [r3, #64] ; 0x40 8003e30: 4614 mov r4, r2 8003e32: f083 4500 eor.w r5, r3, #2147483648 ; 0x80000000 8003e36: 68fb ldr r3, [r7, #12] 8003e38: e9d3 2308 ldrd r2, r3, [r3, #32] 8003e3c: 68f9 ldr r1, [r7, #12] 8003e3e: e9d1 010c ldrd r0, r1, [r1, #48] ; 0x30 8003e42: e9cd 0100 strd r0, r1, [sp] 8003e46: 4620 mov r0, r4 8003e48: 4629 mov r1, r5 8003e4a: f7ff fe9d bl 8003b88 8003e4e: 4602 mov r2, r0 8003e50: 460b mov r3, r1 8003e52: e9c7 2304 strd r2, r3, [r7, #16] max_allowable_speed(-settings.acceleration,previous->entry_speed,previous->millimeters) ); // Check for junction speed change if (current->entry_speed != entry_speed) { 8003e56: 68bb ldr r3, [r7, #8] 8003e58: e9d3 2308 ldrd r2, r3, [r3, #32] 8003e5c: 4610 mov r0, r2 8003e5e: 4619 mov r1, r3 8003e60: e9d7 2304 ldrd r2, r3, [r7, #16] 8003e64: f005 f924 bl 80090b0 <__aeabi_dcmpeq> 8003e68: 4603 mov r3, r0 8003e6a: 2b00 cmp r3, #0 8003e6c: d10b bne.n 8003e86 current->entry_speed = entry_speed; 8003e6e: 68b9 ldr r1, [r7, #8] 8003e70: e9d7 2304 ldrd r2, r3, [r7, #16] 8003e74: e9c1 2308 strd r2, r3, [r1, #32] current->recalculate_flag = true; 8003e78: 68bb ldr r3, [r7, #8] 8003e7a: f04f 0201 mov.w r2, #1 8003e7e: f883 2038 strb.w r2, [r3, #56] ; 0x38 8003e82: e000 b.n 8003e86 // The kernel called by planner_recalculate() when scanning the plan from first to last entry. static void planner_forward_pass_kernel(block_t *previous, block_t *current, block_t *next) { if(!previous) { return; } // Begin planning after buffer_tail 8003e84: bf00 nop current->entry_speed = entry_speed; current->recalculate_flag = true; } } } } 8003e86: f107 071c add.w r7, r7, #28 8003e8a: 46bd mov sp, r7 8003e8c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 08003e90 : // planner_recalculate() needs to go over the current plan twice. Once in reverse and once forward. This // implements the forward pass. static void planner_forward_pass() { 8003e90: b580 push {r7, lr} 8003e92: b084 sub sp, #16 8003e94: af00 add r7, sp, #0 uint8_t block_index = block_buffer_tail; 8003e96: f240 6399 movw r3, #1689 ; 0x699 8003e9a: f2c2 0300 movt r3, #8192 ; 0x2000 8003e9e: 781b ldrb r3, [r3, #0] 8003ea0: 73fb strb r3, [r7, #15] block_t *block[3] = {NULL, NULL, NULL}; 8003ea2: f04f 0300 mov.w r3, #0 8003ea6: 603b str r3, [r7, #0] 8003ea8: f04f 0300 mov.w r3, #0 8003eac: 607b str r3, [r7, #4] 8003eae: f04f 0300 mov.w r3, #0 8003eb2: 60bb str r3, [r7, #8] while(block_index != block_buffer_head) { 8003eb4: e01c b.n 8003ef0 block[0] = block[1]; 8003eb6: 687b ldr r3, [r7, #4] 8003eb8: 603b str r3, [r7, #0] block[1] = block[2]; 8003eba: 68bb ldr r3, [r7, #8] 8003ebc: 607b str r3, [r7, #4] block[2] = &block_buffer[block_index]; 8003ebe: 7bfb ldrb r3, [r7, #15] 8003ec0: f04f 0258 mov.w r2, #88 ; 0x58 8003ec4: fb02 f203 mul.w r2, r2, r3 8003ec8: f240 43e0 movw r3, #1248 ; 0x4e0 8003ecc: f2c2 0300 movt r3, #8192 ; 0x2000 8003ed0: 18d3 adds r3, r2, r3 8003ed2: 60bb str r3, [r7, #8] planner_forward_pass_kernel(block[0],block[1],block[2]); 8003ed4: 6839 ldr r1, [r7, #0] 8003ed6: 687a ldr r2, [r7, #4] 8003ed8: 68bb ldr r3, [r7, #8] 8003eda: 4608 mov r0, r1 8003edc: 4611 mov r1, r2 8003ede: 461a mov r2, r3 8003ee0: f7ff ff50 bl 8003d84 block_index = next_block_index( block_index ); 8003ee4: 7bfb ldrb r3, [r7, #15] 8003ee6: 4618 mov r0, r3 8003ee8: f7ff fd96 bl 8003a18 8003eec: 4603 mov r3, r0 8003eee: 73fb strb r3, [r7, #15] static void planner_forward_pass() { uint8_t block_index = block_buffer_tail; block_t *block[3] = {NULL, NULL, NULL}; while(block_index != block_buffer_head) { 8003ef0: f240 6398 movw r3, #1688 ; 0x698 8003ef4: f2c2 0300 movt r3, #8192 ; 0x2000 8003ef8: 781b ldrb r3, [r3, #0] 8003efa: b2db uxtb r3, r3 8003efc: 7bfa ldrb r2, [r7, #15] 8003efe: 429a cmp r2, r3 8003f00: d1d9 bne.n 8003eb6 block[1] = block[2]; block[2] = &block_buffer[block_index]; planner_forward_pass_kernel(block[0],block[1],block[2]); block_index = next_block_index( block_index ); } planner_forward_pass_kernel(block[1], block[2], NULL); 8003f02: 687a ldr r2, [r7, #4] 8003f04: 68bb ldr r3, [r7, #8] 8003f06: 4610 mov r0, r2 8003f08: 4619 mov r1, r3 8003f0a: f04f 0200 mov.w r2, #0 8003f0e: f7ff ff39 bl 8003d84 } 8003f12: f107 0710 add.w r7, r7, #16 8003f16: 46bd mov sp, r7 8003f18: bd80 pop {r7, pc} 8003f1a: bf00 nop 8003f1c: 0000 movs r0, r0 ... 08003f20 : // Calculates trapezoid parameters so that the entry- and exit-speed is compensated by the provided factors. // The factors represent a factor of braking and must be in the range 0.0-1.0. // This converts the planner parameters to the data required by the stepper controller. // NOTE: Final rates must be computed in terms of their respective blocks. static void calculate_trapezoid_for_block(block_t *block, double entry_factor, double exit_factor) { 8003f20: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} 8003f24: b08c sub sp, #48 ; 0x30 8003f26: af04 add r7, sp, #16 8003f28: 60f8 str r0, [r7, #12] 8003f2a: e9c7 2300 strd r2, r3, [r7] block->initial_rate = ceil(block->nominal_rate*entry_factor); // (step/min) 8003f2e: 68fb ldr r3, [r7, #12] 8003f30: 6d1b ldr r3, [r3, #80] ; 0x50 8003f32: 4618 mov r0, r3 8003f34: f004 fdde bl 8008af4 <__aeabi_ui2d> 8003f38: 4602 mov r2, r0 8003f3a: 460b mov r3, r1 8003f3c: 4610 mov r0, r2 8003f3e: 4619 mov r1, r3 8003f40: e9d7 2300 ldrd r2, r3, [r7] 8003f44: f004 fe4c bl 8008be0 <__aeabi_dmul> 8003f48: 4602 mov r2, r0 8003f4a: 460b mov r3, r1 8003f4c: 4610 mov r0, r2 8003f4e: 4619 mov r1, r3 8003f50: f001 ec0e blx 8005770 8003f54: 4602 mov r2, r0 8003f56: 460b mov r3, r1 8003f58: 4610 mov r0, r2 8003f5a: 4619 mov r1, r3 8003f5c: f005 f902 bl 8009164 <__aeabi_d2uiz> 8003f60: 4602 mov r2, r0 8003f62: 68fb ldr r3, [r7, #12] 8003f64: 63da str r2, [r3, #60] ; 0x3c block->final_rate = ceil(block->nominal_rate*exit_factor); // (step/min) 8003f66: 68fb ldr r3, [r7, #12] 8003f68: 6d1b ldr r3, [r3, #80] ; 0x50 8003f6a: 4618 mov r0, r3 8003f6c: f004 fdc2 bl 8008af4 <__aeabi_ui2d> 8003f70: 4602 mov r2, r0 8003f72: 460b mov r3, r1 8003f74: 4610 mov r0, r2 8003f76: 4619 mov r1, r3 8003f78: e9d7 2310 ldrd r2, r3, [r7, #64] ; 0x40 8003f7c: f004 fe30 bl 8008be0 <__aeabi_dmul> 8003f80: 4602 mov r2, r0 8003f82: 460b mov r3, r1 8003f84: 4610 mov r0, r2 8003f86: 4619 mov r1, r3 8003f88: f001 ebf2 blx 8005770 8003f8c: 4602 mov r2, r0 8003f8e: 460b mov r3, r1 8003f90: 4610 mov r0, r2 8003f92: 4619 mov r1, r3 8003f94: f005 f8e6 bl 8009164 <__aeabi_d2uiz> 8003f98: 4602 mov r2, r0 8003f9a: 68fb ldr r3, [r7, #12] 8003f9c: 641a str r2, [r3, #64] ; 0x40 int32_t acceleration_per_minute = block->rate_delta*ACCELERATION_TICKS_PER_SECOND*60.0; // (step/min^2) 8003f9e: 68fb ldr r3, [r7, #12] 8003fa0: 6c5b ldr r3, [r3, #68] ; 0x44 8003fa2: f04f 0232 mov.w r2, #50 ; 0x32 8003fa6: fb02 f303 mul.w r3, r2, r3 8003faa: 4618 mov r0, r3 8003fac: f004 fdb2 bl 8008b14 <__aeabi_i2d> 8003fb0: 4602 mov r2, r0 8003fb2: 460b mov r3, r1 8003fb4: 4610 mov r0, r2 8003fb6: 4619 mov r1, r3 8003fb8: a35d add r3, pc, #372 ; (adr r3, 8004130 ) 8003fba: e9d3 2300 ldrd r2, r3, [r3] 8003fbe: f004 fe0f bl 8008be0 <__aeabi_dmul> 8003fc2: 4602 mov r2, r0 8003fc4: 460b mov r3, r1 8003fc6: 4610 mov r0, r2 8003fc8: 4619 mov r1, r3 8003fca: f005 f8a3 bl 8009114 <__aeabi_d2iz> 8003fce: 4603 mov r3, r0 8003fd0: 617b str r3, [r7, #20] int32_t accelerate_steps = ceil(estimate_acceleration_distance(block->initial_rate, block->nominal_rate, acceleration_per_minute)); 8003fd2: 68fb ldr r3, [r7, #12] 8003fd4: 6bdb ldr r3, [r3, #60] ; 0x3c 8003fd6: 4618 mov r0, r3 8003fd8: f004 fd8c bl 8008af4 <__aeabi_ui2d> 8003fdc: 4680 mov r8, r0 8003fde: 4689 mov r9, r1 8003fe0: 68fb ldr r3, [r7, #12] 8003fe2: 6d1b ldr r3, [r3, #80] ; 0x50 8003fe4: 4618 mov r0, r3 8003fe6: f004 fd85 bl 8008af4 <__aeabi_ui2d> 8003fea: 4604 mov r4, r0 8003fec: 460d mov r5, r1 8003fee: 6978 ldr r0, [r7, #20] 8003ff0: f004 fd90 bl 8008b14 <__aeabi_i2d> 8003ff4: 4602 mov r2, r0 8003ff6: 460b mov r3, r1 8003ff8: e9cd 2300 strd r2, r3, [sp] 8003ffc: 4640 mov r0, r8 8003ffe: 4649 mov r1, r9 8004000: 4622 mov r2, r4 8004002: 462b mov r3, r5 8004004: f7ff fd34 bl 8003a70 8004008: 4602 mov r2, r0 800400a: 460b mov r3, r1 800400c: 4610 mov r0, r2 800400e: 4619 mov r1, r3 8004010: f001 ebae blx 8005770 8004014: 4602 mov r2, r0 8004016: 460b mov r3, r1 static void calculate_trapezoid_for_block(block_t *block, double entry_factor, double exit_factor) { block->initial_rate = ceil(block->nominal_rate*entry_factor); // (step/min) block->final_rate = ceil(block->nominal_rate*exit_factor); // (step/min) int32_t acceleration_per_minute = block->rate_delta*ACCELERATION_TICKS_PER_SECOND*60.0; // (step/min^2) int32_t accelerate_steps = 8004018: 4610 mov r0, r2 800401a: 4619 mov r1, r3 800401c: f005 f87a bl 8009114 <__aeabi_d2iz> 8004020: 4603 mov r3, r0 8004022: 61fb str r3, [r7, #28] ceil(estimate_acceleration_distance(block->initial_rate, block->nominal_rate, acceleration_per_minute)); int32_t decelerate_steps = floor(estimate_acceleration_distance(block->nominal_rate, block->final_rate, -acceleration_per_minute)); 8004024: 68fb ldr r3, [r7, #12] 8004026: 6d1b ldr r3, [r3, #80] ; 0x50 8004028: 4618 mov r0, r3 800402a: f004 fd63 bl 8008af4 <__aeabi_ui2d> 800402e: 4680 mov r8, r0 8004030: 4689 mov r9, r1 8004032: 68fb ldr r3, [r7, #12] 8004034: 6c1b ldr r3, [r3, #64] ; 0x40 8004036: 4618 mov r0, r3 8004038: f004 fd5c bl 8008af4 <__aeabi_ui2d> 800403c: 4604 mov r4, r0 800403e: 460d mov r5, r1 8004040: 697b ldr r3, [r7, #20] 8004042: f1c3 0300 rsb r3, r3, #0 8004046: 4618 mov r0, r3 8004048: f004 fd64 bl 8008b14 <__aeabi_i2d> 800404c: 4602 mov r2, r0 800404e: 460b mov r3, r1 8004050: e9cd 2300 strd r2, r3, [sp] 8004054: 4640 mov r0, r8 8004056: 4649 mov r1, r9 8004058: 4622 mov r2, r4 800405a: 462b mov r3, r5 800405c: f7ff fd08 bl 8003a70 8004060: 4602 mov r2, r0 8004062: 460b mov r3, r1 8004064: 4610 mov r0, r2 8004066: 4619 mov r1, r3 8004068: f001 ecca blx 8005a00 800406c: 4602 mov r2, r0 800406e: 460b mov r3, r1 block->initial_rate = ceil(block->nominal_rate*entry_factor); // (step/min) block->final_rate = ceil(block->nominal_rate*exit_factor); // (step/min) int32_t acceleration_per_minute = block->rate_delta*ACCELERATION_TICKS_PER_SECOND*60.0; // (step/min^2) int32_t accelerate_steps = ceil(estimate_acceleration_distance(block->initial_rate, block->nominal_rate, acceleration_per_minute)); int32_t decelerate_steps = 8004070: 4610 mov r0, r2 8004072: 4619 mov r1, r3 8004074: f005 f84e bl 8009114 <__aeabi_d2iz> 8004078: 4603 mov r3, r0 800407a: 613b str r3, [r7, #16] floor(estimate_acceleration_distance(block->nominal_rate, block->final_rate, -acceleration_per_minute)); // Calculate the size of Plateau of Nominal Rate. int32_t plateau_steps = block->step_event_count-accelerate_steps-decelerate_steps; 800407c: 68fb ldr r3, [r7, #12] 800407e: 691a ldr r2, [r3, #16] 8004080: 69fb ldr r3, [r7, #28] 8004082: 1ad2 subs r2, r2, r3 8004084: 693b ldr r3, [r7, #16] 8004086: 1ad3 subs r3, r2, r3 8004088: 61bb str r3, [r7, #24] // Is the Plateau of Nominal Rate smaller than nothing? That means no cruising, and we will // have to use intersection_distance() to calculate when to abort acceleration and start braking // in order to reach the final_rate exactly at the end of this block. if (plateau_steps < 0) { 800408a: 69bb ldr r3, [r7, #24] 800408c: 2b00 cmp r3, #0 800408e: da3f bge.n 8004110 accelerate_steps = ceil( intersection_distance(block->initial_rate, block->final_rate, acceleration_per_minute, block->step_event_count)); 8004090: 68fb ldr r3, [r7, #12] 8004092: 6bdb ldr r3, [r3, #60] ; 0x3c // Is the Plateau of Nominal Rate smaller than nothing? That means no cruising, and we will // have to use intersection_distance() to calculate when to abort acceleration and start braking // in order to reach the final_rate exactly at the end of this block. if (plateau_steps < 0) { accelerate_steps = ceil( 8004094: 4618 mov r0, r3 8004096: f004 fd2d bl 8008af4 <__aeabi_ui2d> 800409a: 4680 mov r8, r0 800409c: 4689 mov r9, r1 intersection_distance(block->initial_rate, block->final_rate, acceleration_per_minute, block->step_event_count)); 800409e: 68fb ldr r3, [r7, #12] 80040a0: 6c1b ldr r3, [r3, #64] ; 0x40 // Is the Plateau of Nominal Rate smaller than nothing? That means no cruising, and we will // have to use intersection_distance() to calculate when to abort acceleration and start braking // in order to reach the final_rate exactly at the end of this block. if (plateau_steps < 0) { accelerate_steps = ceil( 80040a2: 4618 mov r0, r3 80040a4: f004 fd26 bl 8008af4 <__aeabi_ui2d> 80040a8: 4604 mov r4, r0 80040aa: 460d mov r5, r1 80040ac: 6978 ldr r0, [r7, #20] 80040ae: f004 fd31 bl 8008b14 <__aeabi_i2d> 80040b2: 4682 mov sl, r0 80040b4: 468b mov fp, r1 intersection_distance(block->initial_rate, block->final_rate, acceleration_per_minute, block->step_event_count)); 80040b6: 68fb ldr r3, [r7, #12] 80040b8: 691b ldr r3, [r3, #16] // Is the Plateau of Nominal Rate smaller than nothing? That means no cruising, and we will // have to use intersection_distance() to calculate when to abort acceleration and start braking // in order to reach the final_rate exactly at the end of this block. if (plateau_steps < 0) { accelerate_steps = ceil( 80040ba: 4618 mov r0, r3 80040bc: f004 fd2a bl 8008b14 <__aeabi_i2d> 80040c0: 4602 mov r2, r0 80040c2: 460b mov r3, r1 80040c4: e9cd ab00 strd sl, fp, [sp] 80040c8: e9cd 2302 strd r2, r3, [sp, #8] 80040cc: 4640 mov r0, r8 80040ce: 4649 mov r1, r9 80040d0: 4622 mov r2, r4 80040d2: 462b mov r3, r5 80040d4: f7ff fd04 bl 8003ae0 80040d8: 4602 mov r2, r0 80040da: 460b mov r3, r1 80040dc: 4610 mov r0, r2 80040de: 4619 mov r1, r3 80040e0: f001 eb46 blx 8005770 80040e4: 4602 mov r2, r0 80040e6: 460b mov r3, r1 80040e8: 4610 mov r0, r2 80040ea: 4619 mov r1, r3 80040ec: f005 f812 bl 8009114 <__aeabi_d2iz> 80040f0: 4603 mov r3, r0 80040f2: 61fb str r3, [r7, #28] intersection_distance(block->initial_rate, block->final_rate, acceleration_per_minute, block->step_event_count)); accelerate_steps = max(accelerate_steps,0); // Check limits due to numerical round-off 80040f4: 69fb ldr r3, [r7, #28] 80040f6: ea23 73e3 bic.w r3, r3, r3, asr #31 80040fa: 61fb str r3, [r7, #28] accelerate_steps = min(accelerate_steps,block->step_event_count); 80040fc: 68fb ldr r3, [r7, #12] 80040fe: 691b ldr r3, [r3, #16] 8004100: 69fa ldr r2, [r7, #28] 8004102: 429a cmp r2, r3 8004104: bfb8 it lt 8004106: 4613 movlt r3, r2 8004108: 61fb str r3, [r7, #28] plateau_steps = 0; 800410a: f04f 0300 mov.w r3, #0 800410e: 61bb str r3, [r7, #24] } block->accelerate_until = accelerate_steps; 8004110: 69fa ldr r2, [r7, #28] 8004112: 68fb ldr r3, [r7, #12] 8004114: 649a str r2, [r3, #72] ; 0x48 block->decelerate_after = accelerate_steps+plateau_steps; 8004116: 69fa ldr r2, [r7, #28] 8004118: 69bb ldr r3, [r7, #24] 800411a: 18d3 adds r3, r2, r3 800411c: 461a mov r2, r3 800411e: 68fb ldr r3, [r7, #12] 8004120: 64da str r2, [r3, #76] ; 0x4c } 8004122: f107 0720 add.w r7, r7, #32 8004126: 46bd mov sp, r7 8004128: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} 800412c: f3af 8000 nop.w 8004130: 00000000 .word 0x00000000 8004134: 404e0000 .word 0x404e0000 08004138 : // entry_speed for each junction and the entry_speed of the next junction. Must be called by // planner_recalculate() after updating the blocks. Any recalulate flagged junction will // compute the two adjacent trapezoids to the junction, since the junction speed corresponds // to exit speed and entry speed of one another. static void planner_recalculate_trapezoids() { 8004138: b5b0 push {r4, r5, r7, lr} 800413a: b086 sub sp, #24 800413c: af02 add r7, sp, #8 uint8_t block_index = block_buffer_tail; 800413e: f240 6399 movw r3, #1689 ; 0x699 8004142: f2c2 0300 movt r3, #8192 ; 0x2000 8004146: 781b ldrb r3, [r3, #0] 8004148: 73fb strb r3, [r7, #15] block_t *current; block_t *next = NULL; 800414a: f04f 0300 mov.w r3, #0 800414e: 60bb str r3, [r7, #8] while(block_index != block_buffer_head) { 8004150: e041 b.n 80041d6 current = next; 8004152: 68bb ldr r3, [r7, #8] 8004154: 607b str r3, [r7, #4] next = &block_buffer[block_index]; 8004156: 7bfb ldrb r3, [r7, #15] 8004158: f04f 0258 mov.w r2, #88 ; 0x58 800415c: fb02 f203 mul.w r2, r2, r3 8004160: f240 43e0 movw r3, #1248 ; 0x4e0 8004164: f2c2 0300 movt r3, #8192 ; 0x2000 8004168: 18d3 adds r3, r2, r3 800416a: 60bb str r3, [r7, #8] if (current) { 800416c: 687b ldr r3, [r7, #4] 800416e: 2b00 cmp r3, #0 8004170: d02b beq.n 80041ca // Recalculate if current block entry or exit junction speed has changed. if (current->recalculate_flag || next->recalculate_flag) { 8004172: 687b ldr r3, [r7, #4] 8004174: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 8004178: 2b00 cmp r3, #0 800417a: d104 bne.n 8004186 800417c: 68bb ldr r3, [r7, #8] 800417e: f893 3038 ldrb.w r3, [r3, #56] ; 0x38 8004182: 2b00 cmp r3, #0 8004184: d021 beq.n 80041ca // NOTE: Entry and exit factors always > 0 by all previous logic operations. calculate_trapezoid_for_block(current, current->entry_speed/current->nominal_speed, 8004186: 687b ldr r3, [r7, #4] 8004188: e9d3 0108 ldrd r0, r1, [r3, #32] 800418c: 687b ldr r3, [r7, #4] 800418e: e9d3 2306 ldrd r2, r3, [r3, #24] 8004192: f004 fe4f bl 8008e34 <__aeabi_ddiv> 8004196: 4602 mov r2, r0 8004198: 460b mov r3, r1 800419a: 4614 mov r4, r2 800419c: 461d mov r5, r3 next->entry_speed/current->nominal_speed); 800419e: 68bb ldr r3, [r7, #8] 80041a0: e9d3 0108 ldrd r0, r1, [r3, #32] 80041a4: 687b ldr r3, [r7, #4] 80041a6: e9d3 2306 ldrd r2, r3, [r3, #24] next = &block_buffer[block_index]; if (current) { // Recalculate if current block entry or exit junction speed has changed. if (current->recalculate_flag || next->recalculate_flag) { // NOTE: Entry and exit factors always > 0 by all previous logic operations. calculate_trapezoid_for_block(current, current->entry_speed/current->nominal_speed, 80041aa: f004 fe43 bl 8008e34 <__aeabi_ddiv> 80041ae: 4602 mov r2, r0 80041b0: 460b mov r3, r1 80041b2: e9cd 2300 strd r2, r3, [sp] 80041b6: 6878 ldr r0, [r7, #4] 80041b8: 4622 mov r2, r4 80041ba: 462b mov r3, r5 80041bc: f7ff feb0 bl 8003f20 next->entry_speed/current->nominal_speed); current->recalculate_flag = false; // Reset current only to ensure next trapezoid is computed 80041c0: 687b ldr r3, [r7, #4] 80041c2: f04f 0200 mov.w r2, #0 80041c6: f883 2038 strb.w r2, [r3, #56] ; 0x38 } } block_index = next_block_index( block_index ); 80041ca: 7bfb ldrb r3, [r7, #15] 80041cc: 4618 mov r0, r3 80041ce: f7ff fc23 bl 8003a18 80041d2: 4603 mov r3, r0 80041d4: 73fb strb r3, [r7, #15] { uint8_t block_index = block_buffer_tail; block_t *current; block_t *next = NULL; while(block_index != block_buffer_head) { 80041d6: f240 6398 movw r3, #1688 ; 0x698 80041da: f2c2 0300 movt r3, #8192 ; 0x2000 80041de: 781b ldrb r3, [r3, #0] 80041e0: b2db uxtb r3, r3 80041e2: 7bfa ldrb r2, [r7, #15] 80041e4: 429a cmp r2, r3 80041e6: d1b4 bne.n 8004152 } } block_index = next_block_index( block_index ); } // Last/newest block in buffer. Exit speed is set with MINIMUM_PLANNER_SPEED. Always recalculated. calculate_trapezoid_for_block(next, next->entry_speed/next->nominal_speed, 80041e8: 68bb ldr r3, [r7, #8] 80041ea: e9d3 0108 ldrd r0, r1, [r3, #32] 80041ee: 68bb ldr r3, [r7, #8] 80041f0: e9d3 2306 ldrd r2, r3, [r3, #24] 80041f4: f004 fe1e bl 8008e34 <__aeabi_ddiv> 80041f8: 4602 mov r2, r0 80041fa: 460b mov r3, r1 80041fc: 4614 mov r4, r2 80041fe: 461d mov r5, r3 MINIMUM_PLANNER_SPEED/next->nominal_speed); 8004200: 68bb ldr r3, [r7, #8] 8004202: e9d3 2306 ldrd r2, r3, [r3, #24] } } block_index = next_block_index( block_index ); } // Last/newest block in buffer. Exit speed is set with MINIMUM_PLANNER_SPEED. Always recalculated. calculate_trapezoid_for_block(next, next->entry_speed/next->nominal_speed, 8004206: a10c add r1, pc, #48 ; (adr r1, 8004238 ) 8004208: e9d1 0100 ldrd r0, r1, [r1] 800420c: f004 fe12 bl 8008e34 <__aeabi_ddiv> 8004210: 4602 mov r2, r0 8004212: 460b mov r3, r1 8004214: e9cd 2300 strd r2, r3, [sp] 8004218: 68b8 ldr r0, [r7, #8] 800421a: 4622 mov r2, r4 800421c: 462b mov r3, r5 800421e: f7ff fe7f bl 8003f20 MINIMUM_PLANNER_SPEED/next->nominal_speed); next->recalculate_flag = false; 8004222: 68bb ldr r3, [r7, #8] 8004224: f04f 0200 mov.w r2, #0 8004228: f883 2038 strb.w r2, [r3, #56] ; 0x38 } 800422c: f107 0710 add.w r7, r7, #16 8004230: 46bd mov sp, r7 8004232: bdb0 pop {r4, r5, r7, pc} 8004234: f3af 8000 nop.w ... 08004240 : // // All planner computations are performed with doubles (float on Arduinos) to minimize numerical round- // off errors. Only when planned values are converted to stepper rate parameters, these are integers. static void planner_recalculate() { 8004240: b580 push {r7, lr} 8004242: af00 add r7, sp, #0 planner_reverse_pass(); 8004244: f7ff fd60 bl 8003d08 planner_forward_pass(); 8004248: f7ff fe22 bl 8003e90 planner_recalculate_trapezoids(); 800424c: f7ff ff74 bl 8004138 } 8004250: bd80 pop {r7, pc} 8004252: bf00 nop 8004254: 0000 movs r0, r0 ... 08004258 : void plan_init() { 8004258: b480 push {r7} 800425a: af00 add r7, sp, #0 block_buffer_head = 0; 800425c: f240 6398 movw r3, #1688 ; 0x698 8004260: f2c2 0300 movt r3, #8192 ; 0x2000 8004264: f04f 0200 mov.w r2, #0 8004268: 701a strb r2, [r3, #0] block_buffer_tail = 0; 800426a: f240 6399 movw r3, #1689 ; 0x699 800426e: f2c2 0300 movt r3, #8192 ; 0x2000 8004272: f04f 0200 mov.w r2, #0 8004276: 701a strb r2, [r3, #0] clear_vector(position); 8004278: f240 639c movw r3, #1692 ; 0x69c 800427c: f2c2 0300 movt r3, #8192 ; 0x2000 8004280: f04f 0200 mov.w r2, #0 8004284: 601a str r2, [r3, #0] 8004286: f103 0304 add.w r3, r3, #4 800428a: f04f 0200 mov.w r2, #0 800428e: 601a str r2, [r3, #0] 8004290: f103 0304 add.w r3, r3, #4 8004294: f04f 0200 mov.w r2, #0 8004298: 601a str r2, [r3, #0] 800429a: f103 0304 add.w r3, r3, #4 clear_vector_double(previous_unit_vec); 800429e: f240 63a8 movw r3, #1704 ; 0x6a8 80042a2: f2c2 0300 movt r3, #8192 ; 0x2000 80042a6: f04f 0200 mov.w r2, #0 80042aa: 601a str r2, [r3, #0] 80042ac: f103 0304 add.w r3, r3, #4 80042b0: f04f 0200 mov.w r2, #0 80042b4: 601a str r2, [r3, #0] 80042b6: f103 0304 add.w r3, r3, #4 80042ba: f04f 0200 mov.w r2, #0 80042be: 601a str r2, [r3, #0] 80042c0: f103 0304 add.w r3, r3, #4 80042c4: f04f 0200 mov.w r2, #0 80042c8: 601a str r2, [r3, #0] 80042ca: f103 0304 add.w r3, r3, #4 80042ce: f04f 0200 mov.w r2, #0 80042d2: 601a str r2, [r3, #0] 80042d4: f103 0304 add.w r3, r3, #4 80042d8: f04f 0200 mov.w r2, #0 80042dc: 601a str r2, [r3, #0] 80042de: f103 0304 add.w r3, r3, #4 previous_nominal_speed = 0.0; 80042e2: f240 63c0 movw r3, #1728 ; 0x6c0 80042e6: f2c2 0300 movt r3, #8192 ; 0x2000 80042ea: a105 add r1, pc, #20 ; (adr r1, 8004300 ) 80042ec: e9d1 0100 ldrd r0, r1, [r1] 80042f0: e9c3 0100 strd r0, r1, [r3] } 80042f4: 46bd mov sp, r7 80042f6: bc80 pop {r7} 80042f8: 4770 bx lr 80042fa: bf00 nop 80042fc: f3af 8000 nop.w ... 08004308 : void plan_discard_current_block() { 8004308: b580 push {r7, lr} 800430a: af00 add r7, sp, #0 if (block_buffer_head != block_buffer_tail) { 800430c: f240 6398 movw r3, #1688 ; 0x698 8004310: f2c2 0300 movt r3, #8192 ; 0x2000 8004314: 781b ldrb r3, [r3, #0] 8004316: b2da uxtb r2, r3 8004318: f240 6399 movw r3, #1689 ; 0x699 800431c: f2c2 0300 movt r3, #8192 ; 0x2000 8004320: 781b ldrb r3, [r3, #0] 8004322: b2db uxtb r3, r3 8004324: 429a cmp r2, r3 8004326: d00f beq.n 8004348 block_buffer_tail = next_block_index( block_buffer_tail ); 8004328: f240 6399 movw r3, #1689 ; 0x699 800432c: f2c2 0300 movt r3, #8192 ; 0x2000 8004330: 781b ldrb r3, [r3, #0] 8004332: b2db uxtb r3, r3 8004334: 4618 mov r0, r3 8004336: f7ff fb6f bl 8003a18 800433a: 4603 mov r3, r0 800433c: 461a mov r2, r3 800433e: f240 6399 movw r3, #1689 ; 0x699 8004342: f2c2 0300 movt r3, #8192 ; 0x2000 8004346: 701a strb r2, [r3, #0] } } 8004348: bd80 pop {r7, pc} 800434a: bf00 nop 0800434c : block_t *plan_get_current_block() { 800434c: b480 push {r7} 800434e: af00 add r7, sp, #0 if (block_buffer_head == block_buffer_tail) { return(NULL); } 8004350: f240 6398 movw r3, #1688 ; 0x698 8004354: f2c2 0300 movt r3, #8192 ; 0x2000 8004358: 781b ldrb r3, [r3, #0] 800435a: b2da uxtb r2, r3 800435c: f240 6399 movw r3, #1689 ; 0x699 8004360: f2c2 0300 movt r3, #8192 ; 0x2000 8004364: 781b ldrb r3, [r3, #0] 8004366: b2db uxtb r3, r3 8004368: 429a cmp r2, r3 800436a: d102 bne.n 8004372 800436c: f04f 0300 mov.w r3, #0 8004370: e00e b.n 8004390 return(&block_buffer[block_buffer_tail]); 8004372: f240 6399 movw r3, #1689 ; 0x699 8004376: f2c2 0300 movt r3, #8192 ; 0x2000 800437a: 781b ldrb r3, [r3, #0] 800437c: b2db uxtb r3, r3 800437e: f04f 0258 mov.w r2, #88 ; 0x58 8004382: fb02 f203 mul.w r2, r2, r3 8004386: f240 43e0 movw r3, #1248 ; 0x4e0 800438a: f2c2 0300 movt r3, #8192 ; 0x2000 800438e: 18d3 adds r3, r2, r3 } 8004390: 4618 mov r0, r3 8004392: 46bd mov sp, r7 8004394: bc80 pop {r7} 8004396: 4770 bx lr 08004398 : // Add a new linear movement to the buffer. x, y and z is the signed, absolute target position in // millimeters. Feed rate specifies the speed of the motion. If feed rate is inverted, the feed // rate is taken to mean "frequency" and would complete the operation in 1/feed_rate minutes. void plan_buffer_line(double x, double y, double z, double feed_rate, uint8_t invert_feed_rate) { 8004398: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 800439c: b0a5 sub sp, #148 ; 0x94 800439e: af02 add r7, sp, #8 80043a0: e9c7 0102 strd r0, r1, [r7, #8] 80043a4: e9c7 2300 strd r2, r3, [r7] // Calculate target position in absolute steps int32_t target[3]; target[X_AXIS] = lround(x*settings.steps_per_mm[X_AXIS]); 80043a8: f240 63d8 movw r3, #1752 ; 0x6d8 80043ac: f2c2 0300 movt r3, #8192 ; 0x2000 80043b0: e9d3 2300 ldrd r2, r3, [r3] 80043b4: 4610 mov r0, r2 80043b6: 4619 mov r1, r3 80043b8: e9d7 2302 ldrd r2, r3, [r7, #8] 80043bc: f004 fc10 bl 8008be0 <__aeabi_dmul> 80043c0: 4602 mov r2, r0 80043c2: 460b mov r3, r1 80043c4: 4610 mov r0, r2 80043c6: 4619 mov r1, r3 80043c8: f001 ebf6 blx 8005bb8 80043cc: 4603 mov r3, r0 80043ce: 647b str r3, [r7, #68] ; 0x44 target[Y_AXIS] = lround(y*settings.steps_per_mm[Y_AXIS]); 80043d0: f240 63d8 movw r3, #1752 ; 0x6d8 80043d4: f2c2 0300 movt r3, #8192 ; 0x2000 80043d8: e9d3 2302 ldrd r2, r3, [r3, #8] 80043dc: 4610 mov r0, r2 80043de: 4619 mov r1, r3 80043e0: e9d7 2300 ldrd r2, r3, [r7] 80043e4: f004 fbfc bl 8008be0 <__aeabi_dmul> 80043e8: 4602 mov r2, r0 80043ea: 460b mov r3, r1 80043ec: 4610 mov r0, r2 80043ee: 4619 mov r1, r3 80043f0: f001 ebe2 blx 8005bb8 80043f4: 4603 mov r3, r0 80043f6: 64bb str r3, [r7, #72] ; 0x48 target[Z_AXIS] = lround(z*settings.steps_per_mm[Z_AXIS]); 80043f8: f240 63d8 movw r3, #1752 ; 0x6d8 80043fc: f2c2 0300 movt r3, #8192 ; 0x2000 8004400: e9d3 2304 ldrd r2, r3, [r3, #16] 8004404: 4610 mov r0, r2 8004406: 4619 mov r1, r3 8004408: e9d7 232c ldrd r2, r3, [r7, #176] ; 0xb0 800440c: f004 fbe8 bl 8008be0 <__aeabi_dmul> 8004410: 4602 mov r2, r0 8004412: 460b mov r3, r1 8004414: 4610 mov r0, r2 8004416: 4619 mov r1, r3 8004418: f001 ebce blx 8005bb8 800441c: 4603 mov r3, r0 800441e: 64fb str r3, [r7, #76] ; 0x4c // Calculate the buffer head after we push this byte uint8_t next_buffer_head = next_block_index( block_buffer_head ); 8004420: f240 6398 movw r3, #1688 ; 0x698 8004424: f2c2 0300 movt r3, #8192 ; 0x2000 8004428: 781b ldrb r3, [r3, #0] 800442a: b2db uxtb r3, r3 800442c: 4618 mov r0, r3 800442e: f7ff faf3 bl 8003a18 8004432: 4603 mov r3, r0 8004434: f887 3077 strb.w r3, [r7, #119] ; 0x77 // If the buffer is full: good! That means we are well ahead of the robot. // Rest here until there is room in the buffer. while(block_buffer_tail == next_buffer_head) { sleep_mode(); } 8004438: e001 b.n 800443e 800443a: f7fe fb51 bl 8002ae0 800443e: f240 6399 movw r3, #1689 ; 0x699 8004442: f2c2 0300 movt r3, #8192 ; 0x2000 8004446: 781b ldrb r3, [r3, #0] 8004448: b2db uxtb r3, r3 800444a: f897 2077 ldrb.w r2, [r7, #119] ; 0x77 800444e: 429a cmp r2, r3 8004450: d0f3 beq.n 800443a // Prepare to set up new block block_t *block = &block_buffer[block_buffer_head]; 8004452: f240 6398 movw r3, #1688 ; 0x698 8004456: f2c2 0300 movt r3, #8192 ; 0x2000 800445a: 781b ldrb r3, [r3, #0] 800445c: b2db uxtb r3, r3 800445e: f04f 0258 mov.w r2, #88 ; 0x58 8004462: fb02 f203 mul.w r2, r2, r3 8004466: f240 43e0 movw r3, #1248 ; 0x4e0 800446a: f2c2 0300 movt r3, #8192 ; 0x2000 800446e: 18d3 adds r3, r2, r3 8004470: 673b str r3, [r7, #112] ; 0x70 // Compute direction bits for this block block->direction_bits = 0; 8004472: 6f3b ldr r3, [r7, #112] ; 0x70 8004474: f04f 0200 mov.w r2, #0 8004478: 701a strb r2, [r3, #0] if (target[X_AXIS] < position[X_AXIS]) { block->direction_bits |= X_DIRECTION_BIT; } 800447a: 6c7a ldr r2, [r7, #68] ; 0x44 800447c: f240 639c movw r3, #1692 ; 0x69c 8004480: f2c2 0300 movt r3, #8192 ; 0x2000 8004484: 681b ldr r3, [r3, #0] 8004486: 429a cmp r2, r3 8004488: da06 bge.n 8004498 800448a: 6f3b ldr r3, [r7, #112] ; 0x70 800448c: 781b ldrb r3, [r3, #0] 800448e: f043 0320 orr.w r3, r3, #32 8004492: b2da uxtb r2, r3 8004494: 6f3b ldr r3, [r7, #112] ; 0x70 8004496: 701a strb r2, [r3, #0] if (target[Y_AXIS] < position[Y_AXIS]) { block->direction_bits |= Y_DIRECTION_BIT; } 8004498: 6cba ldr r2, [r7, #72] ; 0x48 800449a: f240 639c movw r3, #1692 ; 0x69c 800449e: f2c2 0300 movt r3, #8192 ; 0x2000 80044a2: 685b ldr r3, [r3, #4] 80044a4: 429a cmp r2, r3 80044a6: da06 bge.n 80044b6 80044a8: 6f3b ldr r3, [r7, #112] ; 0x70 80044aa: 781b ldrb r3, [r3, #0] 80044ac: f043 0340 orr.w r3, r3, #64 ; 0x40 80044b0: b2da uxtb r2, r3 80044b2: 6f3b ldr r3, [r7, #112] ; 0x70 80044b4: 701a strb r2, [r3, #0] if (target[Z_AXIS] < position[Z_AXIS]) { block->direction_bits |= Z_DIRECTION_BIT; } 80044b6: 6cfa ldr r2, [r7, #76] ; 0x4c 80044b8: f240 639c movw r3, #1692 ; 0x69c 80044bc: f2c2 0300 movt r3, #8192 ; 0x2000 80044c0: 689b ldr r3, [r3, #8] 80044c2: 429a cmp r2, r3 80044c4: da06 bge.n 80044d4 80044c6: 6f3b ldr r3, [r7, #112] ; 0x70 80044c8: 781b ldrb r3, [r3, #0] 80044ca: f063 037f orn r3, r3, #127 ; 0x7f 80044ce: b2da uxtb r2, r3 80044d0: 6f3b ldr r3, [r7, #112] ; 0x70 80044d2: 701a strb r2, [r3, #0] // Number of steps for each axis block->steps_x = labs(target[X_AXIS]-position[X_AXIS]); 80044d4: 6c7a ldr r2, [r7, #68] ; 0x44 80044d6: f240 639c movw r3, #1692 ; 0x69c 80044da: f2c2 0300 movt r3, #8192 ; 0x2000 80044de: 681b ldr r3, [r3, #0] 80044e0: 1ad3 subs r3, r2, r3 80044e2: 2b00 cmp r3, #0 80044e4: bfb8 it lt 80044e6: 425b neglt r3, r3 80044e8: 461a mov r2, r3 80044ea: 6f3b ldr r3, [r7, #112] ; 0x70 80044ec: 605a str r2, [r3, #4] block->steps_y = labs(target[Y_AXIS]-position[Y_AXIS]); 80044ee: 6cba ldr r2, [r7, #72] ; 0x48 80044f0: f240 639c movw r3, #1692 ; 0x69c 80044f4: f2c2 0300 movt r3, #8192 ; 0x2000 80044f8: 685b ldr r3, [r3, #4] 80044fa: 1ad3 subs r3, r2, r3 80044fc: 2b00 cmp r3, #0 80044fe: bfb8 it lt 8004500: 425b neglt r3, r3 8004502: 461a mov r2, r3 8004504: 6f3b ldr r3, [r7, #112] ; 0x70 8004506: 609a str r2, [r3, #8] block->steps_z = labs(target[Z_AXIS]-position[Z_AXIS]); 8004508: 6cfa ldr r2, [r7, #76] ; 0x4c 800450a: f240 639c movw r3, #1692 ; 0x69c 800450e: f2c2 0300 movt r3, #8192 ; 0x2000 8004512: 689b ldr r3, [r3, #8] 8004514: 1ad3 subs r3, r2, r3 8004516: 2b00 cmp r3, #0 8004518: bfb8 it lt 800451a: 425b neglt r3, r3 800451c: 461a mov r2, r3 800451e: 6f3b ldr r3, [r7, #112] ; 0x70 8004520: 60da str r2, [r3, #12] block->step_event_count = max(block->steps_x, max(block->steps_y, block->steps_z)); 8004522: 6f3b ldr r3, [r7, #112] ; 0x70 8004524: 68da ldr r2, [r3, #12] 8004526: 6f3b ldr r3, [r7, #112] ; 0x70 8004528: 689b ldr r3, [r3, #8] 800452a: 429a cmp r2, r3 800452c: bf38 it cc 800452e: 461a movcc r2, r3 8004530: 6f3b ldr r3, [r7, #112] ; 0x70 8004532: 685b ldr r3, [r3, #4] 8004534: 429a cmp r2, r3 8004536: bf28 it cs 8004538: 4613 movcs r3, r2 800453a: 461a mov r2, r3 800453c: 6f3b ldr r3, [r7, #112] ; 0x70 800453e: 611a str r2, [r3, #16] // Bail if this is a zero-length block if (block->step_event_count == 0) { return; }; 8004540: 6f3b ldr r3, [r7, #112] ; 0x70 8004542: 691b ldr r3, [r3, #16] 8004544: 2b00 cmp r3, #0 8004546: f000 82e6 beq.w 8004b16 // Compute path vector in terms of absolute step target and current positions double delta_mm[3]; delta_mm[X_AXIS] = (target[X_AXIS]-position[X_AXIS])/settings.steps_per_mm[X_AXIS]; 800454a: 6c7a ldr r2, [r7, #68] ; 0x44 800454c: f240 639c movw r3, #1692 ; 0x69c 8004550: f2c2 0300 movt r3, #8192 ; 0x2000 8004554: 681b ldr r3, [r3, #0] 8004556: 1ad3 subs r3, r2, r3 8004558: 4618 mov r0, r3 800455a: f004 fadb bl 8008b14 <__aeabi_i2d> 800455e: f240 63d8 movw r3, #1752 ; 0x6d8 8004562: f2c2 0300 movt r3, #8192 ; 0x2000 8004566: e9d3 2300 ldrd r2, r3, [r3] 800456a: f004 fc63 bl 8008e34 <__aeabi_ddiv> 800456e: 4602 mov r2, r0 8004570: 460b mov r3, r1 8004572: e9c7 230a strd r2, r3, [r7, #40] ; 0x28 delta_mm[Y_AXIS] = (target[Y_AXIS]-position[Y_AXIS])/settings.steps_per_mm[Y_AXIS]; 8004576: 6cba ldr r2, [r7, #72] ; 0x48 8004578: f240 639c movw r3, #1692 ; 0x69c 800457c: f2c2 0300 movt r3, #8192 ; 0x2000 8004580: 685b ldr r3, [r3, #4] 8004582: 1ad3 subs r3, r2, r3 8004584: 4618 mov r0, r3 8004586: f004 fac5 bl 8008b14 <__aeabi_i2d> 800458a: f240 63d8 movw r3, #1752 ; 0x6d8 800458e: f2c2 0300 movt r3, #8192 ; 0x2000 8004592: e9d3 2302 ldrd r2, r3, [r3, #8] 8004596: f004 fc4d bl 8008e34 <__aeabi_ddiv> 800459a: 4602 mov r2, r0 800459c: 460b mov r3, r1 800459e: e9c7 230c strd r2, r3, [r7, #48] ; 0x30 delta_mm[Z_AXIS] = (target[Z_AXIS]-position[Z_AXIS])/settings.steps_per_mm[Z_AXIS]; 80045a2: 6cfa ldr r2, [r7, #76] ; 0x4c 80045a4: f240 639c movw r3, #1692 ; 0x69c 80045a8: f2c2 0300 movt r3, #8192 ; 0x2000 80045ac: 689b ldr r3, [r3, #8] 80045ae: 1ad3 subs r3, r2, r3 80045b0: 4618 mov r0, r3 80045b2: f004 faaf bl 8008b14 <__aeabi_i2d> 80045b6: f240 63d8 movw r3, #1752 ; 0x6d8 80045ba: f2c2 0300 movt r3, #8192 ; 0x2000 80045be: e9d3 2304 ldrd r2, r3, [r3, #16] 80045c2: f004 fc37 bl 8008e34 <__aeabi_ddiv> 80045c6: 4602 mov r2, r0 80045c8: 460b mov r3, r1 80045ca: e9c7 230e strd r2, r3, [r7, #56] ; 0x38 block->millimeters = sqrt(pow(delta_mm[X_AXIS],2) + pow(delta_mm[Y_AXIS],2) + 80045ce: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28 80045d2: 4610 mov r0, r2 80045d4: 4619 mov r1, r3 80045d6: f004 fb03 bl 8008be0 <__aeabi_dmul> 80045da: 4602 mov r2, r0 80045dc: 460b mov r3, r1 80045de: 4692 mov sl, r2 80045e0: 469b mov fp, r3 80045e2: e9d7 230c ldrd r2, r3, [r7, #48] ; 0x30 80045e6: 4610 mov r0, r2 80045e8: 4619 mov r1, r3 80045ea: f004 faf9 bl 8008be0 <__aeabi_dmul> 80045ee: 4602 mov r2, r0 80045f0: 460b mov r3, r1 80045f2: 4650 mov r0, sl 80045f4: 4659 mov r1, fp 80045f6: f004 f941 bl 800887c <__adddf3> 80045fa: 4602 mov r2, r0 80045fc: 460b mov r3, r1 80045fe: 4692 mov sl, r2 8004600: 469b mov fp, r3 pow(delta_mm[Z_AXIS],2)); 8004602: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38 8004606: 4610 mov r0, r2 8004608: 4619 mov r1, r3 800460a: f004 fae9 bl 8008be0 <__aeabi_dmul> 800460e: 4602 mov r2, r0 8004610: 460b mov r3, r1 // Compute path vector in terms of absolute step target and current positions double delta_mm[3]; delta_mm[X_AXIS] = (target[X_AXIS]-position[X_AXIS])/settings.steps_per_mm[X_AXIS]; delta_mm[Y_AXIS] = (target[Y_AXIS]-position[Y_AXIS])/settings.steps_per_mm[Y_AXIS]; delta_mm[Z_AXIS] = (target[Z_AXIS]-position[Z_AXIS])/settings.steps_per_mm[Z_AXIS]; block->millimeters = sqrt(pow(delta_mm[X_AXIS],2) + pow(delta_mm[Y_AXIS],2) + 8004612: 4650 mov r0, sl 8004614: 4659 mov r1, fp 8004616: f004 f931 bl 800887c <__adddf3> 800461a: 4602 mov r2, r0 800461c: 460b mov r3, r1 800461e: 4610 mov r0, r2 8004620: 4619 mov r1, r3 8004622: f001 ed34 blx 800608c 8004626: 4602 mov r2, r0 8004628: 460b mov r3, r1 800462a: 6f39 ldr r1, [r7, #112] ; 0x70 800462c: e9c1 230c strd r2, r3, [r1, #48] ; 0x30 pow(delta_mm[Z_AXIS],2)); double inverse_millimeters = 1.0/block->millimeters; // Inverse millimeters to remove multiple divides 8004630: 6f3b ldr r3, [r7, #112] ; 0x70 8004632: e9d3 230c ldrd r2, r3, [r3, #48] ; 0x30 8004636: f20f 41f0 addw r1, pc, #1264 ; 0x4f0 800463a: e9d1 0100 ldrd r0, r1, [r1] 800463e: f004 fbf9 bl 8008e34 <__aeabi_ddiv> 8004642: 4602 mov r2, r0 8004644: 460b mov r3, r1 8004646: e9c7 231a strd r2, r3, [r7, #104] ; 0x68 // Calculate speed in mm/minute for each axis. No divide by zero due to previous checks. // NOTE: Minimum stepper speed is limited by MINIMUM_STEPS_PER_MINUTE in stepper.c double inverse_minute; if (!invert_feed_rate) { 800464a: f897 30c0 ldrb.w r3, [r7, #192] ; 0xc0 800464e: 2b00 cmp r3, #0 8004650: d10a bne.n 8004668 inverse_minute = feed_rate * inverse_millimeters; 8004652: e9d7 012e ldrd r0, r1, [r7, #184] ; 0xb8 8004656: e9d7 231a ldrd r2, r3, [r7, #104] ; 0x68 800465a: f004 fac1 bl 8008be0 <__aeabi_dmul> 800465e: 4602 mov r2, r0 8004660: 460b mov r3, r1 8004662: e9c7 2320 strd r2, r3, [r7, #128] ; 0x80 8004666: e00b b.n 8004680 } else { inverse_minute = 1.0 / feed_rate; 8004668: f20f 41bc addw r1, pc, #1212 ; 0x4bc 800466c: e9d1 0100 ldrd r0, r1, [r1] 8004670: e9d7 232e ldrd r2, r3, [r7, #184] ; 0xb8 8004674: f004 fbde bl 8008e34 <__aeabi_ddiv> 8004678: 4602 mov r2, r0 800467a: 460b mov r3, r1 800467c: e9c7 2320 strd r2, r3, [r7, #128] ; 0x80 } block->nominal_speed = block->millimeters * inverse_minute; // (mm/min) Always > 0 8004680: 6f3b ldr r3, [r7, #112] ; 0x70 8004682: e9d3 230c ldrd r2, r3, [r3, #48] ; 0x30 8004686: 4610 mov r0, r2 8004688: 4619 mov r1, r3 800468a: e9d7 2320 ldrd r2, r3, [r7, #128] ; 0x80 800468e: f004 faa7 bl 8008be0 <__aeabi_dmul> 8004692: 4602 mov r2, r0 8004694: 460b mov r3, r1 8004696: 6f39 ldr r1, [r7, #112] ; 0x70 8004698: e9c1 2306 strd r2, r3, [r1, #24] block->nominal_rate = ceil(block->step_event_count * inverse_minute); // (step/min) Always > 0 800469c: 6f3b ldr r3, [r7, #112] ; 0x70 800469e: 691b ldr r3, [r3, #16] 80046a0: 4618 mov r0, r3 80046a2: f004 fa37 bl 8008b14 <__aeabi_i2d> 80046a6: 4602 mov r2, r0 80046a8: 460b mov r3, r1 80046aa: 4610 mov r0, r2 80046ac: 4619 mov r1, r3 80046ae: e9d7 2320 ldrd r2, r3, [r7, #128] ; 0x80 80046b2: f004 fa95 bl 8008be0 <__aeabi_dmul> 80046b6: 4602 mov r2, r0 80046b8: 460b mov r3, r1 80046ba: 4610 mov r0, r2 80046bc: 4619 mov r1, r3 80046be: f001 e858 blx 8005770 80046c2: 4602 mov r2, r0 80046c4: 460b mov r3, r1 80046c6: 4610 mov r0, r2 80046c8: 4619 mov r1, r3 80046ca: f004 fd4b bl 8009164 <__aeabi_d2uiz> 80046ce: 4602 mov r2, r0 80046d0: 6f3b ldr r3, [r7, #112] ; 0x70 80046d2: 651a str r2, [r3, #80] ; 0x50 // is equal to the travel/step in the particular axis. For a 45 degree line the steppers of both // axes might step for every step event. Travel per step event is then sqrt(travel_x^2+travel_y^2). // To generate trapezoids with contant acceleration between blocks the rate_delta must be computed // specifically for each line to compensate for this phenomenon: // Convert universal acceleration for direction-dependent stepper rate change parameter block->rate_delta = ceil( block->step_event_count*inverse_millimeters * 80046d4: 6f3b ldr r3, [r7, #112] ; 0x70 80046d6: 691b ldr r3, [r3, #16] 80046d8: 4618 mov r0, r3 80046da: f004 fa1b bl 8008b14 <__aeabi_i2d> 80046de: 4602 mov r2, r0 80046e0: 460b mov r3, r1 80046e2: 4610 mov r0, r2 80046e4: 4619 mov r1, r3 80046e6: e9d7 231a ldrd r2, r3, [r7, #104] ; 0x68 80046ea: f004 fa79 bl 8008be0 <__aeabi_dmul> 80046ee: 4602 mov r2, r0 80046f0: 460b mov r3, r1 80046f2: 4610 mov r0, r2 80046f4: 4619 mov r1, r3 settings.acceleration / (60 * ACCELERATION_TICKS_PER_SECOND )); // (step/min/acceleration_tick) 80046f6: f240 63d8 movw r3, #1752 ; 0x6d8 80046fa: f2c2 0300 movt r3, #8192 ; 0x2000 80046fe: e9d3 2310 ldrd r2, r3, [r3, #64] ; 0x40 // is equal to the travel/step in the particular axis. For a 45 degree line the steppers of both // axes might step for every step event. Travel per step event is then sqrt(travel_x^2+travel_y^2). // To generate trapezoids with contant acceleration between blocks the rate_delta must be computed // specifically for each line to compensate for this phenomenon: // Convert universal acceleration for direction-dependent stepper rate change parameter block->rate_delta = ceil( block->step_event_count*inverse_millimeters * 8004702: f004 fa6d bl 8008be0 <__aeabi_dmul> 8004706: 4602 mov r2, r0 8004708: 460b mov r3, r1 800470a: 4610 mov r0, r2 800470c: 4619 mov r1, r3 800470e: f20f 4320 addw r3, pc, #1056 ; 0x420 8004712: e9d3 2300 ldrd r2, r3, [r3] 8004716: f004 fb8d bl 8008e34 <__aeabi_ddiv> 800471a: 4602 mov r2, r0 800471c: 460b mov r3, r1 800471e: 4610 mov r0, r2 8004720: 4619 mov r1, r3 8004722: f001 e826 blx 8005770 8004726: 4602 mov r2, r0 8004728: 460b mov r3, r1 800472a: 4610 mov r0, r2 800472c: 4619 mov r1, r3 800472e: f004 fcf1 bl 8009114 <__aeabi_d2iz> 8004732: 4602 mov r2, r0 8004734: 6f3b ldr r3, [r7, #112] ; 0x70 8004736: 645a str r2, [r3, #68] ; 0x44 settings.acceleration / (60 * ACCELERATION_TICKS_PER_SECOND )); // (step/min/acceleration_tick) // Compute path unit vector double unit_vec[3]; unit_vec[X_AXIS] = delta_mm[X_AXIS]*inverse_millimeters; 8004738: e9d7 230a ldrd r2, r3, [r7, #40] ; 0x28 800473c: 4610 mov r0, r2 800473e: 4619 mov r1, r3 8004740: e9d7 231a ldrd r2, r3, [r7, #104] ; 0x68 8004744: f004 fa4c bl 8008be0 <__aeabi_dmul> 8004748: 4602 mov r2, r0 800474a: 460b mov r3, r1 800474c: e9c7 2304 strd r2, r3, [r7, #16] unit_vec[Y_AXIS] = delta_mm[Y_AXIS]*inverse_millimeters; 8004750: e9d7 230c ldrd r2, r3, [r7, #48] ; 0x30 8004754: 4610 mov r0, r2 8004756: 4619 mov r1, r3 8004758: e9d7 231a ldrd r2, r3, [r7, #104] ; 0x68 800475c: f004 fa40 bl 8008be0 <__aeabi_dmul> 8004760: 4602 mov r2, r0 8004762: 460b mov r3, r1 8004764: e9c7 2306 strd r2, r3, [r7, #24] unit_vec[Z_AXIS] = delta_mm[Z_AXIS]*inverse_millimeters; 8004768: e9d7 230e ldrd r2, r3, [r7, #56] ; 0x38 800476c: 4610 mov r0, r2 800476e: 4619 mov r1, r3 8004770: e9d7 231a ldrd r2, r3, [r7, #104] ; 0x68 8004774: f004 fa34 bl 8008be0 <__aeabi_dmul> 8004778: 4602 mov r2, r0 800477a: 460b mov r3, r1 800477c: e9c7 2308 strd r2, r3, [r7, #32] // path of centripetal acceleration. Solve for max velocity based on max acceleration about the // radius of the circle, defined indirectly by junction deviation. This may be also viewed as // path width or max_jerk in the previous grbl version. This approach does not actually deviate // from path, but used as a robust way to compute cornering speeds, as it takes into account the // nonlinearities of both the junction angle and junction velocity. double vmax_junction = MINIMUM_PLANNER_SPEED; // Set default max junction speed 8004780: a3ed add r3, pc, #948 ; (adr r3, 8004b38 ) 8004782: e9d3 2300 ldrd r2, r3, [r3] 8004786: e9c7 231e strd r2, r3, [r7, #120] ; 0x78 // Skip first block or when previous_nominal_speed is used as a flag for homing and offset cycles. if ((block_buffer_head != block_buffer_tail) && (previous_nominal_speed > 0.0)) { 800478a: f240 6398 movw r3, #1688 ; 0x698 800478e: f2c2 0300 movt r3, #8192 ; 0x2000 8004792: 781b ldrb r3, [r3, #0] 8004794: b2da uxtb r2, r3 8004796: f240 6399 movw r3, #1689 ; 0x699 800479a: f2c2 0300 movt r3, #8192 ; 0x2000 800479e: 781b ldrb r3, [r3, #0] 80047a0: b2db uxtb r3, r3 80047a2: 429a cmp r2, r3 80047a4: f000 812e beq.w 8004a04 80047a8: f240 63c0 movw r3, #1728 ; 0x6c0 80047ac: f2c2 0300 movt r3, #8192 ; 0x2000 80047b0: e9d3 2300 ldrd r2, r3, [r3] 80047b4: f04f 0101 mov.w r1, #1 80047b8: 460e mov r6, r1 80047ba: 4610 mov r0, r2 80047bc: 4619 mov r1, r3 80047be: a3de add r3, pc, #888 ; (adr r3, 8004b38 ) 80047c0: e9d3 2300 ldrd r2, r3, [r3] 80047c4: f004 fc9c bl 8009100 <__aeabi_dcmpgt> 80047c8: 4603 mov r3, r0 80047ca: 2b00 cmp r3, #0 80047cc: d102 bne.n 80047d4 80047ce: f04f 0300 mov.w r3, #0 80047d2: 461e mov r6, r3 80047d4: b2f3 uxtb r3, r6 80047d6: 2b00 cmp r3, #0 80047d8: f000 8114 beq.w 8004a04 // Compute cosine of angle between previous and current path. (prev_unit_vec is negative) // NOTE: Max junction velocity is computed without sin() or acos() by trig half angle identity. double cos_theta = - previous_unit_vec[X_AXIS] * unit_vec[X_AXIS] 80047dc: f240 63a8 movw r3, #1704 ; 0x6a8 80047e0: f2c2 0300 movt r3, #8192 ; 0x2000 80047e4: e9d3 2300 ldrd r2, r3, [r3] 80047e8: 4690 mov r8, r2 80047ea: f083 4900 eor.w r9, r3, #2147483648 ; 0x80000000 80047ee: e9d7 2304 ldrd r2, r3, [r7, #16] 80047f2: 4640 mov r0, r8 80047f4: 4649 mov r1, r9 80047f6: f004 f9f3 bl 8008be0 <__aeabi_dmul> 80047fa: 4602 mov r2, r0 80047fc: 460b mov r3, r1 80047fe: 4690 mov r8, r2 8004800: 4699 mov r9, r3 - previous_unit_vec[Y_AXIS] * unit_vec[Y_AXIS] 8004802: f240 63a8 movw r3, #1704 ; 0x6a8 8004806: f2c2 0300 movt r3, #8192 ; 0x2000 800480a: e9d3 0102 ldrd r0, r1, [r3, #8] 800480e: e9d7 2306 ldrd r2, r3, [r7, #24] 8004812: f004 f9e5 bl 8008be0 <__aeabi_dmul> 8004816: 4602 mov r2, r0 8004818: 460b mov r3, r1 800481a: 4640 mov r0, r8 800481c: 4649 mov r1, r9 800481e: f004 f82b bl 8008878 <__aeabi_dsub> 8004822: 4602 mov r2, r0 8004824: 460b mov r3, r1 8004826: 4690 mov r8, r2 8004828: 4699 mov r9, r3 - previous_unit_vec[Z_AXIS] * unit_vec[Z_AXIS] ; 800482a: f240 63a8 movw r3, #1704 ; 0x6a8 800482e: f2c2 0300 movt r3, #8192 ; 0x2000 8004832: e9d3 0104 ldrd r0, r1, [r3, #16] 8004836: e9d7 2308 ldrd r2, r3, [r7, #32] 800483a: f004 f9d1 bl 8008be0 <__aeabi_dmul> 800483e: 4602 mov r2, r0 8004840: 460b mov r3, r1 // Skip first block or when previous_nominal_speed is used as a flag for homing and offset cycles. if ((block_buffer_head != block_buffer_tail) && (previous_nominal_speed > 0.0)) { // Compute cosine of angle between previous and current path. (prev_unit_vec is negative) // NOTE: Max junction velocity is computed without sin() or acos() by trig half angle identity. double cos_theta = - previous_unit_vec[X_AXIS] * unit_vec[X_AXIS] 8004842: 4640 mov r0, r8 8004844: 4649 mov r1, r9 8004846: f004 f817 bl 8008878 <__aeabi_dsub> 800484a: 4602 mov r2, r0 800484c: 460b mov r3, r1 800484e: e9c7 2318 strd r2, r3, [r7, #96] ; 0x60 - previous_unit_vec[Y_AXIS] * unit_vec[Y_AXIS] - previous_unit_vec[Z_AXIS] * unit_vec[Z_AXIS] ; // Skip and use default max junction speed for 0 degree acute junction. if (cos_theta < 0.95) { 8004852: f04f 0301 mov.w r3, #1 8004856: 461e mov r6, r3 8004858: e9d7 0118 ldrd r0, r1, [r7, #96] ; 0x60 800485c: a3b8 add r3, pc, #736 ; (adr r3, 8004b40 ) 800485e: e9d3 2300 ldrd r2, r3, [r3] 8004862: f004 fc2f bl 80090c4 <__aeabi_dcmplt> 8004866: 4603 mov r3, r0 8004868: 2b00 cmp r3, #0 800486a: d102 bne.n 8004872 800486c: f04f 0300 mov.w r3, #0 8004870: 461e mov r6, r3 8004872: b2f3 uxtb r3, r6 8004874: 2b00 cmp r3, #0 8004876: f000 80c5 beq.w 8004a04 vmax_junction = min(previous_nominal_speed,block->nominal_speed); 800487a: 6f3b ldr r3, [r7, #112] ; 0x70 800487c: e9d3 0106 ldrd r0, r1, [r3, #24] 8004880: f240 63c0 movw r3, #1728 ; 0x6c0 8004884: f2c2 0300 movt r3, #8192 ; 0x2000 8004888: e9d3 2300 ldrd r2, r3, [r3] 800488c: f04f 0601 mov.w r6, #1 8004890: f004 fc36 bl 8009100 <__aeabi_dcmpgt> 8004894: 4603 mov r3, r0 8004896: 2b00 cmp r3, #0 8004898: d102 bne.n 80048a0 800489a: f04f 0300 mov.w r3, #0 800489e: 461e mov r6, r3 80048a0: b2f3 uxtb r3, r6 80048a2: 2b00 cmp r3, #0 80048a4: d006 beq.n 80048b4 80048a6: f240 63c0 movw r3, #1728 ; 0x6c0 80048aa: f2c2 0300 movt r3, #8192 ; 0x2000 80048ae: e9d3 2300 ldrd r2, r3, [r3] 80048b2: e002 b.n 80048ba 80048b4: 6f3b ldr r3, [r7, #112] ; 0x70 80048b6: e9d3 2306 ldrd r2, r3, [r3, #24] 80048ba: e9c7 231e strd r2, r3, [r7, #120] ; 0x78 // Skip and avoid divide by zero for straight junctions at 180 degrees. Limit to min() of nominal speeds. if (cos_theta > -0.95) { 80048be: f04f 0301 mov.w r3, #1 80048c2: 461e mov r6, r3 80048c4: e9d7 0118 ldrd r0, r1, [r7, #96] ; 0x60 80048c8: a39f add r3, pc, #636 ; (adr r3, 8004b48 ) 80048ca: e9d3 2300 ldrd r2, r3, [r3] 80048ce: f004 fc17 bl 8009100 <__aeabi_dcmpgt> 80048d2: 4603 mov r3, r0 80048d4: 2b00 cmp r3, #0 80048d6: d102 bne.n 80048de 80048d8: f04f 0300 mov.w r3, #0 80048dc: 461e mov r6, r3 80048de: b2f3 uxtb r3, r6 80048e0: 2b00 cmp r3, #0 80048e2: f000 808f beq.w 8004a04 // Compute maximum junction velocity based on maximum acceleration and junction deviation double sin_theta_d2 = sqrt(0.5*(1.0-cos_theta)); // Trig half angle identity. Always positive. 80048e6: a190 add r1, pc, #576 ; (adr r1, 8004b28 ) 80048e8: e9d1 0100 ldrd r0, r1, [r1] 80048ec: e9d7 2318 ldrd r2, r3, [r7, #96] ; 0x60 80048f0: f003 ffc2 bl 8008878 <__aeabi_dsub> 80048f4: 4602 mov r2, r0 80048f6: 460b mov r3, r1 80048f8: 4610 mov r0, r2 80048fa: 4619 mov r1, r3 80048fc: a394 add r3, pc, #592 ; (adr r3, 8004b50 ) 80048fe: e9d3 2300 ldrd r2, r3, [r3] 8004902: f004 f96d bl 8008be0 <__aeabi_dmul> 8004906: 4602 mov r2, r0 8004908: 460b mov r3, r1 800490a: 4610 mov r0, r2 800490c: 4619 mov r1, r3 800490e: f001 ebbe blx 800608c 8004912: 4602 mov r2, r0 8004914: 460b mov r3, r1 8004916: e9c7 2316 strd r2, r3, [r7, #88] ; 0x58 vmax_junction = min(vmax_junction, 800491a: f240 63d8 movw r3, #1752 ; 0x6d8 800491e: f2c2 0300 movt r3, #8192 ; 0x2000 8004922: e9d3 0110 ldrd r0, r1, [r3, #64] ; 0x40 8004926: f240 63d8 movw r3, #1752 ; 0x6d8 800492a: f2c2 0300 movt r3, #8192 ; 0x2000 800492e: e9d3 2312 ldrd r2, r3, [r3, #72] ; 0x48 8004932: f004 f955 bl 8008be0 <__aeabi_dmul> 8004936: 4602 mov r2, r0 8004938: 460b mov r3, r1 800493a: 4610 mov r0, r2 800493c: 4619 mov r1, r3 800493e: e9d7 2316 ldrd r2, r3, [r7, #88] ; 0x58 8004942: f004 f94d bl 8008be0 <__aeabi_dmul> 8004946: 4602 mov r2, r0 8004948: 460b mov r3, r1 800494a: 4690 mov r8, r2 800494c: 4699 mov r9, r3 800494e: a176 add r1, pc, #472 ; (adr r1, 8004b28 ) 8004950: e9d1 0100 ldrd r0, r1, [r1] 8004954: e9d7 2316 ldrd r2, r3, [r7, #88] ; 0x58 8004958: f003 ff8e bl 8008878 <__aeabi_dsub> 800495c: 4602 mov r2, r0 800495e: 460b mov r3, r1 8004960: 4640 mov r0, r8 8004962: 4649 mov r1, r9 8004964: f004 fa66 bl 8008e34 <__aeabi_ddiv> 8004968: 4602 mov r2, r0 800496a: 460b mov r3, r1 800496c: 4610 mov r0, r2 800496e: 4619 mov r1, r3 8004970: f001 eb8c blx 800608c 8004974: 4602 mov r2, r0 8004976: 460b mov r3, r1 8004978: f04f 0101 mov.w r1, #1 800497c: 460e mov r6, r1 800497e: 4610 mov r0, r2 8004980: 4619 mov r1, r3 8004982: e9d7 231e ldrd r2, r3, [r7, #120] ; 0x78 8004986: f004 fbbb bl 8009100 <__aeabi_dcmpgt> 800498a: 4603 mov r3, r0 800498c: 2b00 cmp r3, #0 800498e: d102 bne.n 8004996 8004990: f04f 0300 mov.w r3, #0 8004994: 461e mov r6, r3 8004996: b2f3 uxtb r3, r6 8004998: 2b00 cmp r3, #0 800499a: d002 beq.n 80049a2 800499c: e9d7 231e ldrd r2, r3, [r7, #120] ; 0x78 80049a0: e02e b.n 8004a00 80049a2: f240 63d8 movw r3, #1752 ; 0x6d8 80049a6: f2c2 0300 movt r3, #8192 ; 0x2000 80049aa: e9d3 0110 ldrd r0, r1, [r3, #64] ; 0x40 80049ae: f240 63d8 movw r3, #1752 ; 0x6d8 80049b2: f2c2 0300 movt r3, #8192 ; 0x2000 80049b6: e9d3 2312 ldrd r2, r3, [r3, #72] ; 0x48 80049ba: f004 f911 bl 8008be0 <__aeabi_dmul> 80049be: 4602 mov r2, r0 80049c0: 460b mov r3, r1 80049c2: 4610 mov r0, r2 80049c4: 4619 mov r1, r3 80049c6: e9d7 2316 ldrd r2, r3, [r7, #88] ; 0x58 80049ca: f004 f909 bl 8008be0 <__aeabi_dmul> 80049ce: 4602 mov r2, r0 80049d0: 460b mov r3, r1 80049d2: 4690 mov r8, r2 80049d4: 4699 mov r9, r3 80049d6: a154 add r1, pc, #336 ; (adr r1, 8004b28 ) 80049d8: e9d1 0100 ldrd r0, r1, [r1] 80049dc: e9d7 2316 ldrd r2, r3, [r7, #88] ; 0x58 80049e0: f003 ff4a bl 8008878 <__aeabi_dsub> 80049e4: 4602 mov r2, r0 80049e6: 460b mov r3, r1 80049e8: 4640 mov r0, r8 80049ea: 4649 mov r1, r9 80049ec: f004 fa22 bl 8008e34 <__aeabi_ddiv> 80049f0: 4602 mov r2, r0 80049f2: 460b mov r3, r1 80049f4: 4610 mov r0, r2 80049f6: 4619 mov r1, r3 80049f8: f001 eb48 blx 800608c 80049fc: 4602 mov r2, r0 80049fe: 460b mov r3, r1 8004a00: e9c7 231e strd r2, r3, [r7, #120] ; 0x78 sqrt(settings.acceleration * settings.junction_deviation * sin_theta_d2/(1.0-sin_theta_d2)) ); } } } block->max_entry_speed = vmax_junction; 8004a04: 6f39 ldr r1, [r7, #112] ; 0x70 8004a06: e9d7 231e ldrd r2, r3, [r7, #120] ; 0x78 8004a0a: e9c1 230a strd r2, r3, [r1, #40] ; 0x28 // Initialize block entry speed. Compute based on deceleration to user-defined MINIMUM_PLANNER_SPEED. double v_allowable = max_allowable_speed(-settings.acceleration,MINIMUM_PLANNER_SPEED,block->millimeters); 8004a0e: f240 63d8 movw r3, #1752 ; 0x6d8 8004a12: f2c2 0300 movt r3, #8192 ; 0x2000 8004a16: e9d3 2310 ldrd r2, r3, [r3, #64] ; 0x40 8004a1a: 4614 mov r4, r2 8004a1c: f083 4500 eor.w r5, r3, #2147483648 ; 0x80000000 8004a20: 6f3b ldr r3, [r7, #112] ; 0x70 8004a22: e9d3 230c ldrd r2, r3, [r3, #48] ; 0x30 8004a26: e9cd 2300 strd r2, r3, [sp] 8004a2a: 4620 mov r0, r4 8004a2c: 4629 mov r1, r5 8004a2e: a342 add r3, pc, #264 ; (adr r3, 8004b38 ) 8004a30: e9d3 2300 ldrd r2, r3, [r3] 8004a34: f7ff f8a8 bl 8003b88 8004a38: 4602 mov r2, r0 8004a3a: 460b mov r3, r1 8004a3c: e9c7 2314 strd r2, r3, [r7, #80] ; 0x50 block->entry_speed = min(vmax_junction, v_allowable); 8004a40: f04f 0301 mov.w r3, #1 8004a44: 461c mov r4, r3 8004a46: e9d7 011e ldrd r0, r1, [r7, #120] ; 0x78 8004a4a: e9d7 2314 ldrd r2, r3, [r7, #80] ; 0x50 8004a4e: f004 fb39 bl 80090c4 <__aeabi_dcmplt> 8004a52: 4603 mov r3, r0 8004a54: 2b00 cmp r3, #0 8004a56: d102 bne.n 8004a5e 8004a58: f04f 0300 mov.w r3, #0 8004a5c: 461c mov r4, r3 8004a5e: b2e3 uxtb r3, r4 8004a60: 2b00 cmp r3, #0 8004a62: d002 beq.n 8004a6a 8004a64: e9d7 231e ldrd r2, r3, [r7, #120] ; 0x78 8004a68: e001 b.n 8004a6e 8004a6a: e9d7 2314 ldrd r2, r3, [r7, #80] ; 0x50 8004a6e: 6f39 ldr r1, [r7, #112] ; 0x70 8004a70: e9c1 2308 strd r2, r3, [r1, #32] // the current block and next block junction speeds are guaranteed to always be at their maximum // junction speeds in deceleration and acceleration, respectively. This is due to how the current // block nominal speed limits both the current and next maximum junction speeds. Hence, in both // the reverse and forward planners, the corresponding block junction speed will always be at the // the maximum junction speed and may always be ignored for any speed reduction checks. if (block->nominal_speed <= v_allowable) { block->nominal_length_flag = true; } 8004a74: 6f3b ldr r3, [r7, #112] ; 0x70 8004a76: e9d3 2306 ldrd r2, r3, [r3, #24] 8004a7a: f04f 0101 mov.w r1, #1 8004a7e: 460c mov r4, r1 8004a80: 4610 mov r0, r2 8004a82: 4619 mov r1, r3 8004a84: e9d7 2314 ldrd r2, r3, [r7, #80] ; 0x50 8004a88: f004 fb26 bl 80090d8 <__aeabi_dcmple> 8004a8c: 4603 mov r3, r0 8004a8e: 2b00 cmp r3, #0 8004a90: d102 bne.n 8004a98 8004a92: f04f 0300 mov.w r3, #0 8004a96: 461c mov r4, r3 8004a98: b2e3 uxtb r3, r4 8004a9a: 2b00 cmp r3, #0 8004a9c: d005 beq.n 8004aaa 8004a9e: 6f3b ldr r3, [r7, #112] ; 0x70 8004aa0: f04f 0201 mov.w r2, #1 8004aa4: f883 2039 strb.w r2, [r3, #57] ; 0x39 8004aa8: e004 b.n 8004ab4 else { block->nominal_length_flag = false; } 8004aaa: 6f3b ldr r3, [r7, #112] ; 0x70 8004aac: f04f 0200 mov.w r2, #0 8004ab0: f883 2039 strb.w r2, [r3, #57] ; 0x39 block->recalculate_flag = true; // Always calculate trapezoid for new block 8004ab4: 6f3b ldr r3, [r7, #112] ; 0x70 8004ab6: f04f 0201 mov.w r2, #1 8004aba: f883 2038 strb.w r2, [r3, #56] ; 0x38 // Update previous path unit_vector and nominal speed memcpy(previous_unit_vec, unit_vec, sizeof(unit_vec)); // previous_unit_vec[] = unit_vec[] 8004abe: f240 63a8 movw r3, #1704 ; 0x6a8 8004ac2: f2c2 0300 movt r3, #8192 ; 0x2000 8004ac6: f107 0210 add.w r2, r7, #16 8004aca: 461c mov r4, r3 8004acc: 4615 mov r5, r2 8004ace: cd0f ldmia r5!, {r0, r1, r2, r3} 8004ad0: c40f stmia r4!, {r0, r1, r2, r3} 8004ad2: e895 0003 ldmia.w r5, {r0, r1} 8004ad6: e884 0003 stmia.w r4, {r0, r1} previous_nominal_speed = block->nominal_speed; 8004ada: 6f3b ldr r3, [r7, #112] ; 0x70 8004adc: e9d3 0106 ldrd r0, r1, [r3, #24] 8004ae0: f240 63c0 movw r3, #1728 ; 0x6c0 8004ae4: f2c2 0300 movt r3, #8192 ; 0x2000 8004ae8: e9c3 0100 strd r0, r1, [r3] // Move buffer head block_buffer_head = next_buffer_head; 8004aec: f240 6398 movw r3, #1688 ; 0x698 8004af0: f2c2 0300 movt r3, #8192 ; 0x2000 8004af4: f897 2077 ldrb.w r2, [r7, #119] ; 0x77 8004af8: 701a strb r2, [r3, #0] // Update position memcpy(position, target, sizeof(target)); // position[] = target[] 8004afa: f240 639c movw r3, #1692 ; 0x69c 8004afe: f2c2 0300 movt r3, #8192 ; 0x2000 8004b02: f107 0244 add.w r2, r7, #68 ; 0x44 8004b06: ca07 ldmia r2, {r0, r1, r2} 8004b08: e883 0007 stmia.w r3, {r0, r1, r2} planner_recalculate(); 8004b0c: f7ff fb98 bl 8004240 st_cycle_start(); 8004b10: f7fd fafa bl 8002108 8004b14: e000 b.n 8004b18 block->steps_y = labs(target[Y_AXIS]-position[Y_AXIS]); block->steps_z = labs(target[Z_AXIS]-position[Z_AXIS]); block->step_event_count = max(block->steps_x, max(block->steps_y, block->steps_z)); // Bail if this is a zero-length block if (block->step_event_count == 0) { return; }; 8004b16: bf00 nop // Update position memcpy(position, target, sizeof(target)); // position[] = target[] planner_recalculate(); st_cycle_start(); } 8004b18: f107 078c add.w r7, r7, #140 ; 0x8c 8004b1c: 46bd mov sp, r7 8004b1e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8004b22: bf00 nop 8004b24: f3af 8000 nop.w 8004b28: 00000000 .word 0x00000000 8004b2c: 3ff00000 .word 0x3ff00000 8004b30: 00000000 .word 0x00000000 8004b34: 40a77000 .word 0x40a77000 ... 8004b40: 66666666 .word 0x66666666 8004b44: 3fee6666 .word 0x3fee6666 8004b48: 66666666 .word 0x66666666 8004b4c: bfee6666 .word 0xbfee6666 8004b50: 00000000 .word 0x00000000 8004b54: 3fe00000 .word 0x3fe00000 08004b58 : // Reset the planner position vector and planner speed void plan_set_current_position(double x, double y, double z) { 8004b58: b580 push {r7, lr} 8004b5a: b084 sub sp, #16 8004b5c: af00 add r7, sp, #0 8004b5e: e9c7 0102 strd r0, r1, [r7, #8] 8004b62: e9c7 2300 strd r2, r3, [r7] position[X_AXIS] = lround(x*settings.steps_per_mm[X_AXIS]); 8004b66: f240 63d8 movw r3, #1752 ; 0x6d8 8004b6a: f2c2 0300 movt r3, #8192 ; 0x2000 8004b6e: e9d3 2300 ldrd r2, r3, [r3] 8004b72: 4610 mov r0, r2 8004b74: 4619 mov r1, r3 8004b76: e9d7 2302 ldrd r2, r3, [r7, #8] 8004b7a: f004 f831 bl 8008be0 <__aeabi_dmul> 8004b7e: 4602 mov r2, r0 8004b80: 460b mov r3, r1 8004b82: 4610 mov r0, r2 8004b84: 4619 mov r1, r3 8004b86: f001 e818 blx 8005bb8 8004b8a: 4602 mov r2, r0 8004b8c: f240 639c movw r3, #1692 ; 0x69c 8004b90: f2c2 0300 movt r3, #8192 ; 0x2000 8004b94: 601a str r2, [r3, #0] position[Y_AXIS] = lround(y*settings.steps_per_mm[Y_AXIS]); 8004b96: f240 63d8 movw r3, #1752 ; 0x6d8 8004b9a: f2c2 0300 movt r3, #8192 ; 0x2000 8004b9e: e9d3 2302 ldrd r2, r3, [r3, #8] 8004ba2: 4610 mov r0, r2 8004ba4: 4619 mov r1, r3 8004ba6: e9d7 2300 ldrd r2, r3, [r7] 8004baa: f004 f819 bl 8008be0 <__aeabi_dmul> 8004bae: 4602 mov r2, r0 8004bb0: 460b mov r3, r1 8004bb2: 4610 mov r0, r2 8004bb4: 4619 mov r1, r3 8004bb6: f001 e800 blx 8005bb8 8004bba: 4602 mov r2, r0 8004bbc: f240 639c movw r3, #1692 ; 0x69c 8004bc0: f2c2 0300 movt r3, #8192 ; 0x2000 8004bc4: 605a str r2, [r3, #4] position[Z_AXIS] = lround(z*settings.steps_per_mm[Z_AXIS]); 8004bc6: f240 63d8 movw r3, #1752 ; 0x6d8 8004bca: f2c2 0300 movt r3, #8192 ; 0x2000 8004bce: e9d3 2304 ldrd r2, r3, [r3, #16] 8004bd2: 4610 mov r0, r2 8004bd4: 4619 mov r1, r3 8004bd6: e9d7 2306 ldrd r2, r3, [r7, #24] 8004bda: f004 f801 bl 8008be0 <__aeabi_dmul> 8004bde: 4602 mov r2, r0 8004be0: 460b mov r3, r1 8004be2: 4610 mov r0, r2 8004be4: 4619 mov r1, r3 8004be6: f000 efe8 blx 8005bb8 8004bea: 4602 mov r2, r0 8004bec: f240 639c movw r3, #1692 ; 0x69c 8004bf0: f2c2 0300 movt r3, #8192 ; 0x2000 8004bf4: 609a str r2, [r3, #8] previous_nominal_speed = 0.0; // Resets planner junction speeds. Assumes start from rest. 8004bf6: f240 63c0 movw r3, #1728 ; 0x6c0 8004bfa: f2c2 0300 movt r3, #8192 ; 0x2000 8004bfe: a116 add r1, pc, #88 ; (adr r1, 8004c58 ) 8004c00: e9d1 0100 ldrd r0, r1, [r1] 8004c04: e9c3 0100 strd r0, r1, [r3] clear_vector_double(previous_unit_vec); 8004c08: f240 63a8 movw r3, #1704 ; 0x6a8 8004c0c: f2c2 0300 movt r3, #8192 ; 0x2000 8004c10: f04f 0200 mov.w r2, #0 8004c14: 601a str r2, [r3, #0] 8004c16: f103 0304 add.w r3, r3, #4 8004c1a: f04f 0200 mov.w r2, #0 8004c1e: 601a str r2, [r3, #0] 8004c20: f103 0304 add.w r3, r3, #4 8004c24: f04f 0200 mov.w r2, #0 8004c28: 601a str r2, [r3, #0] 8004c2a: f103 0304 add.w r3, r3, #4 8004c2e: f04f 0200 mov.w r2, #0 8004c32: 601a str r2, [r3, #0] 8004c34: f103 0304 add.w r3, r3, #4 8004c38: f04f 0200 mov.w r2, #0 8004c3c: 601a str r2, [r3, #0] 8004c3e: f103 0304 add.w r3, r3, #4 8004c42: f04f 0200 mov.w r2, #0 8004c46: 601a str r2, [r3, #0] 8004c48: f103 0304 add.w r3, r3, #4 } 8004c4c: f107 0710 add.w r7, r7, #16 8004c50: 46bd mov sp, r7 8004c52: bd80 pop {r7, pc} 8004c54: f3af 8000 nop.w ... 08004c60 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) { 8004c60: b480 push {r7} 8004c62: b083 sub sp, #12 8004c64: af00 add r7, sp, #0 8004c66: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; 8004c68: f44f 436d mov.w r3, #60672 ; 0xed00 8004c6c: f2ce 0300 movt r3, #57344 ; 0xe000 8004c70: 687a ldr r2, [r7, #4] 8004c72: f042 62be orr.w r2, r2, #99614720 ; 0x5f00000 8004c76: f442 2220 orr.w r2, r2, #655360 ; 0xa0000 8004c7a: 60da str r2, [r3, #12] } 8004c7c: f107 070c add.w r7, r7, #12 8004c80: 46bd mov sp, r7 8004c82: bc80 pop {r7} 8004c84: 4770 bx lr 8004c86: bf00 nop 08004c88 : * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains * the configuration information for the specified NVIC peripheral. * @retval None */ void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) { 8004c88: b480 push {r7} 8004c8a: b085 sub sp, #20 8004c8c: af00 add r7, sp, #0 8004c8e: 6078 str r0, [r7, #4] uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; 8004c90: f04f 0300 mov.w r3, #0 8004c94: 73fb strb r3, [r7, #15] 8004c96: f04f 0300 mov.w r3, #0 8004c9a: 73bb strb r3, [r7, #14] 8004c9c: f04f 030f mov.w r3, #15 8004ca0: 737b strb r3, [r7, #13] /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) 8004ca2: 687b ldr r3, [r7, #4] 8004ca4: 78db ldrb r3, [r3, #3] 8004ca6: 2b00 cmp r3, #0 8004ca8: d045 beq.n 8004d36 { /* Compute the Corresponding IRQ Priority --------------------------------*/ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; 8004caa: f44f 436d mov.w r3, #60672 ; 0xed00 8004cae: f2ce 0300 movt r3, #57344 ; 0xe000 8004cb2: 68db ldr r3, [r3, #12] 8004cb4: ea6f 0303 mvn.w r3, r3 8004cb8: f403 63e0 and.w r3, r3, #1792 ; 0x700 8004cbc: ea4f 2313 mov.w r3, r3, lsr #8 8004cc0: 73fb strb r3, [r7, #15] tmppre = (0x4 - tmppriority); 8004cc2: 7bfb ldrb r3, [r7, #15] 8004cc4: f1c3 0304 rsb r3, r3, #4 8004cc8: 73bb strb r3, [r7, #14] tmpsub = tmpsub >> tmppriority; 8004cca: 7b7a ldrb r2, [r7, #13] 8004ccc: 7bfb ldrb r3, [r7, #15] 8004cce: fa42 f303 asr.w r3, r2, r3 8004cd2: 737b strb r3, [r7, #13] tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; 8004cd4: 687b ldr r3, [r7, #4] 8004cd6: 785b ldrb r3, [r3, #1] 8004cd8: 461a mov r2, r3 8004cda: 7bbb ldrb r3, [r7, #14] 8004cdc: fa02 f303 lsl.w r3, r2, r3 8004ce0: 73fb strb r3, [r7, #15] tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub); 8004ce2: 687b ldr r3, [r7, #4] 8004ce4: 789a ldrb r2, [r3, #2] 8004ce6: 7b7b ldrb r3, [r7, #13] 8004ce8: 4013 ands r3, r2 8004cea: b2da uxtb r2, r3 8004cec: 7bfb ldrb r3, [r7, #15] 8004cee: 4313 orrs r3, r2 8004cf0: 73fb strb r3, [r7, #15] tmppriority = tmppriority << 0x04; 8004cf2: 7bfb ldrb r3, [r7, #15] 8004cf4: ea4f 1303 mov.w r3, r3, lsl #4 8004cf8: 73fb strb r3, [r7, #15] NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; 8004cfa: f44f 4361 mov.w r3, #57600 ; 0xe100 8004cfe: f2ce 0300 movt r3, #57344 ; 0xe000 8004d02: 687a ldr r2, [r7, #4] 8004d04: 7812 ldrb r2, [r2, #0] 8004d06: 189b adds r3, r3, r2 8004d08: 7bfa ldrb r2, [r7, #15] 8004d0a: f883 2300 strb.w r2, [r3, #768] ; 0x300 /* Enable the Selected IRQ Channels --------------------------------------*/ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 8004d0e: f44f 4361 mov.w r3, #57600 ; 0xe100 8004d12: f2ce 0300 movt r3, #57344 ; 0xe000 8004d16: 687a ldr r2, [r7, #4] 8004d18: 7812 ldrb r2, [r2, #0] 8004d1a: ea4f 1252 mov.w r2, r2, lsr #5 8004d1e: b2d2 uxtb r2, r2 (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 8004d20: 6879 ldr r1, [r7, #4] 8004d22: 7809 ldrb r1, [r1, #0] 8004d24: f001 011f and.w r1, r1, #31 8004d28: f04f 0001 mov.w r0, #1 8004d2c: fa00 f101 lsl.w r1, r0, r1 tmppriority = tmppriority << 0x04; NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; /* Enable the Selected IRQ Channels --------------------------------------*/ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 8004d30: f843 1022 str.w r1, [r3, r2, lsl #2] 8004d34: e014 b.n 8004d60 (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); } else { /* Disable the Selected IRQ Channels -------------------------------------*/ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 8004d36: f44f 4361 mov.w r3, #57600 ; 0xe100 8004d3a: f2ce 0300 movt r3, #57344 ; 0xe000 8004d3e: 687a ldr r2, [r7, #4] 8004d40: 7812 ldrb r2, [r2, #0] 8004d42: ea4f 1252 mov.w r2, r2, lsr #5 8004d46: b2d2 uxtb r2, r2 (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 8004d48: 6879 ldr r1, [r7, #4] 8004d4a: 7809 ldrb r1, [r1, #0] 8004d4c: f001 011f and.w r1, r1, #31 8004d50: f04f 0001 mov.w r0, #1 8004d54: fa00 f101 lsl.w r1, r0, r1 (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); } else { /* Disable the Selected IRQ Channels -------------------------------------*/ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 8004d58: f102 0220 add.w r2, r2, #32 8004d5c: f843 1022 str.w r1, [r3, r2, lsl #2] (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); } } 8004d60: f107 0714 add.w r7, r7, #20 8004d64: 46bd mov sp, r7 8004d66: bc80 pop {r7} 8004d68: 4770 bx lr 8004d6a: bf00 nop 08004d6c : UBRR0H = UBRR0_value >> 8; UBRR0L = UBRR0_value; }*/ void serial_init(long baud) { 8004d6c: b580 push {r7, lr} 8004d6e: b08a sub sp, #40 ; 0x28 8004d70: af00 add r7, sp, #0 8004d72: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStructure; USART_InitTypeDef USART_InitStructure; USART_InitStructure.USART_BaudRate = baud; 8004d74: 687b ldr r3, [r7, #4] 8004d76: 613b str r3, [r7, #16] USART_InitStructure.USART_WordLength = USART_WordLength_8b; 8004d78: f04f 0300 mov.w r3, #0 8004d7c: 82bb strh r3, [r7, #20] USART_InitStructure.USART_StopBits = USART_StopBits_1; 8004d7e: f04f 0300 mov.w r3, #0 8004d82: 82fb strh r3, [r7, #22] USART_InitStructure.USART_Parity = USART_Parity_No; 8004d84: f04f 0300 mov.w r3, #0 8004d88: 833b strh r3, [r7, #24] USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; 8004d8a: f04f 0300 mov.w r3, #0 8004d8e: 83bb strh r3, [r7, #28] USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; 8004d90: f04f 030c mov.w r3, #12 8004d94: 837b strh r3, [r7, #26] // GPIO_InitTypeDef GPIO_InitStructure; //configure clock for USART RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); 8004d96: f44f 2080 mov.w r0, #262144 ; 0x40000 8004d9a: f04f 0101 mov.w r1, #1 8004d9e: f7fd fbbb bl 8002518 //configure clock for GPIO RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE); 8004da2: f04f 0008 mov.w r0, #8 8004da6: f04f 0101 mov.w r1, #1 8004daa: f7fd fb89 bl 80024c0 //configure AF GPIO_PinAFConfig(GPIOD,GPIO_PinSource8,GPIO_AF_USART3); 8004dae: f44f 6040 mov.w r0, #3072 ; 0xc00 8004db2: f2c4 0002 movt r0, #16386 ; 0x4002 8004db6: f04f 0108 mov.w r1, #8 8004dba: f04f 0207 mov.w r2, #7 8004dbe: f7fd ff3f bl 8002c40 GPIO_PinAFConfig(GPIOD,GPIO_PinSource9,GPIO_AF_USART3); 8004dc2: f44f 6040 mov.w r0, #3072 ; 0xc00 8004dc6: f2c4 0002 movt r0, #16386 ; 0x4002 8004dca: f04f 0109 mov.w r1, #9 8004dce: f04f 0207 mov.w r2, #7 8004dd2: f7fd ff35 bl 8002c40 //configure ports, &GPIO_InitStructure); GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; 8004dd6: f04f 0300 mov.w r3, #0 8004dda: f887 3026 strb.w r3, [r7, #38] ; 0x26 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; 8004dde: f04f 0301 mov.w r3, #1 8004de2: f887 3027 strb.w r3, [r7, #39] ; 0x27 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; 8004de6: f04f 0302 mov.w r3, #2 8004dea: f887 3024 strb.w r3, [r7, #36] ; 0x24 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8; //TX 8004dee: f44f 7380 mov.w r3, #256 ; 0x100 8004df2: 623b str r3, [r7, #32] GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 8004df4: f04f 0302 mov.w r3, #2 8004df8: f887 3025 strb.w r3, [r7, #37] ; 0x25 GPIO_Init(GPIOD, &GPIO_InitStructure); 8004dfc: f107 0320 add.w r3, r7, #32 8004e00: f44f 6040 mov.w r0, #3072 ; 0xc00 8004e04: f2c4 0002 movt r0, #16386 ; 0x4002 8004e08: 4619 mov r1, r3 8004e0a: f7fd fe6f bl 8002aec GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF; 8004e0e: f04f 0302 mov.w r3, #2 8004e12: f887 3024 strb.w r3, [r7, #36] ; 0x24 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; //RX 8004e16: f44f 7300 mov.w r3, #512 ; 0x200 8004e1a: 623b str r3, [r7, #32] GPIO_Init(GPIOD, &GPIO_InitStructure); 8004e1c: f107 0320 add.w r3, r7, #32 8004e20: f44f 6040 mov.w r0, #3072 ; 0xc00 8004e24: f2c4 0002 movt r0, #16386 ; 0x4002 8004e28: 4619 mov r1, r3 8004e2a: f7fd fe5f bl 8002aec USART_Init(USART3, &USART_InitStructure); 8004e2e: f107 0310 add.w r3, r7, #16 8004e32: f44f 4090 mov.w r0, #18432 ; 0x4800 8004e36: f2c4 0000 movt r0, #16384 ; 0x4000 8004e3a: 4619 mov r1, r3 8004e3c: f7fb fae0 bl 8000400 /* NVIC configuration */ /* Configure the Priority Group to 2 bits */ NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); 8004e40: f44f 60a0 mov.w r0, #1280 ; 0x500 8004e44: f7ff ff0c bl 8004c60 /* Enable the USARTx Interrupt */ NVIC_InitTypeDef NVIC_InitStructure_UART; NVIC_InitStructure_UART.NVIC_IRQChannel = USART3_IRQn; 8004e48: f04f 0327 mov.w r3, #39 ; 0x27 8004e4c: 733b strb r3, [r7, #12] NVIC_InitStructure_UART.NVIC_IRQChannelPreemptionPriority = 0; 8004e4e: f04f 0300 mov.w r3, #0 8004e52: 737b strb r3, [r7, #13] NVIC_InitStructure_UART.NVIC_IRQChannelSubPriority = 0; 8004e54: f04f 0300 mov.w r3, #0 8004e58: 73bb strb r3, [r7, #14] NVIC_InitStructure_UART.NVIC_IRQChannelCmd = ENABLE; 8004e5a: f04f 0301 mov.w r3, #1 8004e5e: 73fb strb r3, [r7, #15] NVIC_Init(&NVIC_InitStructure_UART); 8004e60: f107 030c add.w r3, r7, #12 8004e64: 4618 mov r0, r3 8004e66: f7ff ff0f bl 8004c88 // Enable USART USART_Cmd(USART3, ENABLE); 8004e6a: f44f 4090 mov.w r0, #18432 ; 0x4800 8004e6e: f2c4 0000 movt r0, #16384 ; 0x4000 8004e72: f04f 0101 mov.w r1, #1 8004e76: f7fb fb99 bl 80005ac // enable interrupt on complete reception of a byte UCSR0B |= 1<: void USART3_IRQHandler(void) { 8004e84: b580 push {r7, lr} 8004e86: b082 sub sp, #8 8004e88: af00 add r7, sp, #0 //USART_ITConfig(USART3, USART_IT_RXNE, DISABLE); //USART_ITConfig(USART3, USART_IT_TXE, DISABLE); if(USART_GetFlagStatus(USART3, USART_FLAG_RXNE) == SET) 8004e8a: f44f 4090 mov.w r0, #18432 ; 0x4800 8004e8e: f2c4 0000 movt r0, #16384 ; 0x4000 8004e92: f04f 0120 mov.w r1, #32 8004e96: f7fb fc21 bl 80006dc 8004e9a: 4603 mov r3, r0 8004e9c: 2b01 cmp r3, #1 8004e9e: d12f bne.n 8004f00 { uint8_t data = USART_ReceiveData(USART3); 8004ea0: f44f 4090 mov.w r0, #18432 ; 0x4800 8004ea4: f2c4 0000 movt r0, #16384 ; 0x4000 8004ea8: f7fb fbb4 bl 8000614 8004eac: 4603 mov r3, r0 8004eae: 717b strb r3, [r7, #5] uint8_t next_head = rx_buffer_head + 1; 8004eb0: f240 63c8 movw r3, #1736 ; 0x6c8 8004eb4: f2c2 0300 movt r3, #8192 ; 0x2000 8004eb8: 781b ldrb r3, [r3, #0] 8004eba: f103 0301 add.w r3, r3, #1 8004ebe: 71fb strb r3, [r7, #7] if (next_head == RX_BUFFER_SIZE) { next_head = 0; } 8004ec0: 79fb ldrb r3, [r7, #7] 8004ec2: 2b40 cmp r3, #64 ; 0x40 8004ec4: d102 bne.n 8004ecc 8004ec6: f04f 0300 mov.w r3, #0 8004eca: 71fb strb r3, [r7, #7] // Write data to buffer unless it is full. if (next_head != rx_buffer_tail) { 8004ecc: f240 63c9 movw r3, #1737 ; 0x6c9 8004ed0: f2c2 0300 movt r3, #8192 ; 0x2000 8004ed4: 781b ldrb r3, [r3, #0] 8004ed6: 79fa ldrb r2, [r7, #7] 8004ed8: 429a cmp r2, r3 8004eda: d011 beq.n 8004f00 rx_buffer[rx_buffer_head] = data; 8004edc: f240 63c8 movw r3, #1736 ; 0x6c8 8004ee0: f2c2 0300 movt r3, #8192 ; 0x2000 8004ee4: 781b ldrb r3, [r3, #0] 8004ee6: 461a mov r2, r3 8004ee8: f240 7328 movw r3, #1832 ; 0x728 8004eec: f2c2 0300 movt r3, #8192 ; 0x2000 8004ef0: 7979 ldrb r1, [r7, #5] 8004ef2: 5499 strb r1, [r3, r2] rx_buffer_head = next_head; 8004ef4: f240 63c8 movw r3, #1736 ; 0x6c8 8004ef8: f2c2 0300 movt r3, #8192 ; 0x2000 8004efc: 79fa ldrb r2, [r7, #7] 8004efe: 701a strb r2, [r3, #0] } } if(USART_GetFlagStatus(USART3, USART_FLAG_TXE) == SET) 8004f00: f44f 4090 mov.w r0, #18432 ; 0x4800 8004f04: f2c4 0000 movt r0, #16384 ; 0x4000 8004f08: f04f 0180 mov.w r1, #128 ; 0x80 8004f0c: f7fb fbe6 bl 80006dc 8004f10: 4603 mov r3, r0 8004f12: 2b01 cmp r3, #1 8004f14: d134 bne.n 8004f80 { // Temporary tx_buffer_tail (to optimize for volatile) uint8_t tail = tx_buffer_tail; 8004f16: f240 63cb movw r3, #1739 ; 0x6cb 8004f1a: f2c2 0300 movt r3, #8192 ; 0x2000 8004f1e: 781b ldrb r3, [r3, #0] 8004f20: 71bb strb r3, [r7, #6] // Send a byte from the buffer USART_SendData(USART3, tx_buffer[tail]); 8004f22: 79ba ldrb r2, [r7, #6] 8004f24: f240 7368 movw r3, #1896 ; 0x768 8004f28: f2c2 0300 movt r3, #8192 ; 0x2000 8004f2c: 5c9b ldrb r3, [r3, r2] 8004f2e: f44f 4090 mov.w r0, #18432 ; 0x4800 8004f32: f2c4 0000 movt r0, #16384 ; 0x4000 8004f36: 4619 mov r1, r3 8004f38: f7fb fb58 bl 80005ec // UDR0 = tx_buffer[tail]; // Update tail position tail ++; 8004f3c: 79bb ldrb r3, [r7, #6] 8004f3e: f103 0301 add.w r3, r3, #1 8004f42: 71bb strb r3, [r7, #6] if (tail == TX_BUFFER_SIZE) { tail = 0; } 8004f44: 79bb ldrb r3, [r7, #6] 8004f46: 2b10 cmp r3, #16 8004f48: d102 bne.n 8004f50 8004f4a: f04f 0300 mov.w r3, #0 8004f4e: 71bb strb r3, [r7, #6] // Turn off Data Register Empty Interrupt to stop tx-streaming if this concludes the transfer if (tail == tx_buffer_head) { USART_ITConfig(USART3, USART_IT_TXE, DISABLE); } 8004f50: f240 63ca movw r3, #1738 ; 0x6ca 8004f54: f2c2 0300 movt r3, #8192 ; 0x2000 8004f58: 781b ldrb r3, [r3, #0] 8004f5a: 79ba ldrb r2, [r7, #6] 8004f5c: 429a cmp r2, r3 8004f5e: d109 bne.n 8004f74 8004f60: f44f 4090 mov.w r0, #18432 ; 0x4800 8004f64: f2c4 0000 movt r0, #16384 ; 0x4000 8004f68: f240 7127 movw r1, #1831 ; 0x727 8004f6c: f04f 0200 mov.w r2, #0 8004f70: f7fb fb62 bl 8000638 tx_buffer_tail = tail; 8004f74: f240 63cb movw r3, #1739 ; 0x6cb 8004f78: f2c2 0300 movt r3, #8192 ; 0x2000 8004f7c: 79ba ldrb r2, [r7, #6] 8004f7e: 701a strb r2, [r3, #0] } //USART_ITConfig(USART3, USART_IT_RXNE, ENABLE); //USART_ITConfig(USART3, USART_IT_TXE, ENABLE); } 8004f80: f107 0708 add.w r7, r7, #8 8004f84: 46bd mov sp, r7 8004f86: bd80 pop {r7, pc} 08004f88 : void serial_write(uint8_t data) { 8004f88: b580 push {r7, lr} 8004f8a: b084 sub sp, #16 8004f8c: af00 add r7, sp, #0 8004f8e: 4603 mov r3, r0 8004f90: 71fb strb r3, [r7, #7] // Calculate next head uint8_t next_head = tx_buffer_head + 1; 8004f92: f240 63ca movw r3, #1738 ; 0x6ca 8004f96: f2c2 0300 movt r3, #8192 ; 0x2000 8004f9a: 781b ldrb r3, [r3, #0] 8004f9c: f103 0301 add.w r3, r3, #1 8004fa0: 73fb strb r3, [r7, #15] if (next_head == TX_BUFFER_SIZE) { next_head = 0; } 8004fa2: 7bfb ldrb r3, [r7, #15] 8004fa4: 2b10 cmp r3, #16 8004fa6: d102 bne.n 8004fae 8004fa8: f04f 0300 mov.w r3, #0 8004fac: 73fb strb r3, [r7, #15] // Wait until there's a space in the buffer while (next_head == tx_buffer_tail) { };//sleep_mode(); }; 8004fae: bf00 nop 8004fb0: f240 63cb movw r3, #1739 ; 0x6cb 8004fb4: f2c2 0300 movt r3, #8192 ; 0x2000 8004fb8: 781b ldrb r3, [r3, #0] 8004fba: b2db uxtb r3, r3 8004fbc: 7bfa ldrb r2, [r7, #15] 8004fbe: 429a cmp r2, r3 8004fc0: d0f6 beq.n 8004fb0 // Store data and advance head tx_buffer[tx_buffer_head] = data; 8004fc2: f240 63ca movw r3, #1738 ; 0x6ca 8004fc6: f2c2 0300 movt r3, #8192 ; 0x2000 8004fca: 781b ldrb r3, [r3, #0] 8004fcc: 461a mov r2, r3 8004fce: f240 7368 movw r3, #1896 ; 0x768 8004fd2: f2c2 0300 movt r3, #8192 ; 0x2000 8004fd6: 79f9 ldrb r1, [r7, #7] 8004fd8: 5499 strb r1, [r3, r2] tx_buffer_head = next_head; 8004fda: f240 63ca movw r3, #1738 ; 0x6ca 8004fde: f2c2 0300 movt r3, #8192 ; 0x2000 8004fe2: 7bfa ldrb r2, [r7, #15] 8004fe4: 701a strb r2, [r3, #0] // Enable Data Register Empty Interrupt to make sure tx-streaming is running USART_ITConfig(USART3, USART_IT_TXE, ENABLE); 8004fe6: f44f 4090 mov.w r0, #18432 ; 0x4800 8004fea: f2c4 0000 movt r0, #16384 ; 0x4000 8004fee: f240 7127 movw r1, #1831 ; 0x727 8004ff2: f04f 0201 mov.w r2, #1 8004ff6: f7fb fb1f bl 8000638 } 8004ffa: f107 0710 add.w r7, r7, #16 8004ffe: 46bd mov sp, r7 8005000: bd80 pop {r7, pc} 8005002: bf00 nop 08005004 : #include "stepper.h" #include "settings.h" #include "nuts_bolts.h" #include "config.h" void limits_init() { 8005004: b480 push {r7} 8005006: af00 add r7, sp, #0 } 8005008: 46bd mov sp, r7 800500a: bc80 pop {r7} 800500c: 4770 bx lr 800500e: bf00 nop 08005010 : static void homing_cycle(bool x_axis, bool y_axis, bool z_axis, bool reverse_direction, uint32_t microseconds_per_pulse) { 8005010: b580 push {r7, lr} 8005012: b084 sub sp, #16 8005014: af00 add r7, sp, #0 8005016: 71f8 strb r0, [r7, #7] 8005018: 71b9 strb r1, [r7, #6] 800501a: 717a strb r2, [r7, #5] 800501c: 713b strb r3, [r7, #4] // First home the Z axis uint32_t step_delay = microseconds_per_pulse - settings.pulse_microseconds; 800501e: f240 63d8 movw r3, #1752 ; 0x6d8 8005022: f2c2 0300 movt r3, #8192 ; 0x2000 8005026: 7e5b ldrb r3, [r3, #25] 8005028: 69ba ldr r2, [r7, #24] 800502a: 1ad3 subs r3, r2, r3 800502c: 60bb str r3, [r7, #8] uint16_t out_bits = DIRECTION_MASK; 800502e: f04f 03e0 mov.w r3, #224 ; 0xe0 8005032: 81fb strh r3, [r7, #14] if (x_axis) { 8005034: 79fb ldrb r3, [r7, #7] 8005036: 2b00 cmp r3, #0 8005038: d003 beq.n 8005042 out_bits |= X_STEP_BIT; 800503a: 89fb ldrh r3, [r7, #14] 800503c: f043 0304 orr.w r3, r3, #4 8005040: 81fb strh r3, [r7, #14] } if (y_axis) { 8005042: 79bb ldrb r3, [r7, #6] 8005044: 2b00 cmp r3, #0 8005046: d003 beq.n 8005050 out_bits |= Y_STEP_BIT; 8005048: 89fb ldrh r3, [r7, #14] 800504a: f043 0308 orr.w r3, r3, #8 800504e: 81fb strh r3, [r7, #14] } if (z_axis) { 8005050: 797b ldrb r3, [r7, #5] 8005052: 2b00 cmp r3, #0 8005054: d003 beq.n 800505e out_bits |= Z_STEP_BIT; 8005056: 89fb ldrh r3, [r7, #14] 8005058: f043 0310 orr.w r3, r3, #16 800505c: 81fb strh r3, [r7, #14] } // Invert direction bits if this is a reverse homing_cycle if (reverse_direction) { 800505e: 793b ldrb r3, [r7, #4] 8005060: 2b00 cmp r3, #0 8005062: d003 beq.n 800506c out_bits ^= DIRECTION_MASK; 8005064: 89fb ldrh r3, [r7, #14] 8005066: f083 03e0 eor.w r3, r3, #224 ; 0xe0 800506a: 81fb strh r3, [r7, #14] //TODO RICHTIG? //STEPPING_PORT = (STEPPING_PORT & ~DIRECTION_MASK) | (out_bits & DIRECTION_MASK); //hier wurde die zuvor gewählten achsen gesetzt set(X_DIRECTION_BIT | Y_DIRECTION_BIT | Z_DIRECTION_BIT); 800506c: f04f 00e0 mov.w r0, #224 ; 0xe0 8005070: f7fd faec bl 800264c for (;;) { uint16_t limits = LIMIT_PIN->IDR; 8005074: f04f 0300 mov.w r3, #0 8005078: f2c4 0302 movt r3, #16386 ; 0x4002 800507c: 691b ldr r3, [r3, #16] 800507e: 81bb strh r3, [r7, #12] if (reverse_direction) { 8005080: 793b ldrb r3, [r7, #4] 8005082: 2b00 cmp r3, #0 8005084: d003 beq.n 800508e // Invert limit_bits if this is a reverse homing_cycle limits ^= LIMIT_MASK; 8005086: 89bb ldrh r3, [r7, #12] 8005088: f083 030e eor.w r3, r3, #14 800508c: 81bb strh r3, [r7, #12] } if (x_axis && !(limits & X_LIMIT_BIT)) { 800508e: 79fb ldrb r3, [r7, #7] 8005090: 2b00 cmp r3, #0 8005092: d00b beq.n 80050ac 8005094: 89bb ldrh r3, [r7, #12] 8005096: f003 0302 and.w r3, r3, #2 800509a: 2b00 cmp r3, #0 800509c: d106 bne.n 80050ac x_axis = false; 800509e: f04f 0300 mov.w r3, #0 80050a2: 71fb strb r3, [r7, #7] out_bits ^= (1 << X_STEP_BIT); 80050a4: 89fb ldrh r3, [r7, #14] 80050a6: f083 0310 eor.w r3, r3, #16 80050aa: 81fb strh r3, [r7, #14] } if (y_axis && !(limits & Y_LIMIT_BIT)) { 80050ac: 79bb ldrb r3, [r7, #6] 80050ae: 2b00 cmp r3, #0 80050b0: d00b beq.n 80050ca 80050b2: 89bb ldrh r3, [r7, #12] 80050b4: f003 0304 and.w r3, r3, #4 80050b8: 2b00 cmp r3, #0 80050ba: d106 bne.n 80050ca y_axis = false; 80050bc: f04f 0300 mov.w r3, #0 80050c0: 71bb strb r3, [r7, #6] out_bits ^= (1 << Y_STEP_BIT); 80050c2: 89fb ldrh r3, [r7, #14] 80050c4: f483 7380 eor.w r3, r3, #256 ; 0x100 80050c8: 81fb strh r3, [r7, #14] } if (z_axis && !(limits & Z_LIMIT_BIT)) { 80050ca: 797b ldrb r3, [r7, #5] 80050cc: 2b00 cmp r3, #0 80050ce: d007 beq.n 80050e0 80050d0: 89bb ldrh r3, [r7, #12] 80050d2: f003 0308 and.w r3, r3, #8 80050d6: 2b00 cmp r3, #0 80050d8: d102 bne.n 80050e0 z_axis = false; 80050da: f04f 0300 mov.w r3, #0 80050de: 717b strb r3, [r7, #5] out_bits ^= (1 << Z_STEP_BIT); } // Check if we are done if (!(x_axis || y_axis || z_axis)) { 80050e0: 79fb ldrb r3, [r7, #7] 80050e2: f083 0301 eor.w r3, r3, #1 80050e6: b2db uxtb r3, r3 80050e8: 2b00 cmp r3, #0 80050ea: d00b beq.n 8005104 80050ec: 79bb ldrb r3, [r7, #6] 80050ee: f083 0301 eor.w r3, r3, #1 80050f2: b2db uxtb r3, r3 80050f4: 2b00 cmp r3, #0 80050f6: d005 beq.n 8005104 80050f8: 797b ldrb r3, [r7, #5] 80050fa: f083 0301 eor.w r3, r3, #1 80050fe: b2db uxtb r3, r3 8005100: 2b00 cmp r3, #0 8005102: d11b bne.n 800513c return; } set(out_bits & STEP_MASK); 8005104: 89fb ldrh r3, [r7, #14] 8005106: f003 031c and.w r3, r3, #28 800510a: b29b uxth r3, r3 800510c: 4618 mov r0, r3 800510e: f7fd fa9d bl 800264c delay_us(settings.pulse_microseconds); 8005112: f240 63d8 movw r3, #1752 ; 0x6d8 8005116: f2c2 0300 movt r3, #8192 ; 0x2000 800511a: 7e5b ldrb r3, [r3, #25] 800511c: 4618 mov r0, r3 800511e: f7fd fcbd bl 8002a9c reset(out_bits & STEP_MASK); 8005122: 89fb ldrh r3, [r7, #14] 8005124: f003 031c and.w r3, r3, #28 8005128: b29b uxth r3, r3 800512a: 4618 mov r0, r3 800512c: f7fd faaa bl 8002684 delay_us(step_delay); 8005130: 68bb ldr r3, [r7, #8] 8005132: b29b uxth r3, r3 8005134: 4618 mov r0, r3 8005136: f7fd fcb1 bl 8002a9c } 800513a: e79b b.n 8005074 z_axis = false; out_bits ^= (1 << Z_STEP_BIT); } // Check if we are done if (!(x_axis || y_axis || z_axis)) { return; 800513c: bf00 nop delay_us(settings.pulse_microseconds); reset(out_bits & STEP_MASK); delay_us(step_delay); } return; } 800513e: f107 0710 add.w r7, r7, #16 8005142: 46bd mov sp, r7 8005144: bd80 pop {r7, pc} 8005146: bf00 nop 08005148 : static void approach_limit_switch(bool x, bool y, bool z) { 8005148: b580 push {r7, lr} 800514a: b084 sub sp, #16 800514c: af02 add r7, sp, #8 800514e: 4613 mov r3, r2 8005150: 4602 mov r2, r0 8005152: 71fa strb r2, [r7, #7] 8005154: 460a mov r2, r1 8005156: 71ba strb r2, [r7, #6] 8005158: 717b strb r3, [r7, #5] homing_cycle(x, y, z, false, 100000); 800515a: 79f8 ldrb r0, [r7, #7] 800515c: 79b9 ldrb r1, [r7, #6] 800515e: 797a ldrb r2, [r7, #5] 8005160: f248 63a0 movw r3, #34464 ; 0x86a0 8005164: f2c0 0301 movt r3, #1 8005168: 9300 str r3, [sp, #0] 800516a: f04f 0300 mov.w r3, #0 800516e: f7ff ff4f bl 8005010 } 8005172: f107 0708 add.w r7, r7, #8 8005176: 46bd mov sp, r7 8005178: bd80 pop {r7, pc} 800517a: bf00 nop 0800517c : static void leave_limit_switch(bool x, bool y, bool z) { 800517c: b580 push {r7, lr} 800517e: b084 sub sp, #16 8005180: af02 add r7, sp, #8 8005182: 4613 mov r3, r2 8005184: 4602 mov r2, r0 8005186: 71fa strb r2, [r7, #7] 8005188: 460a mov r2, r1 800518a: 71ba strb r2, [r7, #6] 800518c: 717b strb r3, [r7, #5] homing_cycle(x, y, z, true, 500000); 800518e: 79f8 ldrb r0, [r7, #7] 8005190: 79b9 ldrb r1, [r7, #6] 8005192: 797a ldrb r2, [r7, #5] 8005194: f24a 1320 movw r3, #41248 ; 0xa120 8005198: f2c0 0307 movt r3, #7 800519c: 9300 str r3, [sp, #0] 800519e: f04f 0301 mov.w r3, #1 80051a2: f7ff ff35 bl 8005010 } 80051a6: f107 0708 add.w r7, r7, #8 80051aa: 46bd mov sp, r7 80051ac: bd80 pop {r7, pc} 80051ae: bf00 nop 080051b0 : void limits_go_home() { 80051b0: b580 push {r7, lr} 80051b2: b082 sub sp, #8 80051b4: af00 add r7, sp, #0 st_synchronize(); 80051b6: f7fc fead bl 8001f14 // Store the current limit switch state uint16_t original_limit_state = LIMIT_PIN->IDR; 80051ba: f04f 0300 mov.w r3, #0 80051be: f2c4 0302 movt r3, #16386 ; 0x4002 80051c2: 691b ldr r3, [r3, #16] 80051c4: 80fb strh r3, [r7, #6] approach_limit_switch(false, false, true); // First home the z axis 80051c6: f04f 0000 mov.w r0, #0 80051ca: f04f 0100 mov.w r1, #0 80051ce: f04f 0201 mov.w r2, #1 80051d2: f7ff ffb9 bl 8005148 approach_limit_switch(true, true, false); // Then home the x and y axis 80051d6: f04f 0001 mov.w r0, #1 80051da: f04f 0101 mov.w r1, #1 80051de: f04f 0200 mov.w r2, #0 80051e2: f7ff ffb1 bl 8005148 // Xor previous and current limit switch state to determine which were high then but have become // low now. These are the actual installed limit switches. uint8_t limit_switches_present = (original_limit_state ^ LIMIT_PIN->IDR) 80051e6: 88fb ldrh r3, [r7, #6] 80051e8: b2da uxtb r2, r3 80051ea: f04f 0300 mov.w r3, #0 80051ee: f2c4 0302 movt r3, #16386 ; 0x4002 80051f2: 691b ldr r3, [r3, #16] 80051f4: b2db uxtb r3, r3 80051f6: 4053 eors r3, r2 80051f8: b2db uxtb r3, r3 80051fa: f003 030e and.w r3, r3, #14 80051fe: 717b strb r3, [r7, #5] & LIMIT_MASK; // Now carefully leave the limit switches leave_limit_switch(limit_switches_present & (1 << X_LIMIT_BIT), 8005200: 797b ldrb r3, [r7, #5] 8005202: f003 0304 and.w r3, r3, #4 8005206: 2b00 cmp r3, #0 8005208: bf0c ite eq 800520a: 2300 moveq r3, #0 800520c: 2301 movne r3, #1 800520e: b2d9 uxtb r1, r3 limit_switches_present & (1 << Y_LIMIT_BIT), 8005210: 797b ldrb r3, [r7, #5] 8005212: f003 0310 and.w r3, r3, #16 // Xor previous and current limit switch state to determine which were high then but have become // low now. These are the actual installed limit switches. uint8_t limit_switches_present = (original_limit_state ^ LIMIT_PIN->IDR) & LIMIT_MASK; // Now carefully leave the limit switches leave_limit_switch(limit_switches_present & (1 << X_LIMIT_BIT), 8005216: 2b00 cmp r3, #0 8005218: bf0c ite eq 800521a: 2300 moveq r3, #0 800521c: 2301 movne r3, #1 800521e: b2da uxtb r2, r3 limit_switches_present & (1 << Y_LIMIT_BIT), limit_switches_present & (1 << Z_LIMIT_BIT)); 8005220: 797b ldrb r3, [r7, #5] 8005222: f403 7380 and.w r3, r3, #256 ; 0x100 // Xor previous and current limit switch state to determine which were high then but have become // low now. These are the actual installed limit switches. uint8_t limit_switches_present = (original_limit_state ^ LIMIT_PIN->IDR) & LIMIT_MASK; // Now carefully leave the limit switches leave_limit_switch(limit_switches_present & (1 << X_LIMIT_BIT), 8005226: 2b00 cmp r3, #0 8005228: bf0c ite eq 800522a: 2300 moveq r3, #0 800522c: 2301 movne r3, #1 800522e: b2db uxtb r3, r3 8005230: 4608 mov r0, r1 8005232: 4611 mov r1, r2 8005234: 461a mov r2, r3 8005236: f7ff ffa1 bl 800517c limit_switches_present & (1 << Y_LIMIT_BIT), limit_switches_present & (1 << Z_LIMIT_BIT)); } 800523a: f107 0708 add.w r7, r7, #8 800523e: 46bd mov sp, r7 8005240: bd80 pop {r7, pc} 8005242: bf00 nop 08005244 : static int current_direction; void spindle_init() { 8005244: b580 push {r7, lr} 8005246: b082 sub sp, #8 8005248: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStructure; GPIO_InitStructure.GPIO_Pin = SPINDLE_ENABLE_BIT | SPINDLE_DIRECTION_BIT; 800524a: f04f 0306 mov.w r3, #6 800524e: 603b str r3, [r7, #0] GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; 8005250: f04f 0301 mov.w r3, #1 8005254: 713b strb r3, [r7, #4] GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; 8005256: f04f 0300 mov.w r3, #0 800525a: 71bb strb r3, [r7, #6] GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; 800525c: f04f 0303 mov.w r3, #3 8005260: 717b strb r3, [r7, #5] GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; 8005262: f04f 0302 mov.w r3, #2 8005266: 71fb strb r3, [r7, #7] GPIO_Init(SPINDLE_PORT, &GPIO_InitStructure); 8005268: 463b mov r3, r7 800526a: f44f 6080 mov.w r0, #1024 ; 0x400 800526e: f2c4 0002 movt r0, #16386 ; 0x4002 8005272: 4619 mov r1, r3 8005274: f7fd fc3a bl 8002aec spindle_run(0, 0); 8005278: f04f 0000 mov.w r0, #0 800527c: f04f 0100 mov.w r1, #0 8005280: f000 f804 bl 800528c } 8005284: f107 0708 add.w r7, r7, #8 8005288: 46bd mov sp, r7 800528a: bd80 pop {r7, pc} 0800528c : void spindle_run(int8_t direction, int32_t rpm) { 800528c: b580 push {r7, lr} 800528e: b082 sub sp, #8 8005290: af00 add r7, sp, #0 8005292: 4603 mov r3, r0 8005294: 6039 str r1, [r7, #0] 8005296: 71fb strb r3, [r7, #7] if (direction != current_direction) { 8005298: f997 2007 ldrsb.w r2, [r7, #7] 800529c: f240 63cc movw r3, #1740 ; 0x6cc 80052a0: f2c2 0300 movt r3, #8192 ; 0x2000 80052a4: 681b ldr r3, [r3, #0] 80052a6: 429a cmp r2, r3 80052a8: d02e beq.n 8005308 st_synchronize(); 80052aa: f7fc fe33 bl 8001f14 if(direction) { 80052ae: f997 3007 ldrsb.w r3, [r7, #7] 80052b2: 2b00 cmp r3, #0 80052b4: d01a beq.n 80052ec if(direction > 0) { 80052b6: f997 3007 ldrsb.w r3, [r7, #7] 80052ba: 2b00 cmp r3, #0 80052bc: dd07 ble.n 80052ce SPINDLE_PORT->BSRRH = SPINDLE_DIRECTION_BIT; //reset 80052be: f44f 6380 mov.w r3, #1024 ; 0x400 80052c2: f2c4 0302 movt r3, #16386 ; 0x4002 80052c6: f04f 0204 mov.w r2, #4 80052ca: 835a strh r2, [r3, #26] 80052cc: e006 b.n 80052dc } else { SPINDLE_PORT->BSRRL = SPINDLE_DIRECTION_BIT; //set 80052ce: f44f 6380 mov.w r3, #1024 ; 0x400 80052d2: f2c4 0302 movt r3, #16386 ; 0x4002 80052d6: f04f 0204 mov.w r2, #4 80052da: 831a strh r2, [r3, #24] } SPINDLE_PORT->BSRRL = SPINDLE_ENABLE_BIT; 80052dc: f44f 6380 mov.w r3, #1024 ; 0x400 80052e0: f2c4 0302 movt r3, #16386 ; 0x4002 80052e4: f04f 0202 mov.w r2, #2 80052e8: 831a strh r2, [r3, #24] 80052ea: e006 b.n 80052fa } else { SPINDLE_PORT->BSRRH = SPINDLE_ENABLE_BIT; 80052ec: f44f 6380 mov.w r3, #1024 ; 0x400 80052f0: f2c4 0302 movt r3, #16386 ; 0x4002 80052f4: f04f 0202 mov.w r2, #2 80052f8: 835a strh r2, [r3, #26] } current_direction = direction; 80052fa: f997 2007 ldrsb.w r2, [r7, #7] 80052fe: f240 63cc movw r3, #1740 ; 0x6cc 8005302: f2c2 0300 movt r3, #8192 ; 0x2000 8005306: 601a str r2, [r3, #0] } } 8005308: f107 0708 add.w r7, r7, #8 800530c: 46bd mov sp, r7 800530e: bd80 pop {r7, pc} 08005310 : * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure * that contains the configuration information for the specified TIM peripheral. * @retval None */ void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) { 8005310: b480 push {r7} 8005312: b085 sub sp, #20 8005314: af00 add r7, sp, #0 8005316: 6078 str r0, [r7, #4] 8005318: 6039 str r1, [r7, #0] uint16_t tmpcr1 = 0; 800531a: f04f 0300 mov.w r3, #0 800531e: 81fb strh r3, [r7, #14] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); tmpcr1 = TIMx->CR1; 8005320: 687b ldr r3, [r7, #4] 8005322: 881b ldrh r3, [r3, #0] 8005324: 81fb strh r3, [r7, #14] if((TIMx == TIM1) || (TIMx == TIM8)|| 8005326: 687a ldr r2, [r7, #4] 8005328: f04f 0300 mov.w r3, #0 800532c: f2c4 0301 movt r3, #16385 ; 0x4001 8005330: 429a cmp r2, r3 8005332: d01f beq.n 8005374 8005334: 687a ldr r2, [r7, #4] 8005336: f44f 6380 mov.w r3, #1024 ; 0x400 800533a: f2c4 0301 movt r3, #16385 ; 0x4001 800533e: 429a cmp r2, r3 8005340: d018 beq.n 8005374 8005342: 687b ldr r3, [r7, #4] 8005344: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 8005348: d014 beq.n 8005374 (TIMx == TIM2) || (TIMx == TIM3)|| 800534a: 687a ldr r2, [r7, #4] 800534c: f44f 6380 mov.w r3, #1024 ; 0x400 8005350: f2c4 0300 movt r3, #16384 ; 0x4000 8005354: 429a cmp r2, r3 8005356: d00d beq.n 8005374 8005358: 687a ldr r2, [r7, #4] 800535a: f44f 6300 mov.w r3, #2048 ; 0x800 800535e: f2c4 0300 movt r3, #16384 ; 0x4000 8005362: 429a cmp r2, r3 8005364: d006 beq.n 8005374 (TIMx == TIM4) || (TIMx == TIM5)) 8005366: 687a ldr r2, [r7, #4] 8005368: f44f 6340 mov.w r3, #3072 ; 0xc00 800536c: f2c4 0300 movt r3, #16384 ; 0x4000 8005370: 429a cmp r2, r3 8005372: d108 bne.n 8005386 { /* Select the Counter Mode */ tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS)); 8005374: 89fb ldrh r3, [r7, #14] 8005376: f023 0370 bic.w r3, r3, #112 ; 0x70 800537a: 81fb strh r3, [r7, #14] tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; 800537c: 683b ldr r3, [r7, #0] 800537e: 885a ldrh r2, [r3, #2] 8005380: 89fb ldrh r3, [r7, #14] 8005382: 4313 orrs r3, r2 8005384: 81fb strh r3, [r7, #14] } if((TIMx != TIM6) && (TIMx != TIM7)) 8005386: 687a ldr r2, [r7, #4] 8005388: f44f 5380 mov.w r3, #4096 ; 0x1000 800538c: f2c4 0300 movt r3, #16384 ; 0x4000 8005390: 429a cmp r2, r3 8005392: d00f beq.n 80053b4 8005394: 687a ldr r2, [r7, #4] 8005396: f44f 53a0 mov.w r3, #5120 ; 0x1400 800539a: f2c4 0300 movt r3, #16384 ; 0x4000 800539e: 429a cmp r2, r3 80053a0: d008 beq.n 80053b4 { /* Set the clock division */ tmpcr1 &= (uint16_t)(~TIM_CR1_CKD); 80053a2: 89fb ldrh r3, [r7, #14] 80053a4: f423 7340 bic.w r3, r3, #768 ; 0x300 80053a8: 81fb strh r3, [r7, #14] tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; 80053aa: 683b ldr r3, [r7, #0] 80053ac: 891a ldrh r2, [r3, #8] 80053ae: 89fb ldrh r3, [r7, #14] 80053b0: 4313 orrs r3, r2 80053b2: 81fb strh r3, [r7, #14] } TIMx->CR1 = tmpcr1; 80053b4: 687b ldr r3, [r7, #4] 80053b6: 89fa ldrh r2, [r7, #14] 80053b8: 801a strh r2, [r3, #0] /* Set the Autoreload value */ TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; 80053ba: 683b ldr r3, [r7, #0] 80053bc: 685a ldr r2, [r3, #4] 80053be: 687b ldr r3, [r7, #4] 80053c0: 62da str r2, [r3, #44] ; 0x2c /* Set the Prescaler value */ TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; 80053c2: 683b ldr r3, [r7, #0] 80053c4: 881a ldrh r2, [r3, #0] 80053c6: 687b ldr r3, [r7, #4] 80053c8: 851a strh r2, [r3, #40] ; 0x28 if ((TIMx == TIM1) || (TIMx == TIM8)) 80053ca: 687a ldr r2, [r7, #4] 80053cc: f04f 0300 mov.w r3, #0 80053d0: f2c4 0301 movt r3, #16385 ; 0x4001 80053d4: 429a cmp r2, r3 80053d6: d006 beq.n 80053e6 80053d8: 687a ldr r2, [r7, #4] 80053da: f44f 6380 mov.w r3, #1024 ; 0x400 80053de: f2c4 0301 movt r3, #16385 ; 0x4001 80053e2: 429a cmp r2, r3 80053e4: d104 bne.n 80053f0 { /* Set the Repetition Counter value */ TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; 80053e6: 683b ldr r3, [r7, #0] 80053e8: 7a9b ldrb r3, [r3, #10] 80053ea: 461a mov r2, r3 80053ec: 687b ldr r3, [r7, #4] 80053ee: 861a strh r2, [r3, #48] ; 0x30 } /* Generate an update event to reload the Prescaler and the repetition counter(only for TIM1 and TIM8) value immediatly */ TIMx->EGR = TIM_PSCReloadMode_Immediate; 80053f0: 687b ldr r3, [r7, #4] 80053f2: f04f 0201 mov.w r2, #1 80053f6: 829a strh r2, [r3, #20] } 80053f8: f107 0714 add.w r7, r7, #20 80053fc: 46bd mov sp, r7 80053fe: bc80 pop {r7} 8005400: 4770 bx lr 8005402: bf00 nop 08005404 : * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef * structure which will be initialized. * @retval None */ void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) { 8005404: b480 push {r7} 8005406: b083 sub sp, #12 8005408: af00 add r7, sp, #0 800540a: 6078 str r0, [r7, #4] /* Set the default configuration */ TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; 800540c: 687b ldr r3, [r7, #4] 800540e: f04f 32ff mov.w r2, #4294967295 8005412: 605a str r2, [r3, #4] TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; 8005414: 687b ldr r3, [r7, #4] 8005416: f04f 0200 mov.w r2, #0 800541a: 801a strh r2, [r3, #0] TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; 800541c: 687b ldr r3, [r7, #4] 800541e: f04f 0200 mov.w r2, #0 8005422: 811a strh r2, [r3, #8] TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; 8005424: 687b ldr r3, [r7, #4] 8005426: f04f 0200 mov.w r2, #0 800542a: 805a strh r2, [r3, #2] TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; 800542c: 687b ldr r3, [r7, #4] 800542e: f04f 0200 mov.w r2, #0 8005432: 729a strb r2, [r3, #10] } 8005434: f107 070c add.w r7, r7, #12 8005438: 46bd mov sp, r7 800543a: bc80 pop {r7} 800543c: 4770 bx lr 800543e: bf00 nop 08005440 : * @param TIMx: where x can be 1 to 14 to select the TIM peripheral. * @param Counter: specifies the Counter register new value. * @retval None */ void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) { 8005440: b480 push {r7} 8005442: b083 sub sp, #12 8005444: af00 add r7, sp, #0 8005446: 6078 str r0, [r7, #4] 8005448: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); /* Set the Counter Register value */ TIMx->CNT = Counter; 800544a: 687b ldr r3, [r7, #4] 800544c: 683a ldr r2, [r7, #0] 800544e: 625a str r2, [r3, #36] ; 0x24 } 8005450: f107 070c add.w r7, r7, #12 8005454: 46bd mov sp, r7 8005456: bc80 pop {r7} 8005458: 4770 bx lr 800545a: bf00 nop 0800545c : * @param NewState: new state of the TIMx peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) { 800545c: b480 push {r7} 800545e: b083 sub sp, #12 8005460: af00 add r7, sp, #0 8005462: 6078 str r0, [r7, #4] 8005464: 460b mov r3, r1 8005466: 70fb strb r3, [r7, #3] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 8005468: 78fb ldrb r3, [r7, #3] 800546a: 2b00 cmp r3, #0 800546c: d008 beq.n 8005480 { /* Enable the TIM Counter */ TIMx->CR1 |= TIM_CR1_CEN; 800546e: 687b ldr r3, [r7, #4] 8005470: 881b ldrh r3, [r3, #0] 8005472: b29b uxth r3, r3 8005474: f043 0301 orr.w r3, r3, #1 8005478: b29a uxth r2, r3 800547a: 687b ldr r3, [r7, #4] 800547c: 801a strh r2, [r3, #0] 800547e: e007 b.n 8005490 } else { /* Disable the TIM Counter */ TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN; 8005480: 687b ldr r3, [r7, #4] 8005482: 881b ldrh r3, [r3, #0] 8005484: b29b uxth r3, r3 8005486: f023 0301 bic.w r3, r3, #1 800548a: b29a uxth r2, r3 800548c: 687b ldr r3, [r7, #4] 800548e: 801a strh r2, [r3, #0] } } 8005490: f107 070c add.w r7, r7, #12 8005494: 46bd mov sp, r7 8005496: bc80 pop {r7} 8005498: 4770 bx lr 800549a: bf00 nop 0800549c : * @param TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral. * @param Compare1: specifies the Capture Compare1 register new value. * @retval None */ void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) { 800549c: b480 push {r7} 800549e: b083 sub sp, #12 80054a0: af00 add r7, sp, #0 80054a2: 6078 str r0, [r7, #4] 80054a4: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_LIST1_PERIPH(TIMx)); /* Set the Capture Compare1 Register value */ TIMx->CCR1 = Compare1; 80054a6: 687b ldr r3, [r7, #4] 80054a8: 683a ldr r2, [r7, #0] 80054aa: 635a str r2, [r3, #52] ; 0x34 } 80054ac: f107 070c add.w r7, r7, #12 80054b0: 46bd mov sp, r7 80054b2: bc80 pop {r7} 80054b4: 4770 bx lr 80054b6: bf00 nop 080054b8 : * @param NewState: new state of the TIM interrupts. * This parameter can be: ENABLE or DISABLE. * @retval None */ void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) { 80054b8: b480 push {r7} 80054ba: b083 sub sp, #12 80054bc: af00 add r7, sp, #0 80054be: 6078 str r0, [r7, #4] 80054c0: 4613 mov r3, r2 80054c2: 460a mov r2, r1 80054c4: 807a strh r2, [r7, #2] 80054c6: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_IT(TIM_IT)); assert_param(IS_FUNCTIONAL_STATE(NewState)); if (NewState != DISABLE) 80054c8: 787b ldrb r3, [r7, #1] 80054ca: 2b00 cmp r3, #0 80054cc: d008 beq.n 80054e0 { /* Enable the Interrupt sources */ TIMx->DIER |= TIM_IT; 80054ce: 687b ldr r3, [r7, #4] 80054d0: 899b ldrh r3, [r3, #12] 80054d2: b29a uxth r2, r3 80054d4: 887b ldrh r3, [r7, #2] 80054d6: 4313 orrs r3, r2 80054d8: b29a uxth r2, r3 80054da: 687b ldr r3, [r7, #4] 80054dc: 819a strh r2, [r3, #12] 80054de: e00a b.n 80054f6 } else { /* Disable the Interrupt sources */ TIMx->DIER &= (uint16_t)~TIM_IT; 80054e0: 687b ldr r3, [r7, #4] 80054e2: 899b ldrh r3, [r3, #12] 80054e4: b29a uxth r2, r3 80054e6: 887b ldrh r3, [r7, #2] 80054e8: ea6f 0303 mvn.w r3, r3 80054ec: b29b uxth r3, r3 80054ee: 4013 ands r3, r2 80054f0: b29a uxth r2, r3 80054f2: 687b ldr r3, [r7, #4] 80054f4: 819a strh r2, [r3, #12] } } 80054f6: f107 070c add.w r7, r7, #12 80054fa: 46bd mov sp, r7 80054fc: bc80 pop {r7} 80054fe: 4770 bx lr 08005500 : * @note TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8. * * @retval None */ void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) { 8005500: b480 push {r7} 8005502: b083 sub sp, #12 8005504: af00 add r7, sp, #0 8005506: 6078 str r0, [r7, #4] 8005508: 460b mov r3, r1 800550a: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); /* Clear the flags */ TIMx->SR = (uint16_t)~TIM_FLAG; 800550c: 887b ldrh r3, [r7, #2] 800550e: ea6f 0303 mvn.w r3, r3 8005512: b29a uxth r2, r3 8005514: 687b ldr r3, [r7, #4] 8005516: 821a strh r2, [r3, #16] } 8005518: f107 070c add.w r7, r7, #12 800551c: 46bd mov sp, r7 800551e: bc80 pop {r7} 8005520: 4770 bx lr 8005522: bf00 nop 08005524 : * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. * * @retval The new state of the TIM_IT(SET or RESET). */ ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) { 8005524: b480 push {r7} 8005526: b085 sub sp, #20 8005528: af00 add r7, sp, #0 800552a: 6078 str r0, [r7, #4] 800552c: 460b mov r3, r1 800552e: 807b strh r3, [r7, #2] ITStatus bitstatus = RESET; 8005530: f04f 0300 mov.w r3, #0 8005534: 73fb strb r3, [r7, #15] uint16_t itstatus = 0x0, itenable = 0x0; 8005536: f04f 0300 mov.w r3, #0 800553a: 81bb strh r3, [r7, #12] 800553c: f04f 0300 mov.w r3, #0 8005540: 817b strh r3, [r7, #10] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); assert_param(IS_TIM_GET_IT(TIM_IT)); itstatus = TIMx->SR & TIM_IT; 8005542: 687b ldr r3, [r7, #4] 8005544: 8a1b ldrh r3, [r3, #16] 8005546: b29a uxth r2, r3 8005548: 887b ldrh r3, [r7, #2] 800554a: 4013 ands r3, r2 800554c: 81bb strh r3, [r7, #12] itenable = TIMx->DIER & TIM_IT; 800554e: 687b ldr r3, [r7, #4] 8005550: 899b ldrh r3, [r3, #12] 8005552: b29a uxth r2, r3 8005554: 887b ldrh r3, [r7, #2] 8005556: 4013 ands r3, r2 8005558: 817b strh r3, [r7, #10] if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) 800555a: 89bb ldrh r3, [r7, #12] 800555c: 2b00 cmp r3, #0 800555e: d006 beq.n 800556e 8005560: 897b ldrh r3, [r7, #10] 8005562: 2b00 cmp r3, #0 8005564: d003 beq.n 800556e { bitstatus = SET; 8005566: f04f 0301 mov.w r3, #1 800556a: 73fb strb r3, [r7, #15] 800556c: e002 b.n 8005574 } else { bitstatus = RESET; 800556e: f04f 0300 mov.w r3, #0 8005572: 73fb strb r3, [r7, #15] } return bitstatus; 8005574: 7bfb ldrb r3, [r7, #15] } 8005576: 4618 mov r0, r3 8005578: f107 0714 add.w r7, r7, #20 800557c: 46bd mov sp, r7 800557e: bc80 pop {r7} 8005580: 4770 bx lr 8005582: bf00 nop 08005584 : * @note TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8. * * @retval None */ void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) { 8005584: b480 push {r7} 8005586: b083 sub sp, #12 8005588: af00 add r7, sp, #0 800558a: 6078 str r0, [r7, #4] 800558c: 460b mov r3, r1 800558e: 807b strh r3, [r7, #2] /* Check the parameters */ assert_param(IS_TIM_ALL_PERIPH(TIMx)); /* Clear the IT pending Bit */ TIMx->SR = (uint16_t)~TIM_IT; 8005590: 887b ldrh r3, [r7, #2] 8005592: ea6f 0303 mvn.w r3, r3 8005596: b29a uxth r2, r3 8005598: 687b ldr r3, [r7, #4] 800559a: 821a strh r2, [r3, #16] } 800559c: f107 070c add.w r7, r7, #12 80055a0: 46bd mov sp, r7 80055a2: bc80 pop {r7} 80055a4: 4770 bx lr 80055a6: bf00 nop 080055a8 : * * \param addr EEPROM address to read from. * \return The byte read from the EEPROM address. */ unsigned char eeprom_get_char( unsigned int addr ) { 80055a8: b480 push {r7} 80055aa: b083 sub sp, #12 80055ac: af00 add r7, sp, #0 80055ae: 6078 str r0, [r7, #4] /*do {} while( EECR & (1<: * * \param addr EEPROM address to write to. * \param new_value New EEPROM value. */ void eeprom_put_char( unsigned int addr, unsigned char new_value ) { 80055c0: b480 push {r7} 80055c2: b083 sub sp, #12 80055c4: af00 add r7, sp, #0 80055c6: 6078 str r0, [r7, #4] 80055c8: 460b mov r3, r1 80055ca: 70fb strb r3, [r7, #3] EECR |= (1<: // Extensions added as part of Grbl void memcpy_to_eeprom_with_checksum(unsigned int destination, char *source, unsigned int size) { 80055d8: b580 push {r7, lr} 80055da: b086 sub sp, #24 80055dc: af00 add r7, sp, #0 80055de: 60f8 str r0, [r7, #12] 80055e0: 60b9 str r1, [r7, #8] 80055e2: 607a str r2, [r7, #4] unsigned char checksum = 0; 80055e4: f04f 0300 mov.w r3, #0 80055e8: 75fb strb r3, [r7, #23] for(; size > 0; size--) { 80055ea: e026 b.n 800563a checksum = (checksum << 1) || (checksum >> 7); 80055ec: 7dfb ldrb r3, [r7, #23] 80055ee: ea4f 0343 mov.w r3, r3, lsl #1 80055f2: 2b00 cmp r3, #0 80055f4: d103 bne.n 80055fe 80055f6: 7dfb ldrb r3, [r7, #23] 80055f8: b25b sxtb r3, r3 80055fa: 2b00 cmp r3, #0 80055fc: da02 bge.n 8005604 80055fe: f04f 0301 mov.w r3, #1 8005602: e001 b.n 8005608 8005604: f04f 0300 mov.w r3, #0 8005608: 75fb strb r3, [r7, #23] checksum += *source; 800560a: 68bb ldr r3, [r7, #8] 800560c: 781a ldrb r2, [r3, #0] 800560e: 7dfb ldrb r3, [r7, #23] 8005610: 18d3 adds r3, r2, r3 8005612: 75fb strb r3, [r7, #23] eeprom_put_char(destination++, *(source++)); 8005614: 68fa ldr r2, [r7, #12] 8005616: 68fb ldr r3, [r7, #12] 8005618: f103 0301 add.w r3, r3, #1 800561c: 60fb str r3, [r7, #12] 800561e: 68bb ldr r3, [r7, #8] 8005620: 781b ldrb r3, [r3, #0] 8005622: 68b9 ldr r1, [r7, #8] 8005624: f101 0101 add.w r1, r1, #1 8005628: 60b9 str r1, [r7, #8] 800562a: 4610 mov r0, r2 800562c: 4619 mov r1, r3 800562e: f7ff ffc7 bl 80055c0 // Extensions added as part of Grbl void memcpy_to_eeprom_with_checksum(unsigned int destination, char *source, unsigned int size) { unsigned char checksum = 0; for(; size > 0; size--) { 8005632: 687b ldr r3, [r7, #4] 8005634: f103 33ff add.w r3, r3, #4294967295 8005638: 607b str r3, [r7, #4] 800563a: 687b ldr r3, [r7, #4] 800563c: 2b00 cmp r3, #0 800563e: d1d5 bne.n 80055ec checksum = (checksum << 1) || (checksum >> 7); checksum += *source; eeprom_put_char(destination++, *(source++)); } eeprom_put_char(destination, checksum); 8005640: 7dfb ldrb r3, [r7, #23] 8005642: 68f8 ldr r0, [r7, #12] 8005644: 4619 mov r1, r3 8005646: f7ff ffbb bl 80055c0 } 800564a: f107 0718 add.w r7, r7, #24 800564e: 46bd mov sp, r7 8005650: bd80 pop {r7, pc} 8005652: bf00 nop 08005654 : int memcpy_from_eeprom_with_checksum(char *destination, unsigned int source, unsigned int size) { 8005654: b580 push {r7, lr} 8005656: b086 sub sp, #24 8005658: af00 add r7, sp, #0 800565a: 60f8 str r0, [r7, #12] 800565c: 60b9 str r1, [r7, #8] 800565e: 607a str r2, [r7, #4] unsigned char data, checksum = 0; 8005660: f04f 0300 mov.w r3, #0 8005664: 75fb strb r3, [r7, #23] for(; size > 0; size--) { 8005666: e027 b.n 80056b8 data = eeprom_get_char(source++); 8005668: 68bb ldr r3, [r7, #8] 800566a: 68ba ldr r2, [r7, #8] 800566c: f102 0201 add.w r2, r2, #1 8005670: 60ba str r2, [r7, #8] 8005672: 4618 mov r0, r3 8005674: f7ff ff98 bl 80055a8 8005678: 4603 mov r3, r0 800567a: 75bb strb r3, [r7, #22] checksum = (checksum << 1) || (checksum >> 7); 800567c: 7dfb ldrb r3, [r7, #23] 800567e: ea4f 0343 mov.w r3, r3, lsl #1 8005682: 2b00 cmp r3, #0 8005684: d103 bne.n 800568e 8005686: 7dfb ldrb r3, [r7, #23] 8005688: b25b sxtb r3, r3 800568a: 2b00 cmp r3, #0 800568c: da02 bge.n 8005694 800568e: f04f 0301 mov.w r3, #1 8005692: e001 b.n 8005698 8005694: f04f 0300 mov.w r3, #0 8005698: 75fb strb r3, [r7, #23] checksum += data; 800569a: 7dfa ldrb r2, [r7, #23] 800569c: 7dbb ldrb r3, [r7, #22] 800569e: 18d3 adds r3, r2, r3 80056a0: 75fb strb r3, [r7, #23] *(destination++) = data; 80056a2: 68fb ldr r3, [r7, #12] 80056a4: 7dba ldrb r2, [r7, #22] 80056a6: 701a strb r2, [r3, #0] 80056a8: 68fb ldr r3, [r7, #12] 80056aa: f103 0301 add.w r3, r3, #1 80056ae: 60fb str r3, [r7, #12] eeprom_put_char(destination, checksum); } int memcpy_from_eeprom_with_checksum(char *destination, unsigned int source, unsigned int size) { unsigned char data, checksum = 0; for(; size > 0; size--) { 80056b0: 687b ldr r3, [r7, #4] 80056b2: f103 33ff add.w r3, r3, #4294967295 80056b6: 607b str r3, [r7, #4] 80056b8: 687b ldr r3, [r7, #4] 80056ba: 2b00 cmp r3, #0 80056bc: d1d4 bne.n 8005668 data = eeprom_get_char(source++); checksum = (checksum << 1) || (checksum >> 7); checksum += data; *(destination++) = data; } return(checksum == eeprom_get_char(source)); 80056be: 68b8 ldr r0, [r7, #8] 80056c0: f7ff ff72 bl 80055a8 80056c4: 4603 mov r3, r0 80056c6: 7dfa ldrb r2, [r7, #23] 80056c8: 429a cmp r2, r3 80056ca: bf14 ite ne 80056cc: 2300 movne r3, #0 80056ce: 2301 moveq r3, #1 } 80056d0: 4618 mov r0, r3 80056d2: f107 0718 add.w r7, r7, #24 80056d6: 46bd mov sp, r7 80056d8: bd80 pop {r7, pc} 80056da: bf00 nop 080056dc <__errno>: 80056dc: e59f3004 ldr r3, [pc, #4] ; 80056e8 <__errno+0xc> 80056e0: e5930000 ldr r0, [r3] 80056e4: e12fff1e bx lr 80056e8: 20000438 .word 0x20000438 080056ec <__fpclassifyd>: 80056ec: e1a03001 mov r3, r1 80056f0: e1901003 orrs r1, r0, r3 80056f4: 1a000001 bne 8005700 <__fpclassifyd+0x14> 80056f8: e3a00002 mov r0, #2 80056fc: e12fff1e bx lr 8005700: e2701001 rsbs r1, r0, #1 8005704: 33a01000 movcc r1, #0 8005708: e3530102 cmp r3, #-2147483648 ; 0x80000000 800570c: 03500000 cmpeq r0, #0 8005710: 0afffff8 beq 80056f8 <__fpclassifyd+0xc> 8005714: e283c47f add ip, r3, #2130706432 ; 0x7f000000 8005718: e59f2048 ldr r2, [pc, #72] ; 8005768 <__fpclassifyd+0x7c> 800571c: e2430601 sub r0, r3, #1048576 ; 0x100000 8005720: e28cc60f add ip, ip, #15728640 ; 0xf00000 8005724: e1500002 cmp r0, r2 8005728: 815c0002 cmphi ip, r2 800572c: 93a00004 movls r0, #4 8005730: 912fff1e bxls lr 8005734: e2832102 add r2, r3, #-2147483648 ; 0x80000000 8005738: e3530601 cmp r3, #1048576 ; 0x100000 800573c: 23520601 cmpcs r2, #1048576 ; 0x100000 8005740: 2a000001 bcs 800574c <__fpclassifyd+0x60> 8005744: e3a00003 mov r0, #3 8005748: e12fff1e bx lr 800574c: e59f2018 ldr r2, [pc, #24] ; 800576c <__fpclassifyd+0x80> 8005750: e3730601 cmn r3, #1048576 ; 0x100000 8005754: 11530002 cmpne r3, r2 8005758: 13a03000 movne r3, #0 800575c: 03a03001 moveq r3, #1 8005760: e0010003 and r0, r1, r3 8005764: e12fff1e bx lr 8005768: 7fdfffff .word 0x7fdfffff 800576c: 7ff00000 .word 0x7ff00000 08005770 : 8005770: e92d4ff0 push {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8005774: e1a06081 lsl r6, r1, #1 8005778: e1a06aa6 lsr r6, r6, #21 800577c: e2464fff sub r4, r6, #1020 ; 0x3fc 8005780: e2444003 sub r4, r4, #3 8005784: e24dd00c sub sp, sp, #12 8005788: e3540013 cmp r4, #19 800578c: e88d0003 stm sp, {r0, r1} 8005790: e1a0a000 mov sl, r0 8005794: e1a0b001 mov fp, r1 8005798: e1a05001 mov r5, r1 800579c: e1a08001 mov r8, r1 80057a0: e1a07000 mov r7, r0 80057a4: ca000016 bgt 8005804 80057a8: e3540000 cmp r4, #0 80057ac: ba000037 blt 8005890 80057b0: e59f3148 ldr r3, [pc, #328] ; 8005900 80057b4: e1a06453 asr r6, r3, r4 80057b8: e0065001 and r5, r6, r1 80057bc: e1955000 orrs r5, r5, r0 80057c0: 0a00000b beq 80057f4 80057c4: e28f3f4b add r3, pc, #300 ; 0x12c 80057c8: e893000c ldm r3, {r2, r3} 80057cc: fa000c2a blx 800887c <__adddf3> 80057d0: e3a02000 mov r2, #0 80057d4: e3a03000 mov r3, #0 80057d8: fa000e48 blx 8009100 <__aeabi_dcmpgt> 80057dc: e3500000 cmp r0, #0 80057e0: 1a00003d bne 80058dc 80057e4: e1a0800b mov r8, fp 80057e8: e1a01008 mov r1, r8 80057ec: e1a0000a mov r0, sl 80057f0: e88d0003 stm sp, {r0, r1} 80057f4: e89d0003 ldm sp, {r0, r1} 80057f8: e28dd00c add sp, sp, #12 80057fc: e8bd4ff0 pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8005800: e12fff1e bx lr 8005804: e3540033 cmp r4, #51 ; 0x33 8005808: da000005 ble 8005824 800580c: e3540b01 cmp r4, #1024 ; 0x400 8005810: 1afffff7 bne 80057f4 8005814: e89d000c ldm sp, {r2, r3} 8005818: fa000c17 blx 800887c <__adddf3> 800581c: e88d0003 stm sp, {r0, r1} 8005820: eafffff3 b 80057f4 8005824: e2463e41 sub r3, r6, #1040 ; 0x410 8005828: e2433003 sub r3, r3, #3 800582c: e3e02000 mvn r2, #0 8005830: e1a09332 lsr r9, r2, r3 8005834: e1190000 tst r9, r0 8005838: 0affffed beq 80057f4 800583c: e28f30b4 add r3, pc, #180 ; 0xb4 8005840: e893000c ldm r3, {r2, r3} 8005844: fa000c0c blx 800887c <__adddf3> 8005848: e3a02000 mov r2, #0 800584c: e3a03000 mov r3, #0 8005850: fa000e2a blx 8009100 <__aeabi_dcmpgt> 8005854: e3500000 cmp r0, #0 8005858: 0affffe1 beq 80057e4 800585c: e35b0000 cmp fp, #0 8005860: da000008 ble 8005888 8005864: e3540014 cmp r4, #20 8005868: 0a000005 beq 8005884 800586c: e2666e43 rsb r6, r6, #1072 ; 0x430 8005870: e2866003 add r6, r6, #3 8005874: e3a0a001 mov sl, #1 8005878: e087a61a add sl, r7, sl, lsl r6 800587c: e157000a cmp r7, sl 8005880: 9a000000 bls 8005888 8005884: e2888001 add r8, r8, #1 8005888: e1caa009 bic sl, sl, r9 800588c: eaffffd5 b 80057e8 8005890: e28f3060 add r3, pc, #96 ; 0x60 8005894: e893000c ldm r3, {r2, r3} 8005898: fa000bf7 blx 800887c <__adddf3> 800589c: e3a02000 mov r2, #0 80058a0: e3a03000 mov r3, #0 80058a4: fa000e15 blx 8009100 <__aeabi_dcmpgt> 80058a8: e3500000 cmp r0, #0 80058ac: 0affffcd beq 80057e8 80058b0: e35b0000 cmp fp, #0 80058b4: b3a0a000 movlt sl, #0 80058b8: b3a08102 movlt r8, #-2147483648 ; 0x80000000 80058bc: baffffc9 blt 80057e8 80058c0: e187500b orr r5, r7, fp 80058c4: e59f8038 ldr r8, [pc, #56] ; 8005904 80058c8: e3550000 cmp r5, #0 80058cc: 01a0a005 moveq sl, r5 80058d0: 13a0a000 movne sl, #0 80058d4: 01a08005 moveq r8, r5 80058d8: eaffffc2 b 80057e8 80058dc: e35b0000 cmp fp, #0 80058e0: c3a03601 movgt r3, #1048576 ; 0x100000 80058e4: c08b8453 addgt r8, fp, r3, asr r4 80058e8: e3a0a000 mov sl, #0 80058ec: e1c88006 bic r8, r8, r6 80058f0: eaffffbc b 80057e8 80058f4: e1a00000 nop ; (mov r0, r0) 80058f8: 8800759c .word 0x8800759c 80058fc: 7e37e43c .word 0x7e37e43c 8005900: 000fffff .word 0x000fffff 8005904: 3ff00000 .word 0x3ff00000 08005908 : 8005908: e92d4030 push {r4, r5, lr} 800590c: e59f20e0 ldr r2, [pc, #224] ; 80059f4 8005910: e3c13102 bic r3, r1, #-2147483648 ; 0x80000000 8005914: e1530002 cmp r3, r2 8005918: e24dd01c sub sp, sp, #28 800591c: e1a04000 mov r4, r0 8005920: e1a05001 mov r5, r1 8005924: da00001d ble 80059a0 8005928: e59f20c8 ldr r2, [pc, #200] ; 80059f8 800592c: e1530002 cmp r3, r2 8005930: da000009 ble 800595c 8005934: e1a02000 mov r2, r0 8005938: e1a03001 mov r3, r1 800593c: fa000bcd blx 8008878 <__aeabi_dsub> 8005940: e1a03000 mov r3, r0 8005944: e1a02001 mov r2, r1 8005948: e1a00003 mov r0, r3 800594c: e1a01002 mov r1, r2 8005950: e28dd01c add sp, sp, #28 8005954: e8bd4030 pop {r4, r5, lr} 8005958: e12fff1e bx lr 800595c: e28d2008 add r2, sp, #8 8005960: eb0003be bl 8006860 <__ieee754_rem_pio2> 8005964: e200c003 and ip, r0, #3 8005968: e35c0001 cmp ip, #1 800596c: e28d1008 add r1, sp, #8 8005970: e8910003 ldm r1, {r0, r1} 8005974: e28d3010 add r3, sp, #16 8005978: e893000c ldm r3, {r2, r3} 800597c: 0a000011 beq 80059c8 8005980: e35c0002 cmp ip, #2 8005984: 0a00000b beq 80059b8 8005988: e35c0000 cmp ip, #0 800598c: 1a000012 bne 80059dc 8005990: eb0005d8 bl 80070f8 <__kernel_cos> 8005994: e1a03000 mov r3, r0 8005998: e1a02001 mov r2, r1 800599c: eaffffe9 b 8005948 80059a0: e3a02000 mov r2, #0 80059a4: e3a03000 mov r3, #0 80059a8: eb0005d2 bl 80070f8 <__kernel_cos> 80059ac: e1a03000 mov r3, r0 80059b0: e1a02001 mov r2, r1 80059b4: eaffffe3 b 8005948 80059b8: eb0005ce bl 80070f8 <__kernel_cos> 80059bc: e1a03000 mov r3, r0 80059c0: e2812102 add r2, r1, #-2147483648 ; 0x80000000 80059c4: eaffffdf b 8005948 80059c8: e58dc000 str ip, [sp] 80059cc: eb00097b bl 8007fc0 <__kernel_sin> 80059d0: e1a03000 mov r3, r0 80059d4: e2812102 add r2, r1, #-2147483648 ; 0x80000000 80059d8: eaffffda b 8005948 80059dc: e3a0c001 mov ip, #1 80059e0: e58dc000 str ip, [sp] 80059e4: eb000975 bl 8007fc0 <__kernel_sin> 80059e8: e1a03000 mov r3, r0 80059ec: e1a02001 mov r2, r1 80059f0: eaffffd4 b 8005948 80059f4: 3fe921fb .word 0x3fe921fb 80059f8: 7fefffff .word 0x7fefffff 80059fc: 00000000 .word 0x00000000 08005a00 : 8005a00: e92d4ff0 push {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8005a04: e1a06081 lsl r6, r1, #1 8005a08: e1a06aa6 lsr r6, r6, #21 8005a0c: e2464fff sub r4, r6, #1020 ; 0x3fc 8005a10: e2444003 sub r4, r4, #3 8005a14: e3540013 cmp r4, #19 8005a18: e24dd00c sub sp, sp, #12 8005a1c: e1a0a000 mov sl, r0 8005a20: e1a0b001 mov fp, r1 8005a24: e1a08000 mov r8, r0 8005a28: e1a09001 mov r9, r1 8005a2c: e1a05001 mov r5, r1 8005a30: e1a07000 mov r7, r0 8005a34: ca000018 bgt 8005a9c 8005a38: e3540000 cmp r4, #0 8005a3c: ba000034 blt 8005b14 8005a40: e59f3168 ldr r3, [pc, #360] ; 8005bb0 8005a44: e1a06453 asr r6, r3, r4 8005a48: e0065001 and r5, r6, r1 8005a4c: e1955000 orrs r5, r5, r0 8005a50: 0a00000c beq 8005a88 8005a54: e28f3f53 add r3, pc, #332 ; 0x14c 8005a58: e893000c ldm r3, {r2, r3} 8005a5c: e58d1004 str r1, [sp, #4] 8005a60: fa000b85 blx 800887c <__adddf3> 8005a64: e3a02000 mov r2, #0 8005a68: e3a03000 mov r3, #0 8005a6c: fa000da3 blx 8009100 <__aeabi_dcmpgt> 8005a70: e3500000 cmp r0, #0 8005a74: e59dc004 ldr ip, [sp, #4] 8005a78: 1a000038 bne 8005b60 8005a7c: e1a0c009 mov ip, r9 8005a80: e1a0b00c mov fp, ip 8005a84: e1a0a008 mov sl, r8 8005a88: e1a0000a mov r0, sl 8005a8c: e1a0100b mov r1, fp 8005a90: e28dd00c add sp, sp, #12 8005a94: e8bd4ff0 pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8005a98: e12fff1e bx lr 8005a9c: e3540033 cmp r4, #51 ; 0x33 8005aa0: da000007 ble 8005ac4 8005aa4: e3540b01 cmp r4, #1024 ; 0x400 8005aa8: 1afffff6 bne 8005a88 8005aac: e1a02000 mov r2, r0 8005ab0: e1a03001 mov r3, r1 8005ab4: fa000b70 blx 800887c <__adddf3> 8005ab8: e1a0a000 mov sl, r0 8005abc: e1a0b001 mov fp, r1 8005ac0: eafffff0 b 8005a88 8005ac4: e2463e41 sub r3, r6, #1040 ; 0x410 8005ac8: e2433003 sub r3, r3, #3 8005acc: e3e02000 mvn r2, #0 8005ad0: e1a05332 lsr r5, r2, r3 8005ad4: e1150000 tst r5, r0 8005ad8: 0affffea beq 8005a88 8005adc: e28f30c4 add r3, pc, #196 ; 0xc4 8005ae0: e893000c ldm r3, {r2, r3} 8005ae4: e58d1004 str r1, [sp, #4] 8005ae8: fa000b63 blx 800887c <__adddf3> 8005aec: e3a02000 mov r2, #0 8005af0: e3a03000 mov r3, #0 8005af4: fa000d81 blx 8009100 <__aeabi_dcmpgt> 8005af8: e3500000 cmp r0, #0 8005afc: e59dc004 ldr ip, [sp, #4] 8005b00: 0affffdd beq 8005a7c 8005b04: e35c0000 cmp ip, #0 8005b08: ba00001a blt 8005b78 8005b0c: e1c88005 bic r8, r8, r5 8005b10: eaffffda b 8005a80 8005b14: e28f308c add r3, pc, #140 ; 0x8c 8005b18: e893000c ldm r3, {r2, r3} 8005b1c: fa000b56 blx 800887c <__adddf3> 8005b20: e3a02000 mov r2, #0 8005b24: e3a03000 mov r3, #0 8005b28: fa000d74 blx 8009100 <__aeabi_dcmpgt> 8005b2c: e3500000 cmp r0, #0 8005b30: 0affffd1 beq 8005a7c 8005b34: e35b0000 cmp fp, #0 8005b38: a3a08000 movge r8, #0 8005b3c: a1a0c008 movge ip, r8 8005b40: aaffffce bge 8005a80 8005b44: e3cb8102 bic r8, fp, #-2147483648 ; 0x80000000 8005b48: e188800a orr r8, r8, sl 8005b4c: e59fc060 ldr ip, [pc, #96] ; 8005bb4 8005b50: e3580000 cmp r8, #0 8005b54: 01a0c00b moveq ip, fp 8005b58: 13a08000 movne r8, #0 8005b5c: eaffffc7 b 8005a80 8005b60: e35c0000 cmp ip, #0 8005b64: b3a03601 movlt r3, #1048576 ; 0x100000 8005b68: b08cc453 addlt ip, ip, r3, asr r4 8005b6c: e3a08000 mov r8, #0 8005b70: e1ccc006 bic ip, ip, r6 8005b74: eaffffc1 b 8005a80 8005b78: e3540014 cmp r4, #20 8005b7c: 0a000005 beq 8005b98 8005b80: e2663e43 rsb r3, r6, #1072 ; 0x430 8005b84: e2833003 add r3, r3, #3 8005b88: e3a08001 mov r8, #1 8005b8c: e08a8318 add r8, sl, r8, lsl r3 8005b90: e15a0008 cmp sl, r8 8005b94: 9affffdc bls 8005b0c 8005b98: e28cc001 add ip, ip, #1 8005b9c: e1c88005 bic r8, r8, r5 8005ba0: eaffffb6 b 8005a80 8005ba4: e1a00000 nop ; (mov r0, r0) 8005ba8: 8800759c .word 0x8800759c 8005bac: 7e37e43c .word 0x7e37e43c 8005bb0: 000fffff .word 0x000fffff 8005bb4: bff00000 .word 0xbff00000 08005bb8 : 8005bb8: e59fc0c4 ldr ip, [pc, #196] ; 8005c84 8005bbc: e92d4038 push {r3, r4, r5, lr} 8005bc0: e2514000 subs r4, r1, #0 8005bc4: e004c00c and ip, r4, ip 8005bc8: e1a0ca2c lsr ip, ip, #20 8005bcc: e24ccfff sub ip, ip, #1020 ; 0x3fc 8005bd0: e3c454ff bic r5, r4, #-16777216 ; 0xff000000 8005bd4: e24c3003 sub r3, ip, #3 8005bd8: a3a04001 movge r4, #1 8005bdc: b3e04000 mvnlt r4, #0 8005be0: e3c5560f bic r5, r5, #15728640 ; 0xf00000 8005be4: e3530013 cmp r3, #19 8005be8: e3855601 orr r5, r5, #1048576 ; 0x100000 8005bec: ca000009 bgt 8005c18 8005bf0: e3530000 cmp r3, #0 8005bf4: ba00001f blt 8005c78 8005bf8: e3a02702 mov r2, #524288 ; 0x80000 8005bfc: e0855352 add r5, r5, r2, asr r3 8005c00: e2633014 rsb r3, r3, #20 8005c04: e1a05335 lsr r5, r5, r3 8005c08: e0040495 mul r4, r5, r4 8005c0c: e1a00004 mov r0, r4 8005c10: e8bd4038 pop {r3, r4, r5, lr} 8005c14: e12fff1e bx lr 8005c18: e353001e cmp r3, #30 8005c1c: 8a000006 bhi 8005c3c 8005c20: e3530033 cmp r3, #51 ; 0x33 8005c24: da000007 ble 8005c48 8005c28: e24c3037 sub r3, ip, #55 ; 0x37 8005c2c: e1a02310 lsl r2, r0, r3 8005c30: e24cc017 sub ip, ip, #23 8005c34: e1825c15 orr r5, r2, r5, lsl ip 8005c38: eafffff2 b 8005c08 8005c3c: fa000d34 blx 8009114 <__aeabi_d2iz> 8005c40: e1a04000 mov r4, r0 8005c44: eafffff0 b 8005c0c 8005c48: e24cc017 sub ip, ip, #23 8005c4c: e3a01102 mov r1, #-2147483648 ; 0x80000000 8005c50: e0801c31 add r1, r0, r1, lsr ip 8005c54: e2633034 rsb r3, r3, #52 ; 0x34 8005c58: e1500001 cmp r0, r1 8005c5c: 82855001 addhi r5, r5, #1 8005c60: e3530020 cmp r3, #32 8005c64: e1a05c15 lsl r5, r5, ip 8005c68: 11a03331 lsrne r3, r1, r3 8005c6c: 03a03000 moveq r3, #0 8005c70: e1835005 orr r5, r3, r5 8005c74: eaffffe3 b 8005c08 8005c78: e3730001 cmn r3, #1 8005c7c: 13a04000 movne r4, #0 8005c80: eaffffe1 b 8005c0c 8005c84: 7ff00000 .word 0x7ff00000 08005c88 : 8005c88: e59f20ec ldr r2, [pc, #236] ; 8005d7c 8005c8c: e0012002 and r2, r1, r2 8005c90: e1a02a42 asr r2, r2, #20 8005c94: e242cfff sub ip, r2, #1020 ; 0x3fc 8005c98: e24cc003 sub ip, ip, #3 8005c9c: e35c0013 cmp ip, #19 8005ca0: e92d40f8 push {r3, r4, r5, r6, r7, lr} 8005ca4: e1a04000 mov r4, r0 8005ca8: e1a05001 mov r5, r1 8005cac: e1a06000 mov r6, r0 8005cb0: e1a07001 mov r7, r1 8005cb4: e1a03001 mov r3, r1 8005cb8: ca000010 bgt 8005d00 8005cbc: e35c0000 cmp ip, #0 8005cc0: ba000026 blt 8005d60 8005cc4: e59f10b4 ldr r1, [pc, #180] ; 8005d80 8005cc8: e1a01c51 asr r1, r1, ip 8005ccc: e0012005 and r2, r1, r5 8005cd0: e1922000 orrs r2, r2, r0 8005cd4: 0a000005 beq 8005cf0 8005cd8: e3a02702 mov r2, #524288 ; 0x80000 8005cdc: e0853c52 add r3, r5, r2, asr ip 8005ce0: e3a02000 mov r2, #0 8005ce4: e1c33001 bic r3, r3, r1 8005ce8: e1a05003 mov r5, r3 8005cec: e1a04002 mov r4, r2 8005cf0: e1a00004 mov r0, r4 8005cf4: e1a01005 mov r1, r5 8005cf8: e8bd40f8 pop {r3, r4, r5, r6, r7, lr} 8005cfc: e12fff1e bx lr 8005d00: e35c0033 cmp ip, #51 ; 0x33 8005d04: da000007 ble 8005d28 8005d08: e35c0b01 cmp ip, #1024 ; 0x400 8005d0c: 1afffff7 bne 8005cf0 8005d10: e1a02000 mov r2, r0 8005d14: e1a03001 mov r3, r1 8005d18: fa000ad7 blx 800887c <__adddf3> 8005d1c: e1a04000 mov r4, r0 8005d20: e1a05001 mov r5, r1 8005d24: eafffff1 b 8005cf0 8005d28: e2421e41 sub r1, r2, #1040 ; 0x410 8005d2c: e2411003 sub r1, r1, #3 8005d30: e3e00000 mvn r0, #0 8005d34: e1a01130 lsr r1, r0, r1 8005d38: e1110004 tst r1, r4 8005d3c: 0affffeb beq 8005cf0 8005d40: e2622e43 rsb r2, r2, #1072 ; 0x430 8005d44: e3a00001 mov r0, #1 8005d48: e2822002 add r2, r2, #2 8005d4c: e0842210 add r2, r4, r0, lsl r2 8005d50: e1540002 cmp r4, r2 8005d54: 80853000 addhi r3, r5, r0 8005d58: e1c22001 bic r2, r2, r1 8005d5c: eaffffe1 b 8005ce8 8005d60: e37c0001 cmn ip, #1 8005d64: e2013102 and r3, r1, #-2147483648 ; 0x80000000 8005d68: 038335ff orreq r3, r3, #1069547520 ; 0x3fc00000 8005d6c: 03833603 orreq r3, r3, #3145728 ; 0x300000 8005d70: 03a02000 moveq r2, #0 8005d74: 13a02000 movne r2, #0 8005d78: eaffffda b 8005ce8 8005d7c: 7ff00000 .word 0x7ff00000 8005d80: 000fffff .word 0x000fffff 08005d84 : 8005d84: e92d4030 push {r4, r5, lr} 8005d88: e59f210c ldr r2, [pc, #268] ; 8005e9c 8005d8c: e3c13102 bic r3, r1, #-2147483648 ; 0x80000000 8005d90: e1530002 cmp r3, r2 8005d94: e24dd01c sub sp, sp, #28 8005d98: e1a04000 mov r4, r0 8005d9c: e1a05001 mov r5, r1 8005da0: da00001f ble 8005e24 8005da4: e59f20f4 ldr r2, [pc, #244] ; 8005ea0 8005da8: e1530002 cmp r3, r2 8005dac: da000009 ble 8005dd8 8005db0: e1a02000 mov r2, r0 8005db4: e1a03001 mov r3, r1 8005db8: fa000aae blx 8008878 <__aeabi_dsub> 8005dbc: e1a03000 mov r3, r0 8005dc0: e1a02001 mov r2, r1 8005dc4: e1a00003 mov r0, r3 8005dc8: e1a01002 mov r1, r2 8005dcc: e28dd01c add sp, sp, #28 8005dd0: e8bd4030 pop {r4, r5, lr} 8005dd4: e12fff1e bx lr 8005dd8: e28d2008 add r2, sp, #8 8005ddc: eb00029f bl 8006860 <__ieee754_rem_pio2> 8005de0: e2000003 and r0, r0, #3 8005de4: e3500001 cmp r0, #1 8005de8: 0a00001f beq 8005e6c 8005dec: e3500002 cmp r0, #2 8005df0: 0a000013 beq 8005e44 8005df4: e3500000 cmp r0, #0 8005df8: e28d3010 add r3, sp, #16 8005dfc: e893000c ldm r3, {r2, r3} 8005e00: e28d1008 add r1, sp, #8 8005e04: e8910003 ldm r1, {r0, r1} 8005e08: 1a00001f bne 8005e8c 8005e0c: e3a0c001 mov ip, #1 8005e10: e58dc000 str ip, [sp] 8005e14: eb000869 bl 8007fc0 <__kernel_sin> 8005e18: e1a03000 mov r3, r0 8005e1c: e1a02001 mov r2, r1 8005e20: eaffffe7 b 8005dc4 8005e24: e3a02000 mov r2, #0 8005e28: e3a03000 mov r3, #0 8005e2c: e3a0c000 mov ip, #0 8005e30: e58dc000 str ip, [sp] 8005e34: eb000861 bl 8007fc0 <__kernel_sin> 8005e38: e1a03000 mov r3, r0 8005e3c: e1a02001 mov r2, r1 8005e40: eaffffdf b 8005dc4 8005e44: e28d3010 add r3, sp, #16 8005e48: e893000c ldm r3, {r2, r3} 8005e4c: e3a0c001 mov ip, #1 8005e50: e28d1008 add r1, sp, #8 8005e54: e8910003 ldm r1, {r0, r1} 8005e58: e58dc000 str ip, [sp] 8005e5c: eb000857 bl 8007fc0 <__kernel_sin> 8005e60: e1a03000 mov r3, r0 8005e64: e2812102 add r2, r1, #-2147483648 ; 0x80000000 8005e68: eaffffd5 b 8005dc4 8005e6c: e28d3010 add r3, sp, #16 8005e70: e893000c ldm r3, {r2, r3} 8005e74: e28d1008 add r1, sp, #8 8005e78: e8910003 ldm r1, {r0, r1} 8005e7c: eb00049d bl 80070f8 <__kernel_cos> 8005e80: e1a03000 mov r3, r0 8005e84: e1a02001 mov r2, r1 8005e88: eaffffcd b 8005dc4 8005e8c: eb000499 bl 80070f8 <__kernel_cos> 8005e90: e1a03000 mov r3, r0 8005e94: e2812102 add r2, r1, #-2147483648 ; 0x80000000 8005e98: eaffffc9 b 8005dc4 8005e9c: 3fe921fb .word 0x3fe921fb 8005ea0: 7fefffff .word 0x7fefffff 08005ea4 : 8005ea4: e92d4370 push {r4, r5, r6, r8, r9, lr} 8005ea8: e59f5098 ldr r5, [pc, #152] ; 8005f48 8005eac: e0015005 and r5, r1, r5 8005eb0: e1a05a45 asr r5, r5, #20 8005eb4: e245cfff sub ip, r5, #1020 ; 0x3fc 8005eb8: e24cc003 sub ip, ip, #3 8005ebc: e35c0013 cmp ip, #19 8005ec0: e1a02000 mov r2, r0 8005ec4: e1a03001 mov r3, r1 8005ec8: e1a08000 mov r8, r0 8005ecc: e1a09001 mov r9, r1 8005ed0: e1a04001 mov r4, r1 8005ed4: e1a06000 mov r6, r0 8005ed8: ca00000c bgt 8005f10 8005edc: e35c0000 cmp ip, #0 8005ee0: a59f3064 ldrge r3, [pc, #100] ; 8005f4c 8005ee4: a1c9cc53 bicge ip, r9, r3, asr ip 8005ee8: e2011102 and r1, r1, #-2147483648 ; 0x80000000 8005eec: b3a03000 movlt r3, #0 8005ef0: a3a03000 movge r3, #0 8005ef4: b1a03001 movlt r3, r1 8005ef8: a18c3001 orrge r3, ip, r1 8005efc: e3a02000 mov r2, #0 8005f00: e1a00002 mov r0, r2 8005f04: e1a01003 mov r1, r3 8005f08: e8bd4370 pop {r4, r5, r6, r8, r9, lr} 8005f0c: e12fff1e bx lr 8005f10: e35c0033 cmp ip, #51 ; 0x33 8005f14: da000005 ble 8005f30 8005f18: e35c0b01 cmp ip, #1024 ; 0x400 8005f1c: 1afffff7 bne 8005f00 8005f20: fa000a55 blx 800887c <__adddf3> 8005f24: e1a02000 mov r2, r0 8005f28: e1a03001 mov r3, r1 8005f2c: eafffff3 b 8005f00 8005f30: e2455e41 sub r5, r5, #1040 ; 0x410 8005f34: e1a03001 mov r3, r1 8005f38: e2455003 sub r5, r5, #3 8005f3c: e3e01000 mvn r1, #0 8005f40: e1c02531 bic r2, r0, r1, lsr r5 8005f44: eaffffed b 8005f00 8005f48: 7ff00000 .word 0x7ff00000 8005f4c: 000fffff .word 0x000fffff 08005f50 : 8005f50: e92d4008 push {r3, lr} 8005f54: eb000095 bl 80061b0 <__ieee754_atan2> 8005f58: e8bd4008 pop {r3, lr} 8005f5c: e12fff1e bx lr 08005f60 : 8005f60: e92d4ff0 push {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8005f64: e24dd02c sub sp, sp, #44 ; 0x2c 8005f68: e1a0b003 mov fp, r3 8005f6c: e1a08000 mov r8, r0 8005f70: e1a09001 mov r9, r1 8005f74: e1a0a002 mov sl, r2 8005f78: eb000144 bl 8006490 <__ieee754_hypot> 8005f7c: e59f40f8 ldr r4, [pc, #248] ; 800607c 8005f80: e1d430d0 ldrsb r3, [r4] 8005f84: e3730001 cmn r3, #1 8005f88: e1a06000 mov r6, r0 8005f8c: e1a07001 mov r7, r1 8005f90: 0a000002 beq 8005fa0 8005f94: eb0009bb bl 8008688 8005f98: e2505000 subs r5, r0, #0 8005f9c: 0a000004 beq 8005fb4 8005fa0: e1a00006 mov r0, r6 8005fa4: e1a01007 mov r1, r7 8005fa8: e28dd02c add sp, sp, #44 ; 0x2c 8005fac: e8bd4ff0 pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8005fb0: e12fff1e bx lr 8005fb4: e1a00008 mov r0, r8 8005fb8: e1a01009 mov r1, r9 8005fbc: eb0009b1 bl 8008688 8005fc0: e3500000 cmp r0, #0 8005fc4: 0afffff5 beq 8005fa0 8005fc8: e1a0000a mov r0, sl 8005fcc: e1a0100b mov r1, fp 8005fd0: eb0009ac bl 8008688 8005fd4: e3500000 cmp r0, #0 8005fd8: 0afffff0 beq 8005fa0 8005fdc: e3a02003 mov r2, #3 8005fe0: e5d43000 ldrb r3, [r4] 8005fe4: e58d2000 str r2, [sp] 8005fe8: e59f2090 ldr r2, [pc, #144] ; 8006080 8005fec: e3530000 cmp r3, #0 8005ff0: e58d2004 str r2, [sp, #4] 8005ff4: e58d5020 str r5, [sp, #32] 8005ff8: e58d8008 str r8, [sp, #8] 8005ffc: e58d900c str r9, [sp, #12] 8006000: e58da010 str sl, [sp, #16] 8006004: e58db014 str fp, [sp, #20] 8006008: 0a00000e beq 8006048 800600c: e3530002 cmp r3, #2 8006010: e59f306c ldr r3, [pc, #108] ; 8006084 8006014: e3a02000 mov r2, #0 8006018: e58d2018 str r2, [sp, #24] 800601c: e58d301c str r3, [sp, #28] 8006020: 1a00000c bne 8006058 8006024: ebfffdac bl 80056dc <__errno> 8006028: e3a03022 mov r3, #34 ; 0x22 800602c: e5803000 str r3, [r0] 8006030: e59d3020 ldr r3, [sp, #32] 8006034: e3530000 cmp r3, #0 8006038: 1a00000b bne 800606c 800603c: e28d7018 add r7, sp, #24 8006040: e89700c0 ldm r7, {r6, r7} 8006044: eaffffd5 b 8005fa0 8006048: e59f3038 ldr r3, [pc, #56] ; 8006088 800604c: e3a0220e mov r2, #-536870912 ; 0xe0000000 8006050: e58d2018 str r2, [sp, #24] 8006054: e58d301c str r3, [sp, #28] 8006058: e1a0000d mov r0, sp 800605c: eb00098e bl 800869c 8006060: e3500000 cmp r0, #0 8006064: 1afffff1 bne 8006030 8006068: eaffffed b 8006024 800606c: ebfffd9a bl 80056dc <__errno> 8006070: e59d3020 ldr r3, [sp, #32] 8006074: e5803000 str r3, [r0] 8006078: eaffffef b 800603c 800607c: 2000043c .word 0x2000043c 8006080: 0800adac .word 0x0800adac 8006084: 7ff00000 .word 0x7ff00000 8006088: 47efffff .word 0x47efffff 0800608c : 800608c: e92d4fd0 push {r4, r6, r7, r8, r9, sl, fp, lr} 8006090: e24dd028 sub sp, sp, #40 ; 0x28 8006094: e1a06000 mov r6, r0 8006098: e1a07001 mov r7, r1 800609c: eb000387 bl 8006ec0 <__ieee754_sqrt> 80060a0: e59f4100 ldr r4, [pc, #256] ; 80061a8 80060a4: e1d430d0 ldrsb r3, [r4] 80060a8: e3730001 cmn r3, #1 80060ac: e1a08000 mov r8, r0 80060b0: e1a09001 mov r9, r1 80060b4: 0a00002b beq 8006168 80060b8: e1a00006 mov r0, r6 80060bc: e1a01007 mov r1, r7 80060c0: ebfffd89 bl 80056ec <__fpclassifyd> 80060c4: e3500000 cmp r0, #0 80060c8: 0a000026 beq 8006168 80060cc: e3a0a000 mov sl, #0 80060d0: e3a0b000 mov fp, #0 80060d4: e1a00006 mov r0, r6 80060d8: e1a01007 mov r1, r7 80060dc: e1a0200a mov r2, sl 80060e0: e1a0300b mov r3, fp 80060e4: fa000bf6 blx 80090c4 <__aeabi_dcmplt> 80060e8: e3500000 cmp r0, #0 80060ec: 0a00001d beq 8006168 80060f0: e3a03001 mov r3, #1 80060f4: e5d44000 ldrb r4, [r4] 80060f8: e58d3000 str r3, [sp] 80060fc: e59f30a8 ldr r3, [pc, #168] ; 80061ac 8006100: e3540000 cmp r4, #0 8006104: e58d3004 str r3, [sp, #4] 8006108: e3a03000 mov r3, #0 800610c: e58d3020 str r3, [sp, #32] 8006110: e58d6010 str r6, [sp, #16] 8006114: e58d7014 str r7, [sp, #20] 8006118: e58d6008 str r6, [sp, #8] 800611c: e58d700c str r7, [sp, #12] 8006120: 0a000015 beq 800617c 8006124: e1a0000a mov r0, sl 8006128: e1a0100b mov r1, fp 800612c: e1a0200a mov r2, sl 8006130: e1a0300b mov r3, fp 8006134: fa000b3e blx 8008e34 <__aeabi_ddiv> 8006138: e3540002 cmp r4, #2 800613c: e58d0018 str r0, [sp, #24] 8006140: e58d101c str r1, [sp, #28] 8006144: 1a00000e bne 8006184 8006148: ebfffd63 bl 80056dc <__errno> 800614c: e3a03021 mov r3, #33 ; 0x21 8006150: e5803000 str r3, [r0] 8006154: e59d3020 ldr r3, [sp, #32] 8006158: e3530000 cmp r3, #0 800615c: 1a00000d bne 8006198 8006160: e28d9018 add r9, sp, #24 8006164: e8990300 ldm r9, {r8, r9} 8006168: e1a00008 mov r0, r8 800616c: e1a01009 mov r1, r9 8006170: e28dd028 add sp, sp, #40 ; 0x28 8006174: e8bd4fd0 pop {r4, r6, r7, r8, r9, sl, fp, lr} 8006178: e12fff1e bx lr 800617c: e58da018 str sl, [sp, #24] 8006180: e58db01c str fp, [sp, #28] 8006184: e1a0000d mov r0, sp 8006188: eb000943 bl 800869c 800618c: e3500000 cmp r0, #0 8006190: 1affffef bne 8006154 8006194: eaffffeb b 8006148 8006198: ebfffd4f bl 80056dc <__errno> 800619c: e59d3020 ldr r3, [sp, #32] 80061a0: e5803000 str r3, [r0] 80061a4: eaffffed b 8006160 80061a8: 2000043c .word 0x2000043c 80061ac: 0800adb4 .word 0x0800adb4 080061b0 <__ieee754_atan2>: 80061b0: e92d4ff0 push {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80061b4: e24dd00c sub sp, sp, #12 80061b8: e1a05003 mov r5, r3 80061bc: e88d000c stm sp, {r2, r3} 80061c0: e1a03002 mov r3, r2 80061c4: e2622000 rsb r2, r2, #0 80061c8: e3c56102 bic r6, r5, #-2147483648 ; 0x80000000 80061cc: e1a04005 mov r4, r5 80061d0: e1822003 orr r2, r2, r3 80061d4: e59f52ac ldr r5, [pc, #684] ; 8006488 <__ieee754_atan2+0x2d8> 80061d8: e1862fa2 orr r2, r6, r2, lsr #31 80061dc: e1520005 cmp r2, r5 80061e0: e1a08000 mov r8, r0 80061e4: e1a09001 mov r9, r1 80061e8: e1a0a000 mov sl, r0 80061ec: e1a0b001 mov fp, r1 80061f0: e1a02000 mov r2, r0 80061f4: 8a000036 bhi 80062d4 <__ieee754_atan2+0x124> 80061f8: e260a000 rsb sl, r0, #0 80061fc: e3c17102 bic r7, r1, #-2147483648 ; 0x80000000 8006200: e18ac000 orr ip, sl, r0 8006204: e187cfac orr ip, r7, ip, lsr #31 8006208: e15c0005 cmp ip, r5 800620c: e1a05001 mov r5, r1 8006210: 8a00002f bhi 80062d4 <__ieee754_atan2+0x124> 8006214: e284c103 add ip, r4, #-1073741824 ; 0xc0000000 8006218: e28cc601 add ip, ip, #1048576 ; 0x100000 800621c: e19cc003 orrs ip, ip, r3 8006220: 0a000042 beq 8006330 <__ieee754_atan2+0x180> 8006224: e1a01f44 asr r1, r4, #30 8006228: e2011002 and r1, r1, #2 800622c: e1972002 orrs r2, r7, r2 8006230: e181afa9 orr sl, r1, r9, lsr #31 8006234: 0a000031 beq 8006300 <__ieee754_atan2+0x150> 8006238: e1963003 orrs r3, r6, r3 800623c: 0a000036 beq 800631c <__ieee754_atan2+0x16c> 8006240: e59f3240 ldr r3, [pc, #576] ; 8006488 <__ieee754_atan2+0x2d8> 8006244: e1560003 cmp r6, r3 8006248: 0a000045 beq 8006364 <__ieee754_atan2+0x1b4> 800624c: e59f3234 ldr r3, [pc, #564] ; 8006488 <__ieee754_atan2+0x2d8> 8006250: e1570003 cmp r7, r3 8006254: 0a000030 beq 800631c <__ieee754_atan2+0x16c> 8006258: e0666007 rsb r6, r6, r7 800625c: e1a06a46 asr r6, r6, #20 8006260: e356003c cmp r6, #60 ; 0x3c 8006264: ca00003b bgt 8006358 <__ieee754_atan2+0x1a8> 8006268: e376003c cmn r6, #60 ; 0x3c 800626c: a3a06000 movge r6, #0 8006270: b3a06001 movlt r6, #1 8006274: e0166fa4 ands r6, r6, r4, lsr #31 8006278: 13a00000 movne r0, #0 800627c: 13a01000 movne r1, #0 8006280: 0a000054 beq 80063d8 <__ieee754_atan2+0x228> 8006284: e35a0001 cmp sl, #1 8006288: 01a03001 moveq r3, r1 800628c: 01a08000 moveq r8, r0 8006290: 02839102 addeq r9, r3, #-2147483648 ; 0x80000000 8006294: 0a000014 beq 80062ec <__ieee754_atan2+0x13c> 8006298: e35a0002 cmp sl, #2 800629c: 0a000042 beq 80063ac <__ieee754_atan2+0x1fc> 80062a0: e35a0000 cmp sl, #0 80062a4: 01a08000 moveq r8, r0 80062a8: 01a09001 moveq r9, r1 80062ac: 0a00000e beq 80062ec <__ieee754_atan2+0x13c> 80062b0: e28f3f62 add r3, pc, #392 ; 0x188 80062b4: e893000c ldm r3, {r2, r3} 80062b8: fa00096e blx 8008878 <__aeabi_dsub> 80062bc: e28f3f61 add r3, pc, #388 ; 0x184 80062c0: e893000c ldm r3, {r2, r3} 80062c4: fa00096b blx 8008878 <__aeabi_dsub> 80062c8: e1a08000 mov r8, r0 80062cc: e1a09001 mov r9, r1 80062d0: ea000005 b 80062ec <__ieee754_atan2+0x13c> 80062d4: e1a00008 mov r0, r8 80062d8: e1a01009 mov r1, r9 80062dc: e89d000c ldm sp, {r2, r3} 80062e0: fa000965 blx 800887c <__adddf3> 80062e4: e1a08000 mov r8, r0 80062e8: e1a09001 mov r9, r1 80062ec: e1a00008 mov r0, r8 80062f0: e1a01009 mov r1, r9 80062f4: e28dd00c add sp, sp, #12 80062f8: e8bd4ff0 pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80062fc: e12fff1e bx lr 8006300: e35a0003 cmp sl, #3 8006304: 979ff10a ldrls pc, [pc, sl, lsl #2] 8006308: eaffffca b 8006238 <__ieee754_atan2+0x88> 800630c: 080062ec .word 0x080062ec 8006310: 080062ec .word 0x080062ec 8006314: 0800634c .word 0x0800634c 8006318: 08006340 .word 0x08006340 800631c: e3550000 cmp r5, #0 8006320: ba00001e blt 80063a0 <__ieee754_atan2+0x1f0> 8006324: e28f9f49 add r9, pc, #292 ; 0x124 8006328: e8990300 ldm r9, {r8, r9} 800632c: eaffffee b 80062ec <__ieee754_atan2+0x13c> 8006330: eb0007aa bl 80081e0 8006334: e1a08000 mov r8, r0 8006338: e1a09001 mov r9, r1 800633c: eaffffea b 80062ec <__ieee754_atan2+0x13c> 8006340: e28f9e11 add r9, pc, #272 ; 0x110 8006344: e8990300 ldm r9, {r8, r9} 8006348: eaffffe7 b 80062ec <__ieee754_atan2+0x13c> 800634c: e28f90f4 add r9, pc, #244 ; 0xf4 8006350: e8990300 ldm r9, {r8, r9} 8006354: eaffffe4 b 80062ec <__ieee754_atan2+0x13c> 8006358: e28f10f0 add r1, pc, #240 ; 0xf0 800635c: e8910003 ldm r1, {r0, r1} 8006360: eaffffc7 b 8006284 <__ieee754_atan2+0xd4> 8006364: e1570006 cmp r7, r6 8006368: 0a000021 beq 80063f4 <__ieee754_atan2+0x244> 800636c: e35a0003 cmp sl, #3 8006370: 979ff10a ldrls pc, [pc, sl, lsl #2] 8006374: eaffffb4 b 800624c <__ieee754_atan2+0x9c> 8006378: 08006394 .word 0x08006394 800637c: 08006388 .word 0x08006388 8006380: 0800634c .word 0x0800634c 8006384: 08006340 .word 0x08006340 8006388: e3a08000 mov r8, #0 800638c: e3a09102 mov r9, #-2147483648 ; 0x80000000 8006390: eaffffd5 b 80062ec <__ieee754_atan2+0x13c> 8006394: e3a08000 mov r8, #0 8006398: e3a09000 mov r9, #0 800639c: eaffffd2 b 80062ec <__ieee754_atan2+0x13c> 80063a0: e28f90b8 add r9, pc, #184 ; 0xb8 80063a4: e8990300 ldm r9, {r8, r9} 80063a8: eaffffcf b 80062ec <__ieee754_atan2+0x13c> 80063ac: e28f308c add r3, pc, #140 ; 0x8c 80063b0: e893000c ldm r3, {r2, r3} 80063b4: fa00092f blx 8008878 <__aeabi_dsub> 80063b8: e1a02000 mov r2, r0 80063bc: e1a03001 mov r3, r1 80063c0: e28f1080 add r1, pc, #128 ; 0x80 80063c4: e8910003 ldm r1, {r0, r1} 80063c8: fa00092a blx 8008878 <__aeabi_dsub> 80063cc: e1a08000 mov r8, r0 80063d0: e1a09001 mov r9, r1 80063d4: eaffffc4 b 80062ec <__ieee754_atan2+0x13c> 80063d8: e89d000c ldm sp, {r2, r3} 80063dc: e1a00008 mov r0, r8 80063e0: e1a01009 mov r1, r9 80063e4: fa000a92 blx 8008e34 <__aeabi_ddiv> 80063e8: eb0008a4 bl 8008680 80063ec: eb00077b bl 80081e0 80063f0: eaffffa3 b 8006284 <__ieee754_atan2+0xd4> 80063f4: e35a0003 cmp sl, #3 80063f8: 979ff10a ldrls pc, [pc, sl, lsl #2] 80063fc: eaffffc6 b 800631c <__ieee754_atan2+0x16c> 8006400: 08006434 .word 0x08006434 8006404: 08006428 .word 0x08006428 8006408: 0800641c .word 0x0800641c 800640c: 08006410 .word 0x08006410 8006410: e28f9050 add r9, pc, #80 ; 0x50 8006414: e8990300 ldm r9, {r8, r9} 8006418: eaffffb3 b 80062ec <__ieee754_atan2+0x13c> 800641c: e28f904c add r9, pc, #76 ; 0x4c 8006420: e8990300 ldm r9, {r8, r9} 8006424: eaffffb0 b 80062ec <__ieee754_atan2+0x13c> 8006428: e28f9048 add r9, pc, #72 ; 0x48 800642c: e8990300 ldm r9, {r8, r9} 8006430: eaffffad b 80062ec <__ieee754_atan2+0x13c> 8006434: e28f9044 add r9, pc, #68 ; 0x44 8006438: e8990300 ldm r9, {r8, r9} 800643c: eaffffaa b 80062ec <__ieee754_atan2+0x13c> 8006440: 33145c07 .word 0x33145c07 8006444: 3ca1a626 .word 0x3ca1a626 8006448: 54442d18 .word 0x54442d18 800644c: 400921fb .word 0x400921fb 8006450: 54442d18 .word 0x54442d18 8006454: 3ff921fb .word 0x3ff921fb 8006458: 54442d18 .word 0x54442d18 800645c: c00921fb .word 0xc00921fb 8006460: 54442d18 .word 0x54442d18 8006464: bff921fb .word 0xbff921fb 8006468: 7f3321d2 .word 0x7f3321d2 800646c: c002d97c .word 0xc002d97c 8006470: 7f3321d2 .word 0x7f3321d2 8006474: 4002d97c .word 0x4002d97c 8006478: 54442d18 .word 0x54442d18 800647c: bfe921fb .word 0xbfe921fb 8006480: 54442d18 .word 0x54442d18 8006484: 3fe921fb .word 0x3fe921fb 8006488: 7ff00000 .word 0x7ff00000 800648c: e1a00000 nop ; (mov r0, r0) 08006490 <__ieee754_hypot>: 8006490: e92d4ff0 push {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8006494: e3c14102 bic r4, r1, #-2147483648 ; 0x80000000 8006498: e3c35102 bic r5, r3, #-2147483648 ; 0x80000000 800649c: e1540005 cmp r4, r5 80064a0: e1a07003 mov r7, r3 80064a4: b1a03004 movlt r3, r4 80064a8: e1a08000 mov r8, r0 80064ac: b1a04005 movlt r4, r5 80064b0: a1a01007 movge r1, r7 80064b4: b1a05003 movlt r5, r3 80064b8: a1a00002 movge r0, r2 80064bc: e1a06002 mov r6, r2 80064c0: e24dd024 sub sp, sp, #36 ; 0x24 80064c4: a1a06008 movge r6, r8 80064c8: e1a09001 mov r9, r1 80064cc: e0653004 rsb r3, r5, r4 80064d0: e1a08000 mov r8, r0 80064d4: e88d0300 stm sp, {r8, r9} 80064d8: e353050f cmp r3, #62914560 ; 0x3c00000 80064dc: e1a0b006 mov fp, r6 80064e0: e1a09004 mov r9, r4 80064e4: e59d7000 ldr r7, [sp] 80064e8: e1a06005 mov r6, r5 80064ec: ca000080 bgt 80066f4 <__ieee754_hypot+0x264> 80064f0: e59f3358 ldr r3, [pc, #856] ; 8006850 <__ieee754_hypot+0x3c0> 80064f4: e1540003 cmp r4, r3 80064f8: d3a08000 movle r8, #0 80064fc: d58d8000 strle r8, [sp] 8006500: ca000065 bgt 800669c <__ieee754_hypot+0x20c> 8006504: e59f3348 ldr r3, [pc, #840] ; 8006854 <__ieee754_hypot+0x3c4> 8006508: e1550003 cmp r5, r3 800650c: ca000019 bgt 8006578 <__ieee754_hypot+0xe8> 8006510: e3550601 cmp r5, #1048576 ; 0x100000 8006514: aa0000c5 bge 8006830 <__ieee754_hypot+0x3a0> 8006518: e1a03007 mov r3, r7 800651c: e1953003 orrs r3, r5, r3 8006520: 01a01009 moveq r1, r9 8006524: 0a000058 beq 800668c <__ieee754_hypot+0x1fc> 8006528: e59f3328 ldr r3, [pc, #808] ; 8006858 <__ieee754_hypot+0x3c8> 800652c: e3a02000 mov r2, #0 8006530: e1a00007 mov r0, r7 8006534: e1a01005 mov r1, r5 8006538: e58d2008 str r2, [sp, #8] 800653c: e58d300c str r3, [sp, #12] 8006540: fa0009a6 blx 8008be0 <__aeabi_dmul> 8006544: e28d3008 add r3, sp, #8 8006548: e893000c ldm r3, {r2, r3} 800654c: e1a07000 mov r7, r0 8006550: e1a06001 mov r6, r1 8006554: e1a0000b mov r0, fp 8006558: e1a01009 mov r1, r9 800655c: fa00099f blx 8008be0 <__aeabi_dmul> 8006560: e59dc000 ldr ip, [sp] 8006564: e24c3fff sub r3, ip, #1020 ; 0x3fc 8006568: e2433002 sub r3, r3, #2 800656c: e58d3000 str r3, [sp] 8006570: e1a0b000 mov fp, r0 8006574: e1a09001 mov r9, r1 8006578: e1a02007 mov r2, r7 800657c: e1a03006 mov r3, r6 8006580: e1a0000b mov r0, fp 8006584: e1a01009 mov r1, r9 8006588: fa0008ba blx 8008878 <__aeabi_dsub> 800658c: e1a02007 mov r2, r7 8006590: e1a03006 mov r3, r6 8006594: e1a08000 mov r8, r0 8006598: e1a0a001 mov sl, r1 800659c: fa000ad7 blx 8009100 <__aeabi_dcmpgt> 80065a0: e3500000 cmp r0, #0 80065a4: 0a000059 beq 8006710 <__ieee754_hypot+0x280> 80065a8: e1a03004 mov r3, r4 80065ac: e3a02000 mov r2, #0 80065b0: e1a04002 mov r4, r2 80065b4: e1a05003 mov r5, r3 80065b8: e1a00004 mov r0, r4 80065bc: e1a01005 mov r1, r5 80065c0: fa000986 blx 8008be0 <__aeabi_dmul> 80065c4: e1a02007 mov r2, r7 80065c8: e58d0008 str r0, [sp, #8] 80065cc: e58d100c str r1, [sp, #12] 80065d0: e1a03006 mov r3, r6 80065d4: e1a00007 mov r0, r7 80065d8: e2861102 add r1, r6, #-2147483648 ; 0x80000000 80065dc: fa00097f blx 8008be0 <__aeabi_dmul> 80065e0: e1a02004 mov r2, r4 80065e4: e58d0010 str r0, [sp, #16] 80065e8: e58d1014 str r1, [sp, #20] 80065ec: e1a03005 mov r3, r5 80065f0: e1a0000b mov r0, fp 80065f4: e1a01009 mov r1, r9 80065f8: fa00089f blx 800887c <__adddf3> 80065fc: e1a02004 mov r2, r4 8006600: e1a06000 mov r6, r0 8006604: e1a07001 mov r7, r1 8006608: e1a0000b mov r0, fp 800660c: e1a03005 mov r3, r5 8006610: e1a01009 mov r1, r9 8006614: fa000897 blx 8008878 <__aeabi_dsub> 8006618: e1a02000 mov r2, r0 800661c: e1a03001 mov r3, r1 8006620: e1a00006 mov r0, r6 8006624: e1a01007 mov r1, r7 8006628: fa00096c blx 8008be0 <__aeabi_dmul> 800662c: e1a02000 mov r2, r0 8006630: e1a03001 mov r3, r1 8006634: e28d1010 add r1, sp, #16 8006638: e8910003 ldm r1, {r0, r1} 800663c: fa00088d blx 8008878 <__aeabi_dsub> 8006640: e1a02000 mov r2, r0 8006644: e1a03001 mov r3, r1 8006648: e28d1008 add r1, sp, #8 800664c: e8910003 ldm r1, {r0, r1} 8006650: fa000888 blx 8008878 <__aeabi_dsub> 8006654: eb000219 bl 8006ec0 <__ieee754_sqrt> 8006658: e1a0b000 mov fp, r0 800665c: e59dc000 ldr ip, [sp] 8006660: e35c0000 cmp ip, #0 8006664: 0a000008 beq 800668c <__ieee754_hypot+0x1fc> 8006668: e1a00a0c lsl r0, ip, #20 800666c: e28035ff add r3, r0, #1069547520 ; 0x3fc00000 8006670: e3a02000 mov r2, #0 8006674: e1a0000b mov r0, fp 8006678: e2833603 add r3, r3, #3145728 ; 0x300000 800667c: e1a05001 mov r5, r1 8006680: fa000956 blx 8008be0 <__aeabi_dmul> 8006684: e1a0400b mov r4, fp 8006688: e1a0b000 mov fp, r0 800668c: e1a0000b mov r0, fp 8006690: e28dd024 add sp, sp, #36 ; 0x24 8006694: e8bd4ff0 pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8006698: e12fff1e bx lr 800669c: e59f31b8 ldr r3, [pc, #440] ; 800685c <__ieee754_hypot+0x3cc> 80066a0: e1540003 cmp r4, r3 80066a4: da000056 ble 8006804 <__ieee754_hypot+0x374> 80066a8: e3c444ff bic r4, r4, #-16777216 ; 0xff000000 80066ac: e3c4460f bic r4, r4, #15728640 ; 0xf00000 80066b0: e194400b orrs r4, r4, fp 80066b4: 01a01009 moveq r1, r9 80066b8: 0a000006 beq 80066d8 <__ieee754_hypot+0x248> 80066bc: e59d8000 ldr r8, [sp] 80066c0: e1a0000b mov r0, fp 80066c4: e1a02008 mov r2, r8 80066c8: e1a01009 mov r1, r9 80066cc: e1a03005 mov r3, r5 80066d0: fa000869 blx 800887c <__adddf3> 80066d4: e1a0b000 mov fp, r0 80066d8: e225347f eor r3, r5, #2130706432 ; 0x7f000000 80066dc: e223360f eor r3, r3, #15728640 ; 0xf00000 80066e0: e1833007 orr r3, r3, r7 80066e4: e3530000 cmp r3, #0 80066e8: 01a0b007 moveq fp, r7 80066ec: 01a01005 moveq r1, r5 80066f0: eaffffe5 b 800668c <__ieee754_hypot+0x1fc> 80066f4: e1a0000b mov r0, fp 80066f8: e1a02007 mov r2, r7 80066fc: e1a01004 mov r1, r4 8006700: e1a03005 mov r3, r5 8006704: fa00085c blx 800887c <__adddf3> 8006708: e1a0b000 mov fp, r0 800670c: eaffffde b 800668c <__ieee754_hypot+0x1fc> 8006710: e3a00000 mov r0, #0 8006714: e1a02000 mov r2, r0 8006718: e2843601 add r3, r4, #1048576 ; 0x100000 800671c: e58d2008 str r2, [sp, #8] 8006720: e58d300c str r3, [sp, #12] 8006724: e1a04000 mov r4, r0 8006728: e1a02000 mov r2, r0 800672c: e1a03005 mov r3, r5 8006730: e28d1008 add r1, sp, #8 8006734: e8910003 ldm r1, {r0, r1} 8006738: fa000928 blx 8008be0 <__aeabi_dmul> 800673c: e1a02008 mov r2, r8 8006740: e58d0010 str r0, [sp, #16] 8006744: e58d1014 str r1, [sp, #20] 8006748: e1a0300a mov r3, sl 800674c: e1a00008 mov r0, r8 8006750: e28a1102 add r1, sl, #-2147483648 ; 0x80000000 8006754: fa000921 blx 8008be0 <__aeabi_dmul> 8006758: e1a02004 mov r2, r4 800675c: e58d0018 str r0, [sp, #24] 8006760: e58d101c str r1, [sp, #28] 8006764: e1a03005 mov r3, r5 8006768: e1a00007 mov r0, r7 800676c: e1a01006 mov r1, r6 8006770: fa000840 blx 8008878 <__aeabi_dsub> 8006774: e1a02000 mov r2, r0 8006778: e1a03001 mov r3, r1 800677c: e28d1008 add r1, sp, #8 8006780: e8910003 ldm r1, {r0, r1} 8006784: fa000915 blx 8008be0 <__aeabi_dmul> 8006788: e1a0200b mov r2, fp 800678c: e1a04000 mov r4, r0 8006790: e1a05001 mov r5, r1 8006794: e1a0000b mov r0, fp 8006798: e1a03009 mov r3, r9 800679c: e1a01009 mov r1, r9 80067a0: fa000835 blx 800887c <__adddf3> 80067a4: e28d3008 add r3, sp, #8 80067a8: e893000c ldm r3, {r2, r3} 80067ac: fa000831 blx 8008878 <__aeabi_dsub> 80067b0: e1a02007 mov r2, r7 80067b4: e1a03006 mov r3, r6 80067b8: fa000908 blx 8008be0 <__aeabi_dmul> 80067bc: e1a02000 mov r2, r0 80067c0: e1a03001 mov r3, r1 80067c4: e1a00004 mov r0, r4 80067c8: e1a01005 mov r1, r5 80067cc: fa00082a blx 800887c <__adddf3> 80067d0: e1a02000 mov r2, r0 80067d4: e1a03001 mov r3, r1 80067d8: e28d1018 add r1, sp, #24 80067dc: e8910003 ldm r1, {r0, r1} 80067e0: fa000824 blx 8008878 <__aeabi_dsub> 80067e4: e1a02000 mov r2, r0 80067e8: e1a03001 mov r3, r1 80067ec: e28d1010 add r1, sp, #16 80067f0: e8910003 ldm r1, {r0, r1} 80067f4: fa00081f blx 8008878 <__aeabi_dsub> 80067f8: eb0001b0 bl 8006ec0 <__ieee754_sqrt> 80067fc: e1a0b000 mov fp, r0 8006800: eaffff95 b 800665c <__ieee754_hypot+0x1cc> 8006804: e59d9000 ldr r9, [sp] 8006808: e1a01005 mov r1, r5 800680c: e2444596 sub r4, r4, #629145600 ; 0x25800000 8006810: e2455596 sub r5, r5, #629145600 ; 0x25800000 8006814: e3a0cf96 mov ip, #600 ; 0x258 8006818: e1a07009 mov r7, r9 800681c: e1a08006 mov r8, r6 8006820: e1a09004 mov r9, r4 8006824: e1a06005 mov r6, r5 8006828: e58dc000 str ip, [sp] 800682c: eaffff34 b 8006504 <__ieee754_hypot+0x74> 8006830: e59d9000 ldr r9, [sp] 8006834: e2844596 add r4, r4, #629145600 ; 0x25800000 8006838: e2499f96 sub r9, r9, #600 ; 0x258 800683c: e2855596 add r5, r5, #629145600 ; 0x25800000 8006840: e58d9000 str r9, [sp] 8006844: e1a06005 mov r6, r5 8006848: e1a09004 mov r9, r4 800684c: eaffff49 b 8006578 <__ieee754_hypot+0xe8> 8006850: 5f300000 .word 0x5f300000 8006854: 20afffff .word 0x20afffff 8006858: 7fd00000 .word 0x7fd00000 800685c: 7fefffff .word 0x7fefffff 08006860 <__ieee754_rem_pio2>: 8006860: e92d4ff0 push {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8006864: e59f33cc ldr r3, [pc, #972] ; 8006c38 <__ieee754_rem_pio2+0x3d8> 8006868: e3c16102 bic r6, r1, #-2147483648 ; 0x80000000 800686c: e1560003 cmp r6, r3 8006870: e24dd044 sub sp, sp, #68 ; 0x44 8006874: e1a04000 mov r4, r0 8006878: e1a05001 mov r5, r1 800687c: e1a08001 mov r8, r1 8006880: e1a07002 mov r7, r2 8006884: da000073 ble 8006a58 <__ieee754_rem_pio2+0x1f8> 8006888: e59f33ac ldr r3, [pc, #940] ; 8006c3c <__ieee754_rem_pio2+0x3dc> 800688c: e1560003 cmp r6, r3 8006890: ca000019 bgt 80068fc <__ieee754_rem_pio2+0x9c> 8006894: e3510000 cmp r1, #0 8006898: e28f3e37 add r3, pc, #880 ; 0x370 800689c: e893000c ldm r3, {r2, r3} 80068a0: da00014b ble 8006dd4 <__ieee754_rem_pio2+0x574> 80068a4: fa0007f3 blx 8008878 <__aeabi_dsub> 80068a8: e59f3390 ldr r3, [pc, #912] ; 8006c40 <__ieee754_rem_pio2+0x3e0> 80068ac: e1560003 cmp r6, r3 80068b0: e1a04000 mov r4, r0 80068b4: e1a05001 mov r5, r1 80068b8: 0a000078 beq 8006aa0 <__ieee754_rem_pio2+0x240> 80068bc: e28f3fd5 add r3, pc, #852 ; 0x354 80068c0: e893000c ldm r3, {r2, r3} 80068c4: fa0007eb blx 8008878 <__aeabi_dsub> 80068c8: e1a02000 mov r2, r0 80068cc: e1a03001 mov r3, r1 80068d0: e8870003 stm r7, {r0, r1} 80068d4: e1a00004 mov r0, r4 80068d8: e1a01005 mov r1, r5 80068dc: fa0007e5 blx 8008878 <__aeabi_dsub> 80068e0: e28f3e33 add r3, pc, #816 ; 0x330 80068e4: e893000c ldm r3, {r2, r3} 80068e8: fa0007e2 blx 8008878 <__aeabi_dsub> 80068ec: e3a04001 mov r4, #1 80068f0: e5870008 str r0, [r7, #8] 80068f4: e587100c str r1, [r7, #12] 80068f8: ea00005c b 8006a70 <__ieee754_rem_pio2+0x210> 80068fc: e59f3340 ldr r3, [pc, #832] ; 8006c44 <__ieee754_rem_pio2+0x3e4> 8006900: e1560003 cmp r6, r3 8006904: da00007a ble 8006af4 <__ieee754_rem_pio2+0x294> 8006908: e59f3338 ldr r3, [pc, #824] ; 8006c48 <__ieee754_rem_pio2+0x3e8> 800690c: e1560003 cmp r6, r3 8006910: ca00005a bgt 8006a80 <__ieee754_rem_pio2+0x220> 8006914: e1a09a46 asr r9, r6, #20 8006918: e2499e41 sub r9, r9, #1040 ; 0x410 800691c: e2499006 sub r9, r9, #6 8006920: e046ba09 sub fp, r6, r9, lsl #20 8006924: e1a0100b mov r1, fp 8006928: e1a0a000 mov sl, r0 800692c: fa0009f8 blx 8009114 <__aeabi_d2iz> 8006930: fa000877 blx 8008b14 <__aeabi_i2d> 8006934: e1a04000 mov r4, r0 8006938: e1a05001 mov r5, r1 800693c: e1a02000 mov r2, r0 8006940: e1a03001 mov r3, r1 8006944: e1a0000a mov r0, sl 8006948: e1a0100b mov r1, fp 800694c: e58d4028 str r4, [sp, #40] ; 0x28 8006950: e58d502c str r5, [sp, #44] ; 0x2c 8006954: fa0007c7 blx 8008878 <__aeabi_dsub> 8006958: e3a02000 mov r2, #0 800695c: e59f32e8 ldr r3, [pc, #744] ; 8006c4c <__ieee754_rem_pio2+0x3ec> 8006960: fa00089e blx 8008be0 <__aeabi_dmul> 8006964: e1a04000 mov r4, r0 8006968: e1a05001 mov r5, r1 800696c: fa0009e8 blx 8009114 <__aeabi_d2iz> 8006970: fa000867 blx 8008b14 <__aeabi_i2d> 8006974: e1a02000 mov r2, r0 8006978: e1a03001 mov r3, r1 800697c: e1a0a000 mov sl, r0 8006980: e1a0b001 mov fp, r1 8006984: e1a00004 mov r0, r4 8006988: e1a01005 mov r1, r5 800698c: e58da030 str sl, [sp, #48] ; 0x30 8006990: e58db034 str fp, [sp, #52] ; 0x34 8006994: fa0007b7 blx 8008878 <__aeabi_dsub> 8006998: e3a02000 mov r2, #0 800699c: e59f32a8 ldr r3, [pc, #680] ; 8006c4c <__ieee754_rem_pio2+0x3ec> 80069a0: fa00088e blx 8008be0 <__aeabi_dmul> 80069a4: e3a02000 mov r2, #0 80069a8: e3a03000 mov r3, #0 80069ac: e58d0038 str r0, [sp, #56] ; 0x38 80069b0: e58d103c str r1, [sp, #60] ; 0x3c 80069b4: fa0009bd blx 80090b0 <__aeabi_dcmpeq> 80069b8: e3500000 cmp r0, #0 80069bc: 03a04003 moveq r4, #3 80069c0: 0a000010 beq 8006a08 <__ieee754_rem_pio2+0x1a8> 80069c4: e1a0000a mov r0, sl 80069c8: e1a0100b mov r1, fp 80069cc: e3a02000 mov r2, #0 80069d0: e3a03000 mov r3, #0 80069d4: fa0009b5 blx 80090b0 <__aeabi_dcmpeq> 80069d8: e3a04003 mov r4, #3 80069dc: e3500000 cmp r0, #0 80069e0: e28d5030 add r5, sp, #48 ; 0x30 80069e4: e2444001 sub r4, r4, #1 80069e8: 0a000006 beq 8006a08 <__ieee754_rem_pio2+0x1a8> 80069ec: e9350003 ldmdb r5!, {r0, r1} 80069f0: e3a02000 mov r2, #0 80069f4: e3a03000 mov r3, #0 80069f8: fa0009ac blx 80090b0 <__aeabi_dcmpeq> 80069fc: e3500000 cmp r0, #0 8006a00: e2444001 sub r4, r4, #1 8006a04: 1afffff8 bne 80069ec <__ieee754_rem_pio2+0x18c> 8006a08: e3a0c002 mov ip, #2 8006a0c: e58dc000 str ip, [sp] 8006a10: e59fc238 ldr ip, [pc, #568] ; 8006c50 <__ieee754_rem_pio2+0x3f0> 8006a14: e1a03004 mov r3, r4 8006a18: e28d0028 add r0, sp, #40 ; 0x28 8006a1c: e1a01007 mov r1, r7 8006a20: e1a02009 mov r2, r9 8006a24: e58dc004 str ip, [sp, #4] 8006a28: eb000284 bl 8007440 <__kernel_rem_pio2> 8006a2c: e3580000 cmp r8, #0 8006a30: e1a04000 mov r4, r0 8006a34: aa00000d bge 8006a70 <__ieee754_rem_pio2+0x210> 8006a38: e5972004 ldr r2, [r7, #4] 8006a3c: e597300c ldr r3, [r7, #12] 8006a40: e2822102 add r2, r2, #-2147483648 ; 0x80000000 8006a44: e2833102 add r3, r3, #-2147483648 ; 0x80000000 8006a48: e5872004 str r2, [r7, #4] 8006a4c: e587300c str r3, [r7, #12] 8006a50: e2604000 rsb r4, r0, #0 8006a54: ea000005 b 8006a70 <__ieee754_rem_pio2+0x210> 8006a58: e8820030 stm r2, {r4, r5} 8006a5c: e3a03000 mov r3, #0 8006a60: e3a02000 mov r2, #0 8006a64: e5872008 str r2, [r7, #8] 8006a68: e587300c str r3, [r7, #12] 8006a6c: e3a04000 mov r4, #0 8006a70: e1a00004 mov r0, r4 8006a74: e28dd044 add sp, sp, #68 ; 0x44 8006a78: e8bd4ff0 pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8006a7c: e12fff1e bx lr 8006a80: e1a02000 mov r2, r0 8006a84: e1a03001 mov r3, r1 8006a88: fa00077a blx 8008878 <__aeabi_dsub> 8006a8c: e3a04000 mov r4, #0 8006a90: e5870008 str r0, [r7, #8] 8006a94: e587100c str r1, [r7, #12] 8006a98: e8870003 stm r7, {r0, r1} 8006a9c: eafffff3 b 8006a70 <__ieee754_rem_pio2+0x210> 8006aa0: e28f3f5e add r3, pc, #376 ; 0x178 8006aa4: e893000c ldm r3, {r2, r3} 8006aa8: fa000772 blx 8008878 <__aeabi_dsub> 8006aac: e28f3f5d add r3, pc, #372 ; 0x174 8006ab0: e893000c ldm r3, {r2, r3} 8006ab4: e1a04000 mov r4, r0 8006ab8: e1a05001 mov r5, r1 8006abc: fa00076d blx 8008878 <__aeabi_dsub> 8006ac0: e1a02000 mov r2, r0 8006ac4: e1a03001 mov r3, r1 8006ac8: e8870003 stm r7, {r0, r1} 8006acc: e1a00004 mov r0, r4 8006ad0: e1a01005 mov r1, r5 8006ad4: fa000767 blx 8008878 <__aeabi_dsub> 8006ad8: e28f3f52 add r3, pc, #328 ; 0x148 8006adc: e893000c ldm r3, {r2, r3} 8006ae0: fa000764 blx 8008878 <__aeabi_dsub> 8006ae4: e3a04001 mov r4, #1 8006ae8: e5870008 str r0, [r7, #8] 8006aec: e587100c str r1, [r7, #12] 8006af0: eaffffde b 8006a70 <__ieee754_rem_pio2+0x210> 8006af4: eb0006e1 bl 8008680 8006af8: e28f3e13 add r3, pc, #304 ; 0x130 8006afc: e893000c ldm r3, {r2, r3} 8006b00: e1a0a000 mov sl, r0 8006b04: e1a0b001 mov fp, r1 8006b08: fa000834 blx 8008be0 <__aeabi_dmul> 8006b0c: e3a02000 mov r2, #0 8006b10: e59f313c ldr r3, [pc, #316] ; 8006c54 <__ieee754_rem_pio2+0x3f4> 8006b14: fa000758 blx 800887c <__adddf3> 8006b18: fa00097d blx 8009114 <__aeabi_d2iz> 8006b1c: e1a04000 mov r4, r0 8006b20: fa0007fb blx 8008b14 <__aeabi_i2d> 8006b24: e28f30e4 add r3, pc, #228 ; 0xe4 8006b28: e893000c ldm r3, {r2, r3} 8006b2c: e58d0018 str r0, [sp, #24] 8006b30: e58d101c str r1, [sp, #28] 8006b34: fa000829 blx 8008be0 <__aeabi_dmul> 8006b38: e1a02000 mov r2, r0 8006b3c: e1a03001 mov r3, r1 8006b40: e1a0000a mov r0, sl 8006b44: e1a0100b mov r1, fp 8006b48: fa00074a blx 8008878 <__aeabi_dsub> 8006b4c: e28f30c4 add r3, pc, #196 ; 0xc4 8006b50: e893000c ldm r3, {r2, r3} 8006b54: e58d0008 str r0, [sp, #8] 8006b58: e58d100c str r1, [sp, #12] 8006b5c: e28d1018 add r1, sp, #24 8006b60: e8910003 ldm r1, {r0, r1} 8006b64: fa00081d blx 8008be0 <__aeabi_dmul> 8006b68: e354001f cmp r4, #31 8006b6c: e58d0010 str r0, [sp, #16] 8006b70: e58d1014 str r1, [sp, #20] 8006b74: e28d1008 add r1, sp, #8 8006b78: e8910003 ldm r1, {r0, r1} 8006b7c: ca000036 bgt 8006c5c <__ieee754_rem_pio2+0x3fc> 8006b80: e59f30d0 ldr r3, [pc, #208] ; 8006c58 <__ieee754_rem_pio2+0x3f8> 8006b84: e2442001 sub r2, r4, #1 8006b88: e7933102 ldr r3, [r3, r2, lsl #2] 8006b8c: e1530006 cmp r3, r6 8006b90: 0a000031 beq 8006c5c <__ieee754_rem_pio2+0x3fc> 8006b94: e28d3010 add r3, sp, #16 8006b98: e893000c ldm r3, {r2, r3} 8006b9c: fa000735 blx 8008878 <__aeabi_dsub> 8006ba0: e1a02000 mov r2, r0 8006ba4: e1a03001 mov r3, r1 8006ba8: e887000c stm r7, {r2, r3} 8006bac: e1a0a000 mov sl, r0 8006bb0: e1a05001 mov r5, r1 8006bb4: e1a0200a mov r2, sl 8006bb8: e1a03005 mov r3, r5 8006bbc: e28d1008 add r1, sp, #8 8006bc0: e8910003 ldm r1, {r0, r1} 8006bc4: fa00072b blx 8008878 <__aeabi_dsub> 8006bc8: e28d3010 add r3, sp, #16 8006bcc: e893000c ldm r3, {r2, r3} 8006bd0: fa000728 blx 8008878 <__aeabi_dsub> 8006bd4: e3580000 cmp r8, #0 8006bd8: e1a02000 mov r2, r0 8006bdc: e1a03001 mov r3, r1 8006be0: e5872008 str r2, [r7, #8] 8006be4: e587300c str r3, [r7, #12] 8006be8: aaffffa0 bge 8006a70 <__ieee754_rem_pio2+0x210> 8006bec: e2855102 add r5, r5, #-2147483648 ; 0x80000000 8006bf0: e2811102 add r1, r1, #-2147483648 ; 0x80000000 8006bf4: e587a000 str sl, [r7] 8006bf8: e5875004 str r5, [r7, #4] 8006bfc: e5870008 str r0, [r7, #8] 8006c00: e587100c str r1, [r7, #12] 8006c04: e2644000 rsb r4, r4, #0 8006c08: eaffff98 b 8006a70 <__ieee754_rem_pio2+0x210> 8006c0c: e1a00000 nop ; (mov r0, r0) 8006c10: 54400000 .word 0x54400000 8006c14: 3ff921fb .word 0x3ff921fb 8006c18: 1a626331 .word 0x1a626331 8006c1c: 3dd0b461 .word 0x3dd0b461 8006c20: 1a600000 .word 0x1a600000 8006c24: 3dd0b461 .word 0x3dd0b461 8006c28: 2e037073 .word 0x2e037073 8006c2c: 3ba3198a .word 0x3ba3198a 8006c30: 6dc9c883 .word 0x6dc9c883 8006c34: 3fe45f30 .word 0x3fe45f30 8006c38: 3fe921fb .word 0x3fe921fb 8006c3c: 4002d97b .word 0x4002d97b 8006c40: 3ff921fb .word 0x3ff921fb 8006c44: 413921fb .word 0x413921fb 8006c48: 7fefffff .word 0x7fefffff 8006c4c: 41700000 .word 0x41700000 8006c50: 0800ae3c .word 0x0800ae3c 8006c54: 3fe00000 .word 0x3fe00000 8006c58: 0800adbc .word 0x0800adbc 8006c5c: e28d3010 add r3, sp, #16 8006c60: e893000c ldm r3, {r2, r3} 8006c64: fa000703 blx 8008878 <__aeabi_dsub> 8006c68: e1a06a46 asr r6, r6, #20 8006c6c: e1a03081 lsl r3, r1, #1 8006c70: e0463aa3 sub r3, r6, r3, lsr #21 8006c74: e3530010 cmp r3, #16 8006c78: e1a05001 mov r5, r1 8006c7c: e1a0a000 mov sl, r0 8006c80: e8870003 stm r7, {r0, r1} 8006c84: daffffca ble 8006bb4 <__ieee754_rem_pio2+0x354> 8006c88: e28f3f82 add r3, pc, #520 ; 0x208 8006c8c: e893000c ldm r3, {r2, r3} 8006c90: e28d1018 add r1, sp, #24 8006c94: e8910003 ldm r1, {r0, r1} 8006c98: fa0007d0 blx 8008be0 <__aeabi_dmul> 8006c9c: e1a0a000 mov sl, r0 8006ca0: e1a0b001 mov fp, r1 8006ca4: e1a0200a mov r2, sl 8006ca8: e1a0300b mov r3, fp 8006cac: e28d1008 add r1, sp, #8 8006cb0: e8910003 ldm r1, {r0, r1} 8006cb4: fa0006ef blx 8008878 <__aeabi_dsub> 8006cb8: e58d0020 str r0, [sp, #32] 8006cbc: e58d1024 str r1, [sp, #36] ; 0x24 8006cc0: e28d3020 add r3, sp, #32 8006cc4: e893000c ldm r3, {r2, r3} 8006cc8: e28d1008 add r1, sp, #8 8006ccc: e8910003 ldm r1, {r0, r1} 8006cd0: fa0006e8 blx 8008878 <__aeabi_dsub> 8006cd4: e1a0200a mov r2, sl 8006cd8: e1a0300b mov r3, fp 8006cdc: fa0006e5 blx 8008878 <__aeabi_dsub> 8006ce0: e28f3f6e add r3, pc, #440 ; 0x1b8 8006ce4: e893000c ldm r3, {r2, r3} 8006ce8: e1a0a000 mov sl, r0 8006cec: e1a0b001 mov fp, r1 8006cf0: e28d1018 add r1, sp, #24 8006cf4: e8910003 ldm r1, {r0, r1} 8006cf8: fa0007b8 blx 8008be0 <__aeabi_dmul> 8006cfc: e1a0200a mov r2, sl 8006d00: e1a0300b mov r3, fp 8006d04: fa0006db blx 8008878 <__aeabi_dsub> 8006d08: e58d0010 str r0, [sp, #16] 8006d0c: e58d1014 str r1, [sp, #20] 8006d10: e28d3010 add r3, sp, #16 8006d14: e893000c ldm r3, {r2, r3} 8006d18: e28d1020 add r1, sp, #32 8006d1c: e8910003 ldm r1, {r0, r1} 8006d20: fa0006d4 blx 8008878 <__aeabi_dsub> 8006d24: e1a03081 lsl r3, r1, #1 8006d28: e0466aa3 sub r6, r6, r3, lsr #21 8006d2c: e3560031 cmp r6, #49 ; 0x31 8006d30: e1a05001 mov r5, r1 8006d34: e1a0a000 mov sl, r0 8006d38: e8870003 stm r7, {r0, r1} 8006d3c: da00004f ble 8006e80 <__ieee754_rem_pio2+0x620> 8006d40: e3a0242e mov r2, #771751936 ; 0x2e000000 8006d44: e59f316c ldr r3, [pc, #364] ; 8006eb8 <__ieee754_rem_pio2+0x658> 8006d48: e28d1018 add r1, sp, #24 8006d4c: e8910003 ldm r1, {r0, r1} 8006d50: fa0007a2 blx 8008be0 <__aeabi_dmul> 8006d54: e1a0a000 mov sl, r0 8006d58: e1a0b001 mov fp, r1 8006d5c: e1a0200a mov r2, sl 8006d60: e1a0300b mov r3, fp 8006d64: e28d1020 add r1, sp, #32 8006d68: e8910003 ldm r1, {r0, r1} 8006d6c: fa0006c1 blx 8008878 <__aeabi_dsub> 8006d70: e58d0008 str r0, [sp, #8] 8006d74: e58d100c str r1, [sp, #12] 8006d78: e28d3008 add r3, sp, #8 8006d7c: e893000c ldm r3, {r2, r3} 8006d80: e28d1020 add r1, sp, #32 8006d84: e8910003 ldm r1, {r0, r1} 8006d88: fa0006ba blx 8008878 <__aeabi_dsub> 8006d8c: e1a0200a mov r2, sl 8006d90: e1a0300b mov r3, fp 8006d94: fa0006b7 blx 8008878 <__aeabi_dsub> 8006d98: e28f3f42 add r3, pc, #264 ; 0x108 8006d9c: e893000c ldm r3, {r2, r3} 8006da0: e1a0a000 mov sl, r0 8006da4: e1a0b001 mov fp, r1 8006da8: e28d1018 add r1, sp, #24 8006dac: e8910003 ldm r1, {r0, r1} 8006db0: fa00078a blx 8008be0 <__aeabi_dmul> 8006db4: e1a0200a mov r2, sl 8006db8: e1a0300b mov r3, fp 8006dbc: fa0006ad blx 8008878 <__aeabi_dsub> 8006dc0: e58d0010 str r0, [sp, #16] 8006dc4: e58d1014 str r1, [sp, #20] 8006dc8: e28d1008 add r1, sp, #8 8006dcc: e8910003 ldm r1, {r0, r1} 8006dd0: eaffff6f b 8006b94 <__ieee754_rem_pio2+0x334> 8006dd4: fa0006a8 blx 800887c <__adddf3> 8006dd8: e59f30dc ldr r3, [pc, #220] ; 8006ebc <__ieee754_rem_pio2+0x65c> 8006ddc: e1560003 cmp r6, r3 8006de0: e1a04000 mov r4, r0 8006de4: e1a05001 mov r5, r1 8006de8: 0a00000f beq 8006e2c <__ieee754_rem_pio2+0x5cc> 8006dec: e28f30bc add r3, pc, #188 ; 0xbc 8006df0: e893000c ldm r3, {r2, r3} 8006df4: fa0006a0 blx 800887c <__adddf3> 8006df8: e1a02000 mov r2, r0 8006dfc: e1a03001 mov r3, r1 8006e00: e8870003 stm r7, {r0, r1} 8006e04: e1a00004 mov r0, r4 8006e08: e1a01005 mov r1, r5 8006e0c: fa000699 blx 8008878 <__aeabi_dsub> 8006e10: e28f3098 add r3, pc, #152 ; 0x98 8006e14: e893000c ldm r3, {r2, r3} 8006e18: fa000697 blx 800887c <__adddf3> 8006e1c: e3e04000 mvn r4, #0 8006e20: e5870008 str r0, [r7, #8] 8006e24: e587100c str r1, [r7, #12] 8006e28: eaffff10 b 8006a70 <__ieee754_rem_pio2+0x210> 8006e2c: e28f3064 add r3, pc, #100 ; 0x64 8006e30: e893000c ldm r3, {r2, r3} 8006e34: fa000690 blx 800887c <__adddf3> 8006e38: e28f3060 add r3, pc, #96 ; 0x60 8006e3c: e893000c ldm r3, {r2, r3} 8006e40: e1a04000 mov r4, r0 8006e44: e1a05001 mov r5, r1 8006e48: fa00068b blx 800887c <__adddf3> 8006e4c: e1a02000 mov r2, r0 8006e50: e1a03001 mov r3, r1 8006e54: e8870003 stm r7, {r0, r1} 8006e58: e1a00004 mov r0, r4 8006e5c: e1a01005 mov r1, r5 8006e60: fa000684 blx 8008878 <__aeabi_dsub> 8006e64: e28f3034 add r3, pc, #52 ; 0x34 8006e68: e893000c ldm r3, {r2, r3} 8006e6c: fa000682 blx 800887c <__adddf3> 8006e70: e3e04000 mvn r4, #0 8006e74: e5870008 str r0, [r7, #8] 8006e78: e587100c str r1, [r7, #12] 8006e7c: eafffefb b 8006a70 <__ieee754_rem_pio2+0x210> 8006e80: e28d3020 add r3, sp, #32 8006e84: e893000c ldm r3, {r2, r3} 8006e88: e58d2008 str r2, [sp, #8] 8006e8c: e58d300c str r3, [sp, #12] 8006e90: eaffff47 b 8006bb4 <__ieee754_rem_pio2+0x354> 8006e94: e1a00000 nop ; (mov r0, r0) 8006e98: 1a600000 .word 0x1a600000 8006e9c: 3dd0b461 .word 0x3dd0b461 8006ea0: 2e037073 .word 0x2e037073 8006ea4: 3ba3198a .word 0x3ba3198a 8006ea8: 252049c1 .word 0x252049c1 8006eac: 397b839a .word 0x397b839a 8006eb0: 1a626331 .word 0x1a626331 8006eb4: 3dd0b461 .word 0x3dd0b461 8006eb8: 3ba3198a .word 0x3ba3198a 8006ebc: 3ff921fb .word 0x3ff921fb 08006ec0 <__ieee754_sqrt>: 8006ec0: e59f222c ldr r2, [pc, #556] ; 80070f4 <__ieee754_sqrt+0x234> 8006ec4: e59fc228 ldr ip, [pc, #552] ; 80070f4 <__ieee754_sqrt+0x234> 8006ec8: e0012002 and r2, r1, r2 8006ecc: e152000c cmp r2, ip 8006ed0: e92d45f8 push {r3, r4, r5, r6, r7, r8, sl, lr} 8006ed4: e1a02000 mov r2, r0 8006ed8: e1a04000 mov r4, r0 8006edc: e1a05001 mov r5, r1 8006ee0: e1a06000 mov r6, r0 8006ee4: e1a07001 mov r7, r1 8006ee8: e1a03001 mov r3, r1 8006eec: 0a00006c beq 80070a4 <__ieee754_sqrt+0x1e4> 8006ef0: e3510000 cmp r1, #0 8006ef4: da000050 ble 800703c <__ieee754_sqrt+0x17c> 8006ef8: e1b01a41 asrs r1, r1, #20 8006efc: 0a000059 beq 8007068 <__ieee754_sqrt+0x1a8> 8006f00: e3c334ff bic r3, r3, #-16777216 ; 0xff000000 8006f04: e3110001 tst r1, #1 8006f08: e3c3360f bic r3, r3, #15728640 ; 0xf00000 8006f0c: e2415fff sub r5, r1, #1020 ; 0x3fc 8006f10: e3833601 orr r3, r3, #1048576 ; 0x100000 8006f14: 01a01fa2 lsreq r1, r2, #31 8006f18: 01a02082 lsleq r2, r2, #1 8006f1c: 00813083 addeq r3, r1, r3, lsl #1 8006f20: e2455003 sub r5, r5, #3 8006f24: e1a01fa2 lsr r1, r2, #31 8006f28: e3a07000 mov r7, #0 8006f2c: e0813083 add r3, r1, r3, lsl #1 8006f30: e1a050c5 asr r5, r5, #1 8006f34: e1a02082 lsl r2, r2, #1 8006f38: e3a0c016 mov ip, #22 8006f3c: e1a00007 mov r0, r7 8006f40: e3a01602 mov r1, #2097152 ; 0x200000 8006f44: e0804001 add r4, r0, r1 8006f48: e1540003 cmp r4, r3 8006f4c: e1a06fa2 lsr r6, r2, #31 8006f50: d0840001 addle r0, r4, r1 8006f54: d0643003 rsble r3, r4, r3 8006f58: d0877001 addle r7, r7, r1 8006f5c: e25cc001 subs ip, ip, #1 8006f60: e0863083 add r3, r6, r3, lsl #1 8006f64: e1a02082 lsl r2, r2, #1 8006f68: e1a010a1 lsr r1, r1, #1 8006f6c: 1afffff4 bne 8006f44 <__ieee754_sqrt+0x84> 8006f70: e3a06020 mov r6, #32 8006f74: e1a0800c mov r8, ip 8006f78: e3a01102 mov r1, #-2147483648 ; 0x80000000 8006f7c: e1500003 cmp r0, r3 8006f80: e0814008 add r4, r1, r8 8006f84: ba000002 blt 8006f94 <__ieee754_sqrt+0xd4> 8006f88: e1540002 cmp r4, r2 8006f8c: 91530000 cmpls r3, r0 8006f90: 1a00000a bne 8006fc0 <__ieee754_sqrt+0x100> 8006f94: e2048102 and r8, r4, #-2147483648 ; 0x80000000 8006f98: e3580102 cmp r8, #-2147483648 ; 0x80000000 8006f9c: e0848001 add r8, r4, r1 8006fa0: 0a00001b beq 8007014 <__ieee754_sqrt+0x154> 8006fa4: e1a0a000 mov sl, r0 8006fa8: e1540002 cmp r4, r2 8006fac: e0603003 rsb r3, r0, r3 8006fb0: 82433001 subhi r3, r3, #1 8006fb4: e0642002 rsb r2, r4, r2 8006fb8: e08cc001 add ip, ip, r1 8006fbc: e1a0000a mov r0, sl 8006fc0: e1a04fa2 lsr r4, r2, #31 8006fc4: e2566001 subs r6, r6, #1 8006fc8: e0843083 add r3, r4, r3, lsl #1 8006fcc: e1a02082 lsl r2, r2, #1 8006fd0: e1a010a1 lsr r1, r1, #1 8006fd4: 1affffe8 bne 8006f7c <__ieee754_sqrt+0xbc> 8006fd8: e1923003 orrs r3, r2, r3 8006fdc: 1a000010 bne 8007024 <__ieee754_sqrt+0x164> 8006fe0: e1a060ac lsr r6, ip, #1 8006fe4: e1a010c7 asr r1, r7, #1 8006fe8: e28115ff add r1, r1, #1069547520 ; 0x3fc00000 8006fec: e3170001 tst r7, #1 8006ff0: e2811602 add r1, r1, #2097152 ; 0x200000 8006ff4: 13866102 orrne r6, r6, #-2147483648 ; 0x80000000 8006ff8: e0813a05 add r3, r1, r5, lsl #20 8006ffc: e1a04006 mov r4, r6 8007000: e1a05003 mov r5, r3 8007004: e1a00004 mov r0, r4 8007008: e1a01005 mov r1, r5 800700c: e8bd45f8 pop {r3, r4, r5, r6, r7, r8, sl, lr} 8007010: e12fff1e bx lr 8007014: e3580000 cmp r8, #0 8007018: a280a001 addge sl, r0, #1 800701c: aaffffe1 bge 8006fa8 <__ieee754_sqrt+0xe8> 8007020: eaffffdf b 8006fa4 <__ieee754_sqrt+0xe4> 8007024: e37c0001 cmn ip, #1 8007028: 02877001 addeq r7, r7, #1 800702c: 0affffec beq 8006fe4 <__ieee754_sqrt+0x124> 8007030: e20c3001 and r3, ip, #1 8007034: e083c00c add ip, r3, ip 8007038: eaffffe8 b 8006fe0 <__ieee754_sqrt+0x120> 800703c: e3c1c102 bic ip, r1, #-2147483648 ; 0x80000000 8007040: e19cc000 orrs ip, ip, r0 8007044: 0affffee beq 8007004 <__ieee754_sqrt+0x144> 8007048: e3510000 cmp r1, #0 800704c: 01a01001 moveq r1, r1 8007050: 1a00001e bne 80070d0 <__ieee754_sqrt+0x210> 8007054: e1a035a2 lsr r3, r2, #11 8007058: e3530000 cmp r3, #0 800705c: e2411015 sub r1, r1, #21 8007060: e1a02a82 lsl r2, r2, #21 8007064: 0afffffa beq 8007054 <__ieee754_sqrt+0x194> 8007068: e2130601 ands r0, r3, #1048576 ; 0x100000 800706c: 13a04020 movne r4, #32 8007070: 13a0c001 movne ip, #1 8007074: 13a00000 movne r0, #0 8007078: 1a000005 bne 8007094 <__ieee754_sqrt+0x1d4> 800707c: e1a03083 lsl r3, r3, #1 8007080: e3130601 tst r3, #1048576 ; 0x100000 8007084: e2800001 add r0, r0, #1 8007088: 0afffffb beq 800707c <__ieee754_sqrt+0x1bc> 800708c: e260c001 rsb ip, r0, #1 8007090: e2604020 rsb r4, r0, #32 8007094: e1833432 orr r3, r3, r2, lsr r4 8007098: e081100c add r1, r1, ip 800709c: e1a02012 lsl r2, r2, r0 80070a0: eaffff96 b 8006f00 <__ieee754_sqrt+0x40> 80070a4: e1a02000 mov r2, r0 80070a8: e1a03001 mov r3, r1 80070ac: fa0006cb blx 8008be0 <__aeabi_dmul> 80070b0: e1a02000 mov r2, r0 80070b4: e1a03001 mov r3, r1 80070b8: e1a00004 mov r0, r4 80070bc: e1a01005 mov r1, r5 80070c0: fa0005ed blx 800887c <__adddf3> 80070c4: e1a04000 mov r4, r0 80070c8: e1a05001 mov r5, r1 80070cc: eaffffcc b 8007004 <__ieee754_sqrt+0x144> 80070d0: e1a03005 mov r3, r5 80070d4: e1a02000 mov r2, r0 80070d8: fa0005e6 blx 8008878 <__aeabi_dsub> 80070dc: e1a02000 mov r2, r0 80070e0: e1a03001 mov r3, r1 80070e4: fa000752 blx 8008e34 <__aeabi_ddiv> 80070e8: e1a04000 mov r4, r0 80070ec: e1a05001 mov r5, r1 80070f0: eaffffc3 b 8007004 <__ieee754_sqrt+0x144> 80070f4: 7ff00000 .word 0x7ff00000 080070f8 <__kernel_cos>: 80070f8: e92d4ff0 push {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80070fc: e3c14102 bic r4, r1, #-2147483648 ; 0x80000000 8007100: e24dd01c sub sp, sp, #28 8007104: e35405f9 cmp r4, #1044381696 ; 0x3e400000 8007108: e1a08000 mov r8, r0 800710c: e1a09001 mov r9, r1 8007110: e1a05001 mov r5, r1 8007114: e88d000c stm sp, {r2, r3} 8007118: aa00004e bge 8007258 <__kernel_cos+0x160> 800711c: fa0007fc blx 8009114 <__aeabi_d2iz> 8007120: e3500000 cmp r0, #0 8007124: 0a0000b0 beq 80073ec <__kernel_cos+0x2f4> 8007128: e1a02008 mov r2, r8 800712c: e1a03009 mov r3, r9 8007130: e1a00008 mov r0, r8 8007134: e1a01009 mov r1, r9 8007138: fa0006a8 blx 8008be0 <__aeabi_dmul> 800713c: e28f3fad add r3, pc, #692 ; 0x2b4 8007140: e893000c ldm r3, {r2, r3} 8007144: e1a06000 mov r6, r0 8007148: e1a07001 mov r7, r1 800714c: fa0006a3 blx 8008be0 <__aeabi_dmul> 8007150: e28f3faa add r3, pc, #680 ; 0x2a8 8007154: e893000c ldm r3, {r2, r3} 8007158: fa0005c7 blx 800887c <__adddf3> 800715c: e1a02006 mov r2, r6 8007160: e1a03007 mov r3, r7 8007164: fa00069d blx 8008be0 <__aeabi_dmul> 8007168: e28f3fa6 add r3, pc, #664 ; 0x298 800716c: e893000c ldm r3, {r2, r3} 8007170: fa0005c0 blx 8008878 <__aeabi_dsub> 8007174: e1a02006 mov r2, r6 8007178: e1a03007 mov r3, r7 800717c: fa000697 blx 8008be0 <__aeabi_dmul> 8007180: e28f3fa2 add r3, pc, #648 ; 0x288 8007184: e893000c ldm r3, {r2, r3} 8007188: fa0005bb blx 800887c <__adddf3> 800718c: e1a02006 mov r2, r6 8007190: e1a03007 mov r3, r7 8007194: fa000691 blx 8008be0 <__aeabi_dmul> 8007198: e28f3f9e add r3, pc, #632 ; 0x278 800719c: e893000c ldm r3, {r2, r3} 80071a0: fa0005b4 blx 8008878 <__aeabi_dsub> 80071a4: e1a02006 mov r2, r6 80071a8: e1a03007 mov r3, r7 80071ac: fa00068b blx 8008be0 <__aeabi_dmul> 80071b0: e28f3f9a add r3, pc, #616 ; 0x268 80071b4: e893000c ldm r3, {r2, r3} 80071b8: fa0005af blx 800887c <__adddf3> 80071bc: e1a02006 mov r2, r6 80071c0: e1a03007 mov r3, r7 80071c4: fa000685 blx 8008be0 <__aeabi_dmul> 80071c8: e1a0a000 mov sl, r0 80071cc: e1a0b001 mov fp, r1 80071d0: e1a00006 mov r0, r6 80071d4: e1a01007 mov r1, r7 80071d8: e3a02000 mov r2, #0 80071dc: e59f3244 ldr r3, [pc, #580] ; 8007428 <__kernel_cos+0x330> 80071e0: fa00067e blx 8008be0 <__aeabi_dmul> 80071e4: e1a0200a mov r2, sl 80071e8: e58d0008 str r0, [sp, #8] 80071ec: e58d100c str r1, [sp, #12] 80071f0: e1a0300b mov r3, fp 80071f4: e1a00006 mov r0, r6 80071f8: e1a01007 mov r1, r7 80071fc: fa000677 blx 8008be0 <__aeabi_dmul> 8007200: e89d000c ldm sp, {r2, r3} 8007204: e1a04000 mov r4, r0 8007208: e1a05001 mov r5, r1 800720c: e1a00008 mov r0, r8 8007210: e1a01009 mov r1, r9 8007214: fa000671 blx 8008be0 <__aeabi_dmul> 8007218: e1a02000 mov r2, r0 800721c: e1a03001 mov r3, r1 8007220: e1a00004 mov r0, r4 8007224: e1a01005 mov r1, r5 8007228: fa000592 blx 8008878 <__aeabi_dsub> 800722c: e1a02000 mov r2, r0 8007230: e1a03001 mov r3, r1 8007234: e28d1008 add r1, sp, #8 8007238: e8910003 ldm r1, {r0, r1} 800723c: fa00058d blx 8008878 <__aeabi_dsub> 8007240: e1a02000 mov r2, r0 8007244: e1a03001 mov r3, r1 8007248: e3a00000 mov r0, #0 800724c: e59f11d8 ldr r1, [pc, #472] ; 800742c <__kernel_cos+0x334> 8007250: fa000588 blx 8008878 <__aeabi_dsub> 8007254: ea00005a b 80073c4 <__kernel_cos+0x2cc> 8007258: e1a02000 mov r2, r0 800725c: e1a03001 mov r3, r1 8007260: fa00065e blx 8008be0 <__aeabi_dmul> 8007264: e28f3f63 add r3, pc, #396 ; 0x18c 8007268: e893000c ldm r3, {r2, r3} 800726c: e1a06000 mov r6, r0 8007270: e1a07001 mov r7, r1 8007274: fa000659 blx 8008be0 <__aeabi_dmul> 8007278: e28f3d06 add r3, pc, #384 ; 0x180 800727c: e893000c ldm r3, {r2, r3} 8007280: fa00057d blx 800887c <__adddf3> 8007284: e1a02006 mov r2, r6 8007288: e1a03007 mov r3, r7 800728c: fa000653 blx 8008be0 <__aeabi_dmul> 8007290: e28f3e17 add r3, pc, #368 ; 0x170 8007294: e893000c ldm r3, {r2, r3} 8007298: fa000576 blx 8008878 <__aeabi_dsub> 800729c: e1a02006 mov r2, r6 80072a0: e1a03007 mov r3, r7 80072a4: fa00064d blx 8008be0 <__aeabi_dmul> 80072a8: e28f3e16 add r3, pc, #352 ; 0x160 80072ac: e893000c ldm r3, {r2, r3} 80072b0: fa000571 blx 800887c <__adddf3> 80072b4: e1a02006 mov r2, r6 80072b8: e1a03007 mov r3, r7 80072bc: fa000647 blx 8008be0 <__aeabi_dmul> 80072c0: e28f3e15 add r3, pc, #336 ; 0x150 80072c4: e893000c ldm r3, {r2, r3} 80072c8: fa00056a blx 8008878 <__aeabi_dsub> 80072cc: e1a02006 mov r2, r6 80072d0: e1a03007 mov r3, r7 80072d4: fa000641 blx 8008be0 <__aeabi_dmul> 80072d8: e28f3d05 add r3, pc, #320 ; 0x140 80072dc: e893000c ldm r3, {r2, r3} 80072e0: fa000565 blx 800887c <__adddf3> 80072e4: e1a03007 mov r3, r7 80072e8: e1a02006 mov r2, r6 80072ec: fa00063b blx 8008be0 <__aeabi_dmul> 80072f0: e59f3138 ldr r3, [pc, #312] ; 8007430 <__kernel_cos+0x338> 80072f4: e1540003 cmp r4, r3 80072f8: e1a0a000 mov sl, r0 80072fc: e1a0b001 mov fp, r1 8007300: daffffb2 ble 80071d0 <__kernel_cos+0xd8> 8007304: e59f3128 ldr r3, [pc, #296] ; 8007434 <__kernel_cos+0x33c> 8007308: e1540003 cmp r4, r3 800730c: ca00002f bgt 80073d0 <__kernel_cos+0x2d8> 8007310: e2443602 sub r3, r4, #2097152 ; 0x200000 8007314: e3a02000 mov r2, #0 8007318: e3a00000 mov r0, #0 800731c: e59f1108 ldr r1, [pc, #264] ; 800742c <__kernel_cos+0x334> 8007320: e1a04002 mov r4, r2 8007324: e1a05003 mov r5, r3 8007328: fa000552 blx 8008878 <__aeabi_dsub> 800732c: e58d0010 str r0, [sp, #16] 8007330: e58d1014 str r1, [sp, #20] 8007334: e3a02000 mov r2, #0 8007338: e59f30e8 ldr r3, [pc, #232] ; 8007428 <__kernel_cos+0x330> 800733c: e1a00006 mov r0, r6 8007340: e1a01007 mov r1, r7 8007344: fa000625 blx 8008be0 <__aeabi_dmul> 8007348: e1a02004 mov r2, r4 800734c: e1a03005 mov r3, r5 8007350: fa000548 blx 8008878 <__aeabi_dsub> 8007354: e1a0200a mov r2, sl 8007358: e58d0008 str r0, [sp, #8] 800735c: e58d100c str r1, [sp, #12] 8007360: e1a0300b mov r3, fp 8007364: e1a00006 mov r0, r6 8007368: e1a01007 mov r1, r7 800736c: fa00061b blx 8008be0 <__aeabi_dmul> 8007370: e89d000c ldm sp, {r2, r3} 8007374: e1a04000 mov r4, r0 8007378: e1a05001 mov r5, r1 800737c: e1a00008 mov r0, r8 8007380: e1a01009 mov r1, r9 8007384: fa000615 blx 8008be0 <__aeabi_dmul> 8007388: e1a02000 mov r2, r0 800738c: e1a03001 mov r3, r1 8007390: e1a00004 mov r0, r4 8007394: e1a01005 mov r1, r5 8007398: fa000536 blx 8008878 <__aeabi_dsub> 800739c: e1a02000 mov r2, r0 80073a0: e1a03001 mov r3, r1 80073a4: e28d1008 add r1, sp, #8 80073a8: e8910003 ldm r1, {r0, r1} 80073ac: fa000531 blx 8008878 <__aeabi_dsub> 80073b0: e1a02000 mov r2, r0 80073b4: e1a03001 mov r3, r1 80073b8: e28d1010 add r1, sp, #16 80073bc: e8910003 ldm r1, {r0, r1} 80073c0: fa00052c blx 8008878 <__aeabi_dsub> 80073c4: e28dd01c add sp, sp, #28 80073c8: e8bd4ff0 pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80073cc: e12fff1e bx lr 80073d0: e59f4060 ldr r4, [pc, #96] ; 8007438 <__kernel_cos+0x340> 80073d4: e3a03000 mov r3, #0 80073d8: e58d3010 str r3, [sp, #16] 80073dc: e58d4014 str r4, [sp, #20] 80073e0: e59f5054 ldr r5, [pc, #84] ; 800743c <__kernel_cos+0x344> 80073e4: e3a04000 mov r4, #0 80073e8: eaffffd1 b 8007334 <__kernel_cos+0x23c> 80073ec: e3a00000 mov r0, #0 80073f0: e59f1034 ldr r1, [pc, #52] ; 800742c <__kernel_cos+0x334> 80073f4: eafffff2 b 80073c4 <__kernel_cos+0x2cc> 80073f8: be8838d4 .word 0xbe8838d4 80073fc: bda8fae9 .word 0xbda8fae9 8007400: bdb4b1c4 .word 0xbdb4b1c4 8007404: 3e21ee9e .word 0x3e21ee9e 8007408: 809c52ad .word 0x809c52ad 800740c: 3e927e4f .word 0x3e927e4f 8007410: 19cb1590 .word 0x19cb1590 8007414: 3efa01a0 .word 0x3efa01a0 8007418: 16c15177 .word 0x16c15177 800741c: 3f56c16c .word 0x3f56c16c 8007420: 5555554c .word 0x5555554c 8007424: 3fa55555 .word 0x3fa55555 8007428: 3fe00000 .word 0x3fe00000 800742c: 3ff00000 .word 0x3ff00000 8007430: 3fd33332 .word 0x3fd33332 8007434: 3fe90000 .word 0x3fe90000 8007438: 3fe70000 .word 0x3fe70000 800743c: 3fd20000 .word 0x3fd20000 08007440 <__kernel_rem_pio2>: 8007440: e92d4ff0 push {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8007444: e59feb54 ldr lr, [pc, #2900] ; 8007fa0 <__kernel_rem_pio2+0xb60> 8007448: e242c003 sub ip, r2, #3 800744c: e0ce4e9c smull r4, lr, ip, lr 8007450: e1a0cfcc asr ip, ip, #31 8007454: e24ddf9b sub sp, sp, #620 ; 0x26c 8007458: e06cc14e rsb ip, ip, lr, asr #2 800745c: e1a07003 mov r7, r3 8007460: e59d4290 ldr r4, [sp, #656] ; 0x290 8007464: e1cccfcc bic ip, ip, ip, asr #31 8007468: e59f3b34 ldr r3, [pc, #2868] ; 8007fa4 <__kernel_rem_pio2+0xb64> 800746c: e58dc028 str ip, [sp, #40] ; 0x28 8007470: e7933104 ldr r3, [r3, r4, lsl #2] 8007474: e247c001 sub ip, r7, #1 8007478: e59d4028 ldr r4, [sp, #40] ; 0x28 800747c: e58dc010 str ip, [sp, #16] 8007480: e1e0c004 mvn ip, r4 8007484: e59d4010 ldr r4, [sp, #16] 8007488: e08cc08c add ip, ip, ip, lsl #1 800748c: e58d3024 str r3, [sp, #36] ; 0x24 8007490: e082c18c add ip, r2, ip, lsl #3 8007494: e0943003 adds r3, r4, r3 8007498: e58d0018 str r0, [sp, #24] 800749c: e58d1020 str r1, [sp, #32] 80074a0: e58dc01c str ip, [sp, #28] 80074a4: 4a000011 bmi 80074f0 <__kernel_rem_pio2+0xb0> 80074a8: e59dc028 ldr ip, [sp, #40] ; 0x28 80074ac: e064500c rsb r5, r4, ip 80074b0: e59dc294 ldr ip, [sp, #660] ; 0x294 80074b4: e2833001 add r3, r3, #1 80074b8: e28d6038 add r6, sp, #56 ; 0x38 80074bc: e1a08103 lsl r8, r3, #2 80074c0: e3a04000 mov r4, #0 80074c4: e08ca105 add sl, ip, r5, lsl #2 80074c8: e3550000 cmp r5, #0 80074cc: b3a00000 movlt r0, #0 80074d0: b3a01000 movlt r1, #0 80074d4: a79a0004 ldrge r0, [sl, r4] 80074d8: ab000d6a blge 800aa88 <____aeabi_i2d_from_arm> 80074dc: e2844004 add r4, r4, #4 80074e0: e1540008 cmp r4, r8 80074e4: e8a60003 stmia r6!, {r0, r1} 80074e8: e2855001 add r5, r5, #1 80074ec: 1afffff5 bne 80074c8 <__kernel_rem_pio2+0x88> 80074f0: e59d4024 ldr r4, [sp, #36] ; 0x24 80074f4: e3540000 cmp r4, #0 80074f8: ba000022 blt 8007588 <__kernel_rem_pio2+0x148> 80074fc: e59d4024 ldr r4, [sp, #36] ; 0x24 8007500: e28dcd06 add ip, sp, #384 ; 0x180 8007504: e08cc184 add ip, ip, r4, lsl #3 8007508: e58dc004 str ip, [sp, #4] 800750c: e28daf5e add sl, sp, #376 ; 0x178 8007510: e1a0b007 mov fp, r7 8007514: e59dc010 ldr ip, [sp, #16] 8007518: e35c0000 cmp ip, #0 800751c: b3a08000 movlt r8, #0 8007520: b3a09000 movlt r9, #0 8007524: ba000012 blt 8007574 <__kernel_rem_pio2+0x134> 8007528: e28de038 add lr, sp, #56 ; 0x38 800752c: e59d5018 ldr r5, [sp, #24] 8007530: e08e618b add r6, lr, fp, lsl #3 8007534: e3a08000 mov r8, #0 8007538: e3a09000 mov r9, #0 800753c: e3a04000 mov r4, #0 8007540: e936000c ldmdb r6!, {r2, r3} 8007544: e8b50003 ldm r5!, {r0, r1} 8007548: fa0005a4 blx 8008be0 <__aeabi_dmul> 800754c: e1a02000 mov r2, r0 8007550: e1a03001 mov r3, r1 8007554: e1a00008 mov r0, r8 8007558: e1a01009 mov r1, r9 800755c: fa0004c6 blx 800887c <__adddf3> 8007560: e2844001 add r4, r4, #1 8007564: e1540007 cmp r4, r7 8007568: e1a08000 mov r8, r0 800756c: e1a09001 mov r9, r1 8007570: 1afffff2 bne 8007540 <__kernel_rem_pio2+0x100> 8007574: e8aa0300 stmia sl!, {r8, r9} 8007578: e59dc004 ldr ip, [sp, #4] 800757c: e15a000c cmp sl, ip 8007580: e28bb001 add fp, fp, #1 8007584: 1affffe2 bne 8007514 <__kernel_rem_pio2+0xd4> 8007588: e59d4024 ldr r4, [sp, #36] ; 0x24 800758c: e28dcf86 add ip, sp, #536 ; 0x218 8007590: e2443001 sub r3, r4, #1 8007594: e1a03103 lsl r3, r3, #2 8007598: e08cc104 add ip, ip, r4, lsl #2 800759c: e58d4004 str r4, [sp, #4] 80075a0: e28d4f9a add r4, sp, #616 ; 0x268 80075a4: e0844003 add r4, r4, r3 80075a8: e58d302c str r3, [sp, #44] ; 0x2c 80075ac: e58dc030 str ip, [sp, #48] ; 0x30 80075b0: e58d4034 str r4, [sp, #52] ; 0x34 80075b4: e59dc004 ldr ip, [sp, #4] 80075b8: e28def9a add lr, sp, #616 ; 0x268 80075bc: e1a0418c lsl r4, ip, #3 80075c0: e08e3004 add r3, lr, r4 80075c4: e35c0000 cmp ip, #0 80075c8: e24390f0 sub r9, r3, #240 ; 0xf0 80075cc: e8990300 ldm r9, {r8, r9} 80075d0: da00001d ble 800764c <__kernel_rem_pio2+0x20c> 80075d4: e28d6f5e add r6, sp, #376 ; 0x178 80075d8: e28d5f85 add r5, sp, #532 ; 0x214 80075dc: e0864004 add r4, r6, r4 80075e0: e3a02000 mov r2, #0 80075e4: e59f39bc ldr r3, [pc, #2492] ; 8007fa8 <__kernel_rem_pio2+0xb68> 80075e8: e1a00008 mov r0, r8 80075ec: e1a01009 mov r1, r9 80075f0: fa00057a blx 8008be0 <__aeabi_dmul> 80075f4: fa0006c6 blx 8009114 <__aeabi_d2iz> 80075f8: fa000545 blx 8008b14 <__aeabi_i2d> 80075fc: e3a02000 mov r2, #0 8007600: e59f39a4 ldr r3, [pc, #2468] ; 8007fac <__kernel_rem_pio2+0xb6c> 8007604: e1a0a000 mov sl, r0 8007608: e1a0b001 mov fp, r1 800760c: fa000573 blx 8008be0 <__aeabi_dmul> 8007610: e1a02000 mov r2, r0 8007614: e1a03001 mov r3, r1 8007618: e1a00008 mov r0, r8 800761c: e1a01009 mov r1, r9 8007620: fa000494 blx 8008878 <__aeabi_dsub> 8007624: fa0006ba blx 8009114 <__aeabi_d2iz> 8007628: e1a0200a mov r2, sl 800762c: e5a50004 str r0, [r5, #4]! 8007630: e1a0300b mov r3, fp 8007634: e9340003 ldmdb r4!, {r0, r1} 8007638: fa00048f blx 800887c <__adddf3> 800763c: e1540006 cmp r4, r6 8007640: e1a08000 mov r8, r0 8007644: e1a09001 mov r9, r1 8007648: 1affffe4 bne 80075e0 <__kernel_rem_pio2+0x1a0> 800764c: e59d201c ldr r2, [sp, #28] 8007650: e1a00008 mov r0, r8 8007654: e1a01009 mov r1, r9 8007658: eb000412 bl 80086a8 800765c: e3a02000 mov r2, #0 8007660: e3a035ff mov r3, #1069547520 ; 0x3fc00000 8007664: e1a04000 mov r4, r0 8007668: e1a05001 mov r5, r1 800766c: fa00055b blx 8008be0 <__aeabi_dmul> 8007670: ebfff8e2 bl 8005a00 8007674: e3a02000 mov r2, #0 8007678: e59f3930 ldr r3, [pc, #2352] ; 8007fb0 <__kernel_rem_pio2+0xb70> 800767c: fa000557 blx 8008be0 <__aeabi_dmul> 8007680: e1a02000 mov r2, r0 8007684: e1a03001 mov r3, r1 8007688: e1a00004 mov r0, r4 800768c: e1a01005 mov r1, r5 8007690: fa000478 blx 8008878 <__aeabi_dsub> 8007694: e1a04000 mov r4, r0 8007698: e1a05001 mov r5, r1 800769c: fa00069c blx 8009114 <__aeabi_d2iz> 80076a0: e1a06000 mov r6, r0 80076a4: fa00051a blx 8008b14 <__aeabi_i2d> 80076a8: e1a02000 mov r2, r0 80076ac: e1a03001 mov r3, r1 80076b0: e1a00004 mov r0, r4 80076b4: e1a01005 mov r1, r5 80076b8: fa00046e blx 8008878 <__aeabi_dsub> 80076bc: e59d401c ldr r4, [sp, #28] 80076c0: e3540000 cmp r4, #0 80076c4: e1a08000 mov r8, r0 80076c8: e1a09001 mov r9, r1 80076cc: da00012d ble 8007b88 <__kernel_rem_pio2+0x748> 80076d0: e59dc004 ldr ip, [sp, #4] 80076d4: e28def9a add lr, sp, #616 ; 0x268 80076d8: e24c2001 sub r2, ip, #1 80076dc: e08e2102 add r2, lr, r2, lsl #2 80076e0: e5120050 ldr r0, [r2, #-80] ; 0x50 80076e4: e2643018 rsb r3, r4, #24 80076e8: e1a01350 asr r1, r0, r3 80076ec: e0403311 sub r3, r0, r1, lsl r3 80076f0: e2645017 rsb r5, r4, #23 80076f4: e1a05553 asr r5, r3, r5 80076f8: e5023050 str r3, [r2, #-80] ; 0x50 80076fc: e0866001 add r6, r6, r1 8007700: e3550000 cmp r5, #0 8007704: da000028 ble 80077ac <__kernel_rem_pio2+0x36c> 8007708: e59d4004 ldr r4, [sp, #4] 800770c: e3540000 cmp r4, #0 8007710: e2866001 add r6, r6, #1 8007714: d3a04000 movle r4, #0 8007718: da000012 ble 8007768 <__kernel_rem_pio2+0x328> 800771c: e28d3f86 add r3, sp, #536 ; 0x218 8007720: e0831104 add r1, r3, r4, lsl #2 8007724: e3a04000 mov r4, #0 8007728: ea000005 b 8007744 <__kernel_rem_pio2+0x304> 800772c: e3520000 cmp r2, #0 8007730: 12622401 rsbne r2, r2, #16777216 ; 0x1000000 8007734: 15032004 strne r2, [r3, #-4] 8007738: 13a04001 movne r4, #1 800773c: e1530001 cmp r3, r1 8007740: 0a000008 beq 8007768 <__kernel_rem_pio2+0x328> 8007744: e3540000 cmp r4, #0 8007748: e4932004 ldr r2, [r3], #4 800774c: 0afffff6 beq 800772c <__kernel_rem_pio2+0x2ec> 8007750: e3e004ff mvn r0, #-16777216 ; 0xff000000 8007754: e0620000 rsb r0, r2, r0 8007758: e1530001 cmp r3, r1 800775c: e5030004 str r0, [r3, #-4] 8007760: e3a04001 mov r4, #1 8007764: 1afffff6 bne 8007744 <__kernel_rem_pio2+0x304> 8007768: e59dc01c ldr ip, [sp, #28] 800776c: e35c0000 cmp ip, #0 8007770: da00000b ble 80077a4 <__kernel_rem_pio2+0x364> 8007774: e35c0001 cmp ip, #1 8007778: 0a000109 beq 8007ba4 <__kernel_rem_pio2+0x764> 800777c: e35c0002 cmp ip, #2 8007780: 1a000007 bne 80077a4 <__kernel_rem_pio2+0x364> 8007784: e59dc004 ldr ip, [sp, #4] 8007788: e28def9a add lr, sp, #616 ; 0x268 800778c: e24c3001 sub r3, ip, #1 8007790: e08e3103 add r3, lr, r3, lsl #2 8007794: e5132050 ldr r2, [r3, #-80] ; 0x50 8007798: e3c224ff bic r2, r2, #-16777216 ; 0xff000000 800779c: e3c22503 bic r2, r2, #12582912 ; 0xc00000 80077a0: e5032050 str r2, [r3, #-80] ; 0x50 80077a4: e3550002 cmp r5, #2 80077a8: 0a00005c beq 8007920 <__kernel_rem_pio2+0x4e0> 80077ac: e1a00008 mov r0, r8 80077b0: e1a01009 mov r1, r9 80077b4: e3a02000 mov r2, #0 80077b8: e3a03000 mov r3, #0 80077bc: fa00063b blx 80090b0 <__aeabi_dcmpeq> 80077c0: e3500000 cmp r0, #0 80077c4: 0a000070 beq 800798c <__kernel_rem_pio2+0x54c> 80077c8: e59d4004 ldr r4, [sp, #4] 80077cc: e59dc024 ldr ip, [sp, #36] ; 0x24 80077d0: e2440001 sub r0, r4, #1 80077d4: e15c0000 cmp ip, r0 80077d8: ca000009 bgt 8007804 <__kernel_rem_pio2+0x3c4> 80077dc: e28def86 add lr, sp, #536 ; 0x218 80077e0: e59dc030 ldr ip, [sp, #48] ; 0x30 80077e4: e08e3104 add r3, lr, r4, lsl #2 80077e8: e3a02000 mov r2, #0 80077ec: e5331004 ldr r1, [r3, #-4]! 80077f0: e153000c cmp r3, ip 80077f4: e1822001 orr r2, r2, r1 80077f8: 1afffffb bne 80077ec <__kernel_rem_pio2+0x3ac> 80077fc: e3520000 cmp r2, #0 8007800: 1a0001c2 bne 8007f10 <__kernel_rem_pio2+0xad0> 8007804: e59d4034 ldr r4, [sp, #52] ; 0x34 8007808: e5143050 ldr r3, [r4, #-80] ; 0x50 800780c: e3530000 cmp r3, #0 8007810: 13a03001 movne r3, #1 8007814: 1a000007 bne 8007838 <__kernel_rem_pio2+0x3f8> 8007818: e59dc02c ldr ip, [sp, #44] ; 0x2c 800781c: e28def86 add lr, sp, #536 ; 0x218 8007820: e08e200c add r2, lr, ip 8007824: e3a03001 mov r3, #1 8007828: e5321004 ldr r1, [r2, #-4]! 800782c: e3510000 cmp r1, #0 8007830: e2833001 add r3, r3, #1 8007834: 0afffffb beq 8007828 <__kernel_rem_pio2+0x3e8> 8007838: e59d4004 ldr r4, [sp, #4] 800783c: e0843003 add r3, r4, r3 8007840: e284a001 add sl, r4, #1 8007844: e15a0003 cmp sl, r3 8007848: e58d3014 str r3, [sp, #20] 800784c: ca000030 bgt 8007914 <__kernel_rem_pio2+0x4d4> 8007850: e59dc028 ldr ip, [sp, #40] ; 0x28 8007854: e084b00c add fp, r4, ip 8007858: e59d4010 ldr r4, [sp, #16] 800785c: e59dc294 ldr ip, [sp, #660] ; 0x294 8007860: e084300a add r3, r4, sl 8007864: e08cb10b add fp, ip, fp, lsl #2 8007868: e28d4038 add r4, sp, #56 ; 0x38 800786c: e28dcf5e add ip, sp, #376 ; 0x178 8007870: e0844183 add r4, r4, r3, lsl #3 8007874: e08cc18a add ip, ip, sl, lsl #3 8007878: e58d4004 str r4, [sp, #4] 800787c: e58dc008 str ip, [sp, #8] 8007880: e5bb0004 ldr r0, [fp, #4]! 8007884: fa0004a2 blx 8008b14 <__aeabi_i2d> 8007888: e59dc004 ldr ip, [sp, #4] 800788c: e59d4010 ldr r4, [sp, #16] 8007890: e8ac0003 stmia ip!, {r0, r1} 8007894: e3540000 cmp r4, #0 8007898: e58dc004 str ip, [sp, #4] 800789c: b3a08000 movlt r8, #0 80078a0: b3a09000 movlt r9, #0 80078a4: ba000013 blt 80078f8 <__kernel_rem_pio2+0x4b8> 80078a8: e08a6007 add r6, sl, r7 80078ac: e28de038 add lr, sp, #56 ; 0x38 80078b0: e59d5018 ldr r5, [sp, #24] 80078b4: e08e6186 add r6, lr, r6, lsl #3 80078b8: e3a08000 mov r8, #0 80078bc: e3a09000 mov r9, #0 80078c0: e3a04000 mov r4, #0 80078c4: e936000c ldmdb r6!, {r2, r3} 80078c8: e8b50003 ldm r5!, {r0, r1} 80078cc: fa0004c3 blx 8008be0 <__aeabi_dmul> 80078d0: e1a02000 mov r2, r0 80078d4: e1a03001 mov r3, r1 80078d8: e1a00008 mov r0, r8 80078dc: e1a01009 mov r1, r9 80078e0: fa0003e5 blx 800887c <__adddf3> 80078e4: e2844001 add r4, r4, #1 80078e8: e1540007 cmp r4, r7 80078ec: e1a08000 mov r8, r0 80078f0: e1a09001 mov r9, r1 80078f4: 1afffff2 bne 80078c4 <__kernel_rem_pio2+0x484> 80078f8: e59dc008 ldr ip, [sp, #8] 80078fc: e59d4014 ldr r4, [sp, #20] 8007900: e8ac0300 stmia ip!, {r8, r9} 8007904: e28aa001 add sl, sl, #1 8007908: e15a0004 cmp sl, r4 800790c: e58dc008 str ip, [sp, #8] 8007910: daffffda ble 8007880 <__kernel_rem_pio2+0x440> 8007914: e59d4014 ldr r4, [sp, #20] 8007918: e58d4004 str r4, [sp, #4] 800791c: eaffff24 b 80075b4 <__kernel_rem_pio2+0x174> 8007920: e1a02008 mov r2, r8 8007924: e1a03009 mov r3, r9 8007928: e3a00000 mov r0, #0 800792c: e59f1680 ldr r1, [pc, #1664] ; 8007fb4 <__kernel_rem_pio2+0xb74> 8007930: fa0003d0 blx 8008878 <__aeabi_dsub> 8007934: e3540000 cmp r4, #0 8007938: e1a08000 mov r8, r0 800793c: e1a09001 mov r9, r1 8007940: 0affff99 beq 80077ac <__kernel_rem_pio2+0x36c> 8007944: e59d201c ldr r2, [sp, #28] 8007948: e3a00000 mov r0, #0 800794c: e59f1660 ldr r1, [pc, #1632] ; 8007fb4 <__kernel_rem_pio2+0xb74> 8007950: eb000354 bl 80086a8 8007954: e1a02000 mov r2, r0 8007958: e1a03001 mov r3, r1 800795c: e1a00008 mov r0, r8 8007960: e1a01009 mov r1, r9 8007964: fa0003c3 blx 8008878 <__aeabi_dsub> 8007968: e1a08000 mov r8, r0 800796c: e1a09001 mov r9, r1 8007970: e1a00008 mov r0, r8 8007974: e1a01009 mov r1, r9 8007978: e3a02000 mov r2, #0 800797c: e3a03000 mov r3, #0 8007980: fa0005ca blx 80090b0 <__aeabi_dcmpeq> 8007984: e3500000 cmp r0, #0 8007988: 1affff8e bne 80077c8 <__kernel_rem_pio2+0x388> 800798c: e3500000 cmp r0, #0 8007990: e58d6014 str r6, [sp, #20] 8007994: e58d5010 str r5, [sp, #16] 8007998: 1a000175 bne 8007f74 <__kernel_rem_pio2+0xb34> 800799c: e59d401c ldr r4, [sp, #28] 80079a0: e1a00008 mov r0, r8 80079a4: e2642000 rsb r2, r4, #0 80079a8: e1a01009 mov r1, r9 80079ac: eb00033d bl 80086a8 80079b0: e3a02000 mov r2, #0 80079b4: e59f35f0 ldr r3, [pc, #1520] ; 8007fac <__kernel_rem_pio2+0xb6c> 80079b8: e1a04000 mov r4, r0 80079bc: e1a05001 mov r5, r1 80079c0: fa0005c9 blx 80090ec <__aeabi_dcmpge> 80079c4: e3500000 cmp r0, #0 80079c8: 0a00016c beq 8007f80 <__kernel_rem_pio2+0xb40> 80079cc: e3a02000 mov r2, #0 80079d0: e59f35d0 ldr r3, [pc, #1488] ; 8007fa8 <__kernel_rem_pio2+0xb68> 80079d4: e1a00004 mov r0, r4 80079d8: e1a01005 mov r1, r5 80079dc: fa00047f blx 8008be0 <__aeabi_dmul> 80079e0: fa0005cb blx 8009114 <__aeabi_d2iz> 80079e4: fa00044a blx 8008b14 <__aeabi_i2d> 80079e8: e3a02000 mov r2, #0 80079ec: e59f35b8 ldr r3, [pc, #1464] ; 8007fac <__kernel_rem_pio2+0xb6c> 80079f0: e1a06000 mov r6, r0 80079f4: e1a07001 mov r7, r1 80079f8: fa000478 blx 8008be0 <__aeabi_dmul> 80079fc: e1a02000 mov r2, r0 8007a00: e1a03001 mov r3, r1 8007a04: e1a00004 mov r0, r4 8007a08: e1a01005 mov r1, r5 8007a0c: fa000399 blx 8008878 <__aeabi_dsub> 8007a10: fa0005bf blx 8009114 <__aeabi_d2iz> 8007a14: e59dc004 ldr ip, [sp, #4] 8007a18: e28def9a add lr, sp, #616 ; 0x268 8007a1c: e08e310c add r3, lr, ip, lsl #2 8007a20: e5030050 str r0, [r3, #-80] ; 0x50 8007a24: e1a01007 mov r1, r7 8007a28: e1a00006 mov r0, r6 8007a2c: fa0005b8 blx 8009114 <__aeabi_d2iz> 8007a30: e59d4004 ldr r4, [sp, #4] 8007a34: e28dcf9a add ip, sp, #616 ; 0x268 8007a38: e2844001 add r4, r4, #1 8007a3c: e08c3104 add r3, ip, r4, lsl #2 8007a40: e58d4004 str r4, [sp, #4] 8007a44: e59d401c ldr r4, [sp, #28] 8007a48: e2844018 add r4, r4, #24 8007a4c: e58d401c str r4, [sp, #28] 8007a50: e5030050 str r0, [r3, #-80] ; 0x50 8007a54: e3a00000 mov r0, #0 8007a58: e59f1554 ldr r1, [pc, #1364] ; 8007fb4 <__kernel_rem_pio2+0xb74> 8007a5c: e59d201c ldr r2, [sp, #28] 8007a60: eb000310 bl 80086a8 8007a64: e59d4004 ldr r4, [sp, #4] 8007a68: e3540000 cmp r4, #0 8007a6c: e1a06000 mov r6, r0 8007a70: e1a07001 mov r7, r1 8007a74: ba00003b blt 8007b68 <__kernel_rem_pio2+0x728> 8007a78: e2844001 add r4, r4, #1 8007a7c: e28dbf5e add fp, sp, #376 ; 0x178 8007a80: e28dcf86 add ip, sp, #536 ; 0x218 8007a84: e08c5104 add r5, ip, r4, lsl #2 8007a88: e08b4184 add r4, fp, r4, lsl #3 8007a8c: e5350004 ldr r0, [r5, #-4]! 8007a90: fa00041f blx 8008b14 <__aeabi_i2d> 8007a94: e1a02006 mov r2, r6 8007a98: e1a03007 mov r3, r7 8007a9c: fa00044f blx 8008be0 <__aeabi_dmul> 8007aa0: e3a02000 mov r2, #0 8007aa4: e9240003 stmdb r4!, {r0, r1} 8007aa8: e59f34f8 ldr r3, [pc, #1272] ; 8007fa8 <__kernel_rem_pio2+0xb68> 8007aac: e1a00006 mov r0, r6 8007ab0: e1a01007 mov r1, r7 8007ab4: fa000449 blx 8008be0 <__aeabi_dmul> 8007ab8: e154000b cmp r4, fp 8007abc: e1a06000 mov r6, r0 8007ac0: e1a07001 mov r7, r1 8007ac4: 1afffff0 bne 8007a8c <__kernel_rem_pio2+0x64c> 8007ac8: e59da004 ldr sl, [sp, #4] 8007acc: e59d8024 ldr r8, [sp, #36] ; 0x24 8007ad0: e58da008 str sl, [sp, #8] 8007ad4: e3a07000 mov r7, #0 8007ad8: e3580000 cmp r8, #0 8007adc: b3a09000 movlt r9, #0 8007ae0: b3a0a000 movlt sl, #0 8007ae4: ba000015 blt 8007b40 <__kernel_rem_pio2+0x700> 8007ae8: e59d4008 ldr r4, [sp, #8] 8007aec: e59f54c4 ldr r5, [pc, #1220] ; 8007fb8 <__kernel_rem_pio2+0xb78> 8007af0: e08b6184 add r6, fp, r4, lsl #3 8007af4: e3a09000 mov r9, #0 8007af8: e3a0a000 mov sl, #0 8007afc: e3a04000 mov r4, #0 8007b00: ea000001 b 8007b0c <__kernel_rem_pio2+0x6cc> 8007b04: e1540007 cmp r4, r7 8007b08: ca00000c bgt 8007b40 <__kernel_rem_pio2+0x700> 8007b0c: e8b6000c ldm r6!, {r2, r3} 8007b10: e8b50003 ldm r5!, {r0, r1} 8007b14: fa000431 blx 8008be0 <__aeabi_dmul> 8007b18: e1a02000 mov r2, r0 8007b1c: e1a03001 mov r3, r1 8007b20: e1a00009 mov r0, r9 8007b24: e1a0100a mov r1, sl 8007b28: fa000353 blx 800887c <__adddf3> 8007b2c: e2844001 add r4, r4, #1 8007b30: e1580004 cmp r8, r4 8007b34: e1a09000 mov r9, r0 8007b38: e1a0a001 mov sl, r1 8007b3c: aafffff0 bge 8007b04 <__kernel_rem_pio2+0x6c4> 8007b40: e59d4008 ldr r4, [sp, #8] 8007b44: e28dcf9a add ip, sp, #616 ; 0x268 8007b48: e2444001 sub r4, r4, #1 8007b4c: e08c3187 add r3, ip, r7, lsl #3 8007b50: e3740001 cmn r4, #1 8007b54: e58d4008 str r4, [sp, #8] 8007b58: e5039190 str r9, [r3, #-400] ; 0x190 8007b5c: e503a18c str sl, [r3, #-396] ; 0x18c 8007b60: e2877001 add r7, r7, #1 8007b64: 1affffdb bne 8007ad8 <__kernel_rem_pio2+0x698> 8007b68: e59dc290 ldr ip, [sp, #656] ; 0x290 8007b6c: e35c0003 cmp ip, #3 8007b70: 979ff10c ldrls pc, [pc, ip, lsl #2] 8007b74: ea00002e b 8007c34 <__kernel_rem_pio2+0x7f4> 8007b78: 08007ea4 .word 0x08007ea4 8007b7c: 08007dc4 .word 0x08007dc4 8007b80: 08007dc4 .word 0x08007dc4 8007b84: 08007c48 .word 0x08007c48 8007b88: 1a00000e bne 8007bc8 <__kernel_rem_pio2+0x788> 8007b8c: e59d4004 ldr r4, [sp, #4] 8007b90: e28dcf9a add ip, sp, #616 ; 0x268 8007b94: e08c3104 add r3, ip, r4, lsl #2 8007b98: e5135054 ldr r5, [r3, #-84] ; 0x54 8007b9c: e1a05bc5 asr r5, r5, #23 8007ba0: eafffed6 b 8007700 <__kernel_rem_pio2+0x2c0> 8007ba4: e59dc004 ldr ip, [sp, #4] 8007ba8: e28def9a add lr, sp, #616 ; 0x268 8007bac: e24c3001 sub r3, ip, #1 8007bb0: e08e3103 add r3, lr, r3, lsl #2 8007bb4: e5132050 ldr r2, [r3, #-80] ; 0x50 8007bb8: e3c224ff bic r2, r2, #-16777216 ; 0xff000000 8007bbc: e3c22502 bic r2, r2, #8388608 ; 0x800000 8007bc0: e5032050 str r2, [r3, #-80] ; 0x50 8007bc4: eafffef6 b 80077a4 <__kernel_rem_pio2+0x364> 8007bc8: e3a02000 mov r2, #0 8007bcc: e59f33e8 ldr r3, [pc, #1000] ; 8007fbc <__kernel_rem_pio2+0xb7c> 8007bd0: fa000545 blx 80090ec <__aeabi_dcmpge> 8007bd4: e3500000 cmp r0, #0 8007bd8: 03a05000 moveq r5, #0 8007bdc: 0afffef2 beq 80077ac <__kernel_rem_pio2+0x36c> 8007be0: e3a05002 mov r5, #2 8007be4: eafffec7 b 8007708 <__kernel_rem_pio2+0x2c8> 8007be8: e59d4010 ldr r4, [sp, #16] 8007bec: e3a03000 mov r3, #0 8007bf0: e3540000 cmp r4, #0 8007bf4: e1a02003 mov r2, r3 8007bf8: 0a000064 beq 8007d90 <__kernel_rem_pio2+0x950> 8007bfc: e59d00dc ldr r0, [sp, #220] ; 0xdc 8007c00: e59d4020 ldr r4, [sp, #32] 8007c04: e2800102 add r0, r0, #-2147483648 ; 0x80000000 8007c08: e59d10e4 ldr r1, [sp, #228] ; 0xe4 8007c0c: e59dc0d8 ldr ip, [sp, #216] ; 0xd8 8007c10: e5840004 str r0, [r4, #4] 8007c14: e59d00e0 ldr r0, [sp, #224] ; 0xe0 8007c18: e2811102 add r1, r1, #-2147483648 ; 0x80000000 8007c1c: e2822102 add r2, r2, #-2147483648 ; 0x80000000 8007c20: e584c000 str ip, [r4] 8007c24: e5840008 str r0, [r4, #8] 8007c28: e584100c str r1, [r4, #12] 8007c2c: e5843010 str r3, [r4, #16] 8007c30: e5842014 str r2, [r4, #20] 8007c34: e59dc014 ldr ip, [sp, #20] 8007c38: e20c0007 and r0, ip, #7 8007c3c: e28ddf9b add sp, sp, #620 ; 0x26c 8007c40: e8bd4ff0 pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8007c44: e12fff1e bx lr 8007c48: e59d4004 ldr r4, [sp, #4] 8007c4c: e3540000 cmp r4, #0 8007c50: daffffe4 ble 8007be8 <__kernel_rem_pio2+0x7a8> 8007c54: e59d4004 ldr r4, [sp, #4] 8007c58: e28d60d8 add r6, sp, #216 ; 0xd8 8007c5c: e0865184 add r5, r6, r4, lsl #3 8007c60: e1a04005 mov r4, r5 8007c64: e9340300 ldmdb r4!, {r8, r9} 8007c68: e284b008 add fp, r4, #8 8007c6c: e89b0c00 ldm fp, {sl, fp} 8007c70: e1a00008 mov r0, r8 8007c74: e1a0200a mov r2, sl 8007c78: e1a0300b mov r3, fp 8007c7c: e1a01009 mov r1, r9 8007c80: fa0002fd blx 800887c <__adddf3> 8007c84: e58d0008 str r0, [sp, #8] 8007c88: e58d100c str r1, [sp, #12] 8007c8c: e28d3008 add r3, sp, #8 8007c90: e893000c ldm r3, {r2, r3} 8007c94: e1a00008 mov r0, r8 8007c98: e1a01009 mov r1, r9 8007c9c: fa0002f5 blx 8008878 <__aeabi_dsub> 8007ca0: e1a02000 mov r2, r0 8007ca4: e1a03001 mov r3, r1 8007ca8: e1a0000a mov r0, sl 8007cac: e1a0100b mov r1, fp 8007cb0: fa0002f1 blx 800887c <__adddf3> 8007cb4: e5840008 str r0, [r4, #8] 8007cb8: e584100c str r1, [r4, #12] 8007cbc: e28d1008 add r1, sp, #8 8007cc0: e8910003 ldm r1, {r0, r1} 8007cc4: e1540006 cmp r4, r6 8007cc8: e8840003 stm r4, {r0, r1} 8007ccc: 1affffe4 bne 8007c64 <__kernel_rem_pio2+0x824> 8007cd0: e59d4004 ldr r4, [sp, #4] 8007cd4: e3540001 cmp r4, #1 8007cd8: daffffc2 ble 8007be8 <__kernel_rem_pio2+0x7a8> 8007cdc: e2864008 add r4, r6, #8 8007ce0: e9350300 ldmdb r5!, {r8, r9} 8007ce4: e285b008 add fp, r5, #8 8007ce8: e89b0c00 ldm fp, {sl, fp} 8007cec: e1a00008 mov r0, r8 8007cf0: e1a0200a mov r2, sl 8007cf4: e1a0300b mov r3, fp 8007cf8: e1a01009 mov r1, r9 8007cfc: fa0002de blx 800887c <__adddf3> 8007d00: e58d0008 str r0, [sp, #8] 8007d04: e58d100c str r1, [sp, #12] 8007d08: e28d3008 add r3, sp, #8 8007d0c: e893000c ldm r3, {r2, r3} 8007d10: e1a00008 mov r0, r8 8007d14: e1a01009 mov r1, r9 8007d18: fa0002d6 blx 8008878 <__aeabi_dsub> 8007d1c: e1a02000 mov r2, r0 8007d20: e1a03001 mov r3, r1 8007d24: e1a0000a mov r0, sl 8007d28: e1a0100b mov r1, fp 8007d2c: fa0002d2 blx 800887c <__adddf3> 8007d30: e5850008 str r0, [r5, #8] 8007d34: e585100c str r1, [r5, #12] 8007d38: e28d1008 add r1, sp, #8 8007d3c: e8910003 ldm r1, {r0, r1} 8007d40: e1550004 cmp r5, r4 8007d44: e8850003 stm r5, {r0, r1} 8007d48: 1affffe4 bne 8007ce0 <__kernel_rem_pio2+0x8a0> 8007d4c: e59dc004 ldr ip, [sp, #4] 8007d50: e3a03000 mov r3, #0 8007d54: e28c4001 add r4, ip, #1 8007d58: e0864184 add r4, r6, r4, lsl #3 8007d5c: e1a02003 mov r2, r3 8007d60: e2866010 add r6, r6, #16 8007d64: e1a00003 mov r0, r3 8007d68: e1a01002 mov r1, r2 8007d6c: e934000c ldmdb r4!, {r2, r3} 8007d70: fa0002c1 blx 800887c <__adddf3> 8007d74: e1540006 cmp r4, r6 8007d78: e1a03000 mov r3, r0 8007d7c: e1a02001 mov r2, r1 8007d80: 1afffff7 bne 8007d64 <__kernel_rem_pio2+0x924> 8007d84: e59d4010 ldr r4, [sp, #16] 8007d88: e3540000 cmp r4, #0 8007d8c: 1affff9a bne 8007bfc <__kernel_rem_pio2+0x7bc> 8007d90: e59dc020 ldr ip, [sp, #32] 8007d94: e1a00003 mov r0, r3 8007d98: e1a01002 mov r1, r2 8007d9c: e28d30d8 add r3, sp, #216 ; 0xd8 8007da0: e893000c ldm r3, {r2, r3} 8007da4: e88c000c stm ip, {r2, r3} 8007da8: e28d30e0 add r3, sp, #224 ; 0xe0 8007dac: e893000c ldm r3, {r2, r3} 8007db0: e58c0010 str r0, [ip, #16] 8007db4: e58c1014 str r1, [ip, #20] 8007db8: e58c2008 str r2, [ip, #8] 8007dbc: e58c300c str r3, [ip, #12] 8007dc0: eaffff9b b 8007c34 <__kernel_rem_pio2+0x7f4> 8007dc4: e59dc004 ldr ip, [sp, #4] 8007dc8: e35c0000 cmp ip, #0 8007dcc: b3a02000 movlt r2, #0 8007dd0: b1a03002 movlt r3, r2 8007dd4: ba00000d blt 8007e10 <__kernel_rem_pio2+0x9d0> 8007dd8: e59dc004 ldr ip, [sp, #4] 8007ddc: e28d50d8 add r5, sp, #216 ; 0xd8 8007de0: e28c4001 add r4, ip, #1 8007de4: e3a02000 mov r2, #0 8007de8: e0854184 add r4, r5, r4, lsl #3 8007dec: e1a03002 mov r3, r2 8007df0: e1a00002 mov r0, r2 8007df4: e1a01003 mov r1, r3 8007df8: e934000c ldmdb r4!, {r2, r3} 8007dfc: fa00029e blx 800887c <__adddf3> 8007e00: e1540005 cmp r4, r5 8007e04: e1a02000 mov r2, r0 8007e08: e1a03001 mov r3, r1 8007e0c: 1afffff7 bne 8007df0 <__kernel_rem_pio2+0x9b0> 8007e10: e59d4010 ldr r4, [sp, #16] 8007e14: e3540000 cmp r4, #0 8007e18: 1283c102 addne ip, r3, #-2147483648 ; 0x80000000 8007e1c: 01a0c003 moveq ip, r3 8007e20: e1a0100c mov r1, ip 8007e24: e59dc020 ldr ip, [sp, #32] 8007e28: e1a00002 mov r0, r2 8007e2c: e88c0003 stm ip, {r0, r1} 8007e30: e28d10d8 add r1, sp, #216 ; 0xd8 8007e34: e8910003 ldm r1, {r0, r1} 8007e38: e1a05003 mov r5, r3 8007e3c: fa00028d blx 8008878 <__aeabi_dsub> 8007e40: e59d4004 ldr r4, [sp, #4] 8007e44: e3540000 cmp r4, #0 8007e48: e1a02000 mov r2, r0 8007e4c: e1a03001 mov r3, r1 8007e50: da00000a ble 8007e80 <__kernel_rem_pio2+0xa40> 8007e54: e59dc004 ldr ip, [sp, #4] 8007e58: e28d40e0 add r4, sp, #224 ; 0xe0 8007e5c: e084518c add r5, r4, ip, lsl #3 8007e60: e1a00002 mov r0, r2 8007e64: e1a01003 mov r1, r3 8007e68: e8b4000c ldm r4!, {r2, r3} 8007e6c: fa000282 blx 800887c <__adddf3> 8007e70: e1540005 cmp r4, r5 8007e74: e1a02000 mov r2, r0 8007e78: e1a03001 mov r3, r1 8007e7c: 1afffff7 bne 8007e60 <__kernel_rem_pio2+0xa20> 8007e80: e59d4010 ldr r4, [sp, #16] 8007e84: e3540000 cmp r4, #0 8007e88: 12833102 addne r3, r3, #-2147483648 ; 0x80000000 8007e8c: e59dc020 ldr ip, [sp, #32] 8007e90: e1a00002 mov r0, r2 8007e94: e1a01003 mov r1, r3 8007e98: e58c0008 str r0, [ip, #8] 8007e9c: e58c100c str r1, [ip, #12] 8007ea0: eaffff63 b 8007c34 <__kernel_rem_pio2+0x7f4> 8007ea4: e59d4004 ldr r4, [sp, #4] 8007ea8: e3540000 cmp r4, #0 8007eac: b3a02000 movlt r2, #0 8007eb0: b1a03002 movlt r3, r2 8007eb4: ba00000d blt 8007ef0 <__kernel_rem_pio2+0xab0> 8007eb8: e59dc004 ldr ip, [sp, #4] 8007ebc: e28d40d8 add r4, sp, #216 ; 0xd8 8007ec0: e28c5001 add r5, ip, #1 8007ec4: e3a02000 mov r2, #0 8007ec8: e0845185 add r5, r4, r5, lsl #3 8007ecc: e1a03002 mov r3, r2 8007ed0: e1a00002 mov r0, r2 8007ed4: e1a01003 mov r1, r3 8007ed8: e935000c ldmdb r5!, {r2, r3} 8007edc: fa000266 blx 800887c <__adddf3> 8007ee0: e1550004 cmp r5, r4 8007ee4: e1a02000 mov r2, r0 8007ee8: e1a03001 mov r3, r1 8007eec: 1afffff7 bne 8007ed0 <__kernel_rem_pio2+0xa90> 8007ef0: e59d4010 ldr r4, [sp, #16] 8007ef4: e3540000 cmp r4, #0 8007ef8: 12833102 addne r3, r3, #-2147483648 ; 0x80000000 8007efc: e59dc020 ldr ip, [sp, #32] 8007f00: e1a00002 mov r0, r2 8007f04: e1a01003 mov r1, r3 8007f08: e88c0003 stm ip, {r0, r1} 8007f0c: eaffff48 b 8007c34 <__kernel_rem_pio2+0x7f4> 8007f10: e58d6014 str r6, [sp, #20] 8007f14: e58d5010 str r5, [sp, #16] 8007f18: e1a03100 lsl r3, r0, #2 8007f1c: e28def9a add lr, sp, #616 ; 0x268 8007f20: e08e2003 add r2, lr, r3 8007f24: e59d401c ldr r4, [sp, #28] 8007f28: e5122050 ldr r2, [r2, #-80] ; 0x50 8007f2c: e2444018 sub r4, r4, #24 8007f30: e3520000 cmp r2, #0 8007f34: e58d401c str r4, [sp, #28] 8007f38: 158d0004 strne r0, [sp, #4] 8007f3c: 1afffec4 bne 8007a54 <__kernel_rem_pio2+0x614> 8007f40: e28dcf86 add ip, sp, #536 ; 0x218 8007f44: e58d0004 str r0, [sp, #4] 8007f48: e08c3003 add r3, ip, r3 8007f4c: e1a02000 mov r2, r0 8007f50: e1a01004 mov r1, r4 8007f54: e5330004 ldr r0, [r3, #-4]! 8007f58: e3500000 cmp r0, #0 8007f5c: e2422001 sub r2, r2, #1 8007f60: e2411018 sub r1, r1, #24 8007f64: 0afffffa beq 8007f54 <__kernel_rem_pio2+0xb14> 8007f68: e58d2004 str r2, [sp, #4] 8007f6c: e58d101c str r1, [sp, #28] 8007f70: eafffeb7 b 8007a54 <__kernel_rem_pio2+0x614> 8007f74: e59dc004 ldr ip, [sp, #4] 8007f78: e24c0001 sub r0, ip, #1 8007f7c: eaffffe5 b 8007f18 <__kernel_rem_pio2+0xad8> 8007f80: e1a00004 mov r0, r4 8007f84: e1a01005 mov r1, r5 8007f88: fa000461 blx 8009114 <__aeabi_d2iz> 8007f8c: e59dc004 ldr ip, [sp, #4] 8007f90: e28def9a add lr, sp, #616 ; 0x268 8007f94: e08e310c add r3, lr, ip, lsl #2 8007f98: e5030050 str r0, [r3, #-80] ; 0x50 8007f9c: eafffeac b 8007a54 <__kernel_rem_pio2+0x614> 8007fa0: 2aaaaaab .word 0x2aaaaaab 8007fa4: 0800af44 .word 0x0800af44 8007fa8: 3e700000 .word 0x3e700000 8007fac: 41700000 .word 0x41700000 8007fb0: 40200000 .word 0x40200000 8007fb4: 3ff00000 .word 0x3ff00000 8007fb8: 0800af58 .word 0x0800af58 8007fbc: 3fe00000 .word 0x3fe00000 08007fc0 <__kernel_sin>: 8007fc0: e92d4ff0 push {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8007fc4: e3c1c102 bic ip, r1, #-2147483648 ; 0x80000000 8007fc8: e35c05f9 cmp ip, #1044381696 ; 0x3e400000 8007fcc: e24dd014 sub sp, sp, #20 8007fd0: e1a06000 mov r6, r0 8007fd4: e1a07001 mov r7, r1 8007fd8: e1a04000 mov r4, r0 8007fdc: e1a05001 mov r5, r1 8007fe0: e1a08002 mov r8, r2 8007fe4: e1a09003 mov r9, r3 8007fe8: aa000002 bge 8007ff8 <__kernel_sin+0x38> 8007fec: fa000448 blx 8009114 <__aeabi_d2iz> 8007ff0: e3500000 cmp r0, #0 8007ff4: 0a000052 beq 8008144 <__kernel_sin+0x184> 8007ff8: e1a02006 mov r2, r6 8007ffc: e1a03007 mov r3, r7 8008000: e1a00006 mov r0, r6 8008004: e1a01007 mov r1, r7 8008008: fa0002f4 blx 8008be0 <__aeabi_dmul> 800800c: e1a02006 mov r2, r6 8008010: e1a03007 mov r3, r7 8008014: e1a04000 mov r4, r0 8008018: e1a05001 mov r5, r1 800801c: fa0002ef blx 8008be0 <__aeabi_dmul> 8008020: e28f3d06 add r3, pc, #384 ; 0x180 8008024: e893000c ldm r3, {r2, r3} 8008028: e1a0a000 mov sl, r0 800802c: e1a0b001 mov fp, r1 8008030: e1a00004 mov r0, r4 8008034: e1a01005 mov r1, r5 8008038: fa0002e8 blx 8008be0 <__aeabi_dmul> 800803c: e28f3f5b add r3, pc, #364 ; 0x16c 8008040: e893000c ldm r3, {r2, r3} 8008044: fa00020b blx 8008878 <__aeabi_dsub> 8008048: e1a02004 mov r2, r4 800804c: e1a03005 mov r3, r5 8008050: fa0002e2 blx 8008be0 <__aeabi_dmul> 8008054: e28f3f57 add r3, pc, #348 ; 0x15c 8008058: e893000c ldm r3, {r2, r3} 800805c: fa000206 blx 800887c <__adddf3> 8008060: e1a02004 mov r2, r4 8008064: e1a03005 mov r3, r5 8008068: fa0002dc blx 8008be0 <__aeabi_dmul> 800806c: e28f3f53 add r3, pc, #332 ; 0x14c 8008070: e893000c ldm r3, {r2, r3} 8008074: fa0001ff blx 8008878 <__aeabi_dsub> 8008078: e1a02004 mov r2, r4 800807c: e1a03005 mov r3, r5 8008080: fa0002d6 blx 8008be0 <__aeabi_dmul> 8008084: e28f3f4f add r3, pc, #316 ; 0x13c 8008088: e893000c ldm r3, {r2, r3} 800808c: fa0001fa blx 800887c <__adddf3> 8008090: e59d3038 ldr r3, [sp, #56] ; 0x38 8008094: e3530000 cmp r3, #0 8008098: e88d0003 stm sp, {r0, r1} 800809c: 0a00002d beq 8008158 <__kernel_sin+0x198> 80080a0: e3a02000 mov r2, #0 80080a4: e59f312c ldr r3, [pc, #300] ; 80081d8 <__kernel_sin+0x218> 80080a8: e1a00008 mov r0, r8 80080ac: e1a01009 mov r1, r9 80080b0: fa0002ca blx 8008be0 <__aeabi_dmul> 80080b4: e89d000c ldm sp, {r2, r3} 80080b8: e58d0008 str r0, [sp, #8] 80080bc: e58d100c str r1, [sp, #12] 80080c0: e1a0000a mov r0, sl 80080c4: e1a0100b mov r1, fp 80080c8: fa0002c4 blx 8008be0 <__aeabi_dmul> 80080cc: e1a02000 mov r2, r0 80080d0: e1a03001 mov r3, r1 80080d4: e28d1008 add r1, sp, #8 80080d8: e8910003 ldm r1, {r0, r1} 80080dc: fa0001e5 blx 8008878 <__aeabi_dsub> 80080e0: e1a02004 mov r2, r4 80080e4: e1a03005 mov r3, r5 80080e8: fa0002bc blx 8008be0 <__aeabi_dmul> 80080ec: e1a02008 mov r2, r8 80080f0: e1a03009 mov r3, r9 80080f4: fa0001df blx 8008878 <__aeabi_dsub> 80080f8: e28f30d0 add r3, pc, #208 ; 0xd0 80080fc: e893000c ldm r3, {r2, r3} 8008100: e1a04000 mov r4, r0 8008104: e1a05001 mov r5, r1 8008108: e1a0000a mov r0, sl 800810c: e1a0100b mov r1, fp 8008110: fa0002b2 blx 8008be0 <__aeabi_dmul> 8008114: e1a02000 mov r2, r0 8008118: e1a03001 mov r3, r1 800811c: e1a00004 mov r0, r4 8008120: e1a01005 mov r1, r5 8008124: fa0001d4 blx 800887c <__adddf3> 8008128: e1a02000 mov r2, r0 800812c: e1a03001 mov r3, r1 8008130: e1a00006 mov r0, r6 8008134: e1a01007 mov r1, r7 8008138: fa0001ce blx 8008878 <__aeabi_dsub> 800813c: e1a06000 mov r6, r0 8008140: e1a07001 mov r7, r1 8008144: e1a00006 mov r0, r6 8008148: e1a01007 mov r1, r7 800814c: e28dd014 add sp, sp, #20 8008150: e8bd4ff0 pop {r4, r5, r6, r7, r8, r9, sl, fp, lr} 8008154: e12fff1e bx lr 8008158: e1a02000 mov r2, r0 800815c: e1a03001 mov r3, r1 8008160: e1a00004 mov r0, r4 8008164: e1a01005 mov r1, r5 8008168: fa00029c blx 8008be0 <__aeabi_dmul> 800816c: e28f305c add r3, pc, #92 ; 0x5c 8008170: e893000c ldm r3, {r2, r3} 8008174: fa0001bf blx 8008878 <__aeabi_dsub> 8008178: e1a0200a mov r2, sl 800817c: e1a0300b mov r3, fp 8008180: fa000296 blx 8008be0 <__aeabi_dmul> 8008184: e1a02000 mov r2, r0 8008188: e1a03001 mov r3, r1 800818c: e1a00006 mov r0, r6 8008190: e1a01007 mov r1, r7 8008194: fa0001b8 blx 800887c <__adddf3> 8008198: e1a06000 mov r6, r0 800819c: e1a07001 mov r7, r1 80081a0: eaffffe7 b 8008144 <__kernel_sin+0x184> 80081a4: e1a00000 nop ; (mov r0, r0) 80081a8: 5acfd57c .word 0x5acfd57c 80081ac: 3de5d93a .word 0x3de5d93a 80081b0: 8a2b9ceb .word 0x8a2b9ceb 80081b4: 3e5ae5e6 .word 0x3e5ae5e6 80081b8: 57b1fe7d .word 0x57b1fe7d 80081bc: 3ec71de3 .word 0x3ec71de3 80081c0: 19c161d5 .word 0x19c161d5 80081c4: 3f2a01a0 .word 0x3f2a01a0 80081c8: 1110f8a6 .word 0x1110f8a6 80081cc: 3f811111 .word 0x3f811111 80081d0: 55555549 .word 0x55555549 80081d4: 3fc55555 .word 0x3fc55555 80081d8: 3fe00000 .word 0x3fe00000 80081dc: e1a00000 nop ; (mov r0, r0) 080081e0 : 80081e0: e92d4df0 push {r4, r5, r6, r7, r8, sl, fp, lr} 80081e4: e59f345c ldr r3, [pc, #1116] ; 8008648 80081e8: e3c16102 bic r6, r1, #-2147483648 ; 0x80000000 80081ec: e1560003 cmp r6, r3 80081f0: e24dd010 sub sp, sp, #16 80081f4: e1a04001 mov r4, r1 80081f8: e1a08001 mov r8, r1 80081fc: e1a05000 mov r5, r0 8008200: da00000f ble 8008244 8008204: e59f2440 ldr r2, [pc, #1088] ; 800864c 8008208: e1560002 cmp r6, r2 800820c: ca00007d bgt 8008408 8008210: 13a02000 movne r2, #0 8008214: 03a02001 moveq r2, #1 8008218: e3500000 cmp r0, #0 800821c: 03a03000 moveq r3, #0 8008220: 12023001 andne r3, r2, #1 8008224: e3530000 cmp r3, #0 8008228: 1a000076 bne 8008408 800822c: e59f341c ldr r3, [pc, #1052] ; 8008650 8008230: e3510000 cmp r1, #0 8008234: e59f4418 ldr r4, [pc, #1048] ; 8008654 8008238: e59f5418 ldr r5, [pc, #1048] ; 8008658 800823c: c1a04003 movgt r4, r3 8008240: ea000077 b 8008424 8008244: e59f3410 ldr r3, [pc, #1040] ; 800865c 8008248: e1560003 cmp r6, r3 800824c: ca000082 bgt 800845c 8008250: e243376f sub r3, r3, #29097984 ; 0x1bc0000 8008254: e1560003 cmp r6, r3 8008258: da000076 ble 8008438 800825c: e3e0a000 mvn sl, #0 8008260: e1a02005 mov r2, r5 8008264: e1a03004 mov r3, r4 8008268: e1a00005 mov r0, r5 800826c: e1a01004 mov r1, r4 8008270: fa00025a blx 8008be0 <__aeabi_dmul> 8008274: e1a02000 mov r2, r0 8008278: e1a03001 mov r3, r1 800827c: e1a0b000 mov fp, r0 8008280: e58d1004 str r1, [sp, #4] 8008284: fa000255 blx 8008be0 <__aeabi_dmul> 8008288: e28f3fd6 add r3, pc, #856 ; 0x358 800828c: e893000c ldm r3, {r2, r3} 8008290: e1a06000 mov r6, r0 8008294: e1a07001 mov r7, r1 8008298: fa000250 blx 8008be0 <__aeabi_dmul> 800829c: e28f3fd3 add r3, pc, #844 ; 0x34c 80082a0: e893000c ldm r3, {r2, r3} 80082a4: fa000174 blx 800887c <__adddf3> 80082a8: e1a02006 mov r2, r6 80082ac: e1a03007 mov r3, r7 80082b0: fa00024a blx 8008be0 <__aeabi_dmul> 80082b4: e28f3fcf add r3, pc, #828 ; 0x33c 80082b8: e893000c ldm r3, {r2, r3} 80082bc: fa00016e blx 800887c <__adddf3> 80082c0: e1a02006 mov r2, r6 80082c4: e1a03007 mov r3, r7 80082c8: fa000244 blx 8008be0 <__aeabi_dmul> 80082cc: e28f3fcb add r3, pc, #812 ; 0x32c 80082d0: e893000c ldm r3, {r2, r3} 80082d4: fa000168 blx 800887c <__adddf3> 80082d8: e1a02006 mov r2, r6 80082dc: e1a03007 mov r3, r7 80082e0: fa00023e blx 8008be0 <__aeabi_dmul> 80082e4: e28f3fc7 add r3, pc, #796 ; 0x31c 80082e8: e893000c ldm r3, {r2, r3} 80082ec: fa000162 blx 800887c <__adddf3> 80082f0: e1a02006 mov r2, r6 80082f4: e1a03007 mov r3, r7 80082f8: fa000238 blx 8008be0 <__aeabi_dmul> 80082fc: e28f3fc3 add r3, pc, #780 ; 0x30c 8008300: e893000c ldm r3, {r2, r3} 8008304: fa00015c blx 800887c <__adddf3> 8008308: e59dc004 ldr ip, [sp, #4] 800830c: e1a0200b mov r2, fp 8008310: e1a0300c mov r3, ip 8008314: fa000231 blx 8008be0 <__aeabi_dmul> 8008318: e28f3fbe add r3, pc, #760 ; 0x2f8 800831c: e893000c ldm r3, {r2, r3} 8008320: e58d0008 str r0, [sp, #8] 8008324: e58d100c str r1, [sp, #12] 8008328: e1a00006 mov r0, r6 800832c: e1a01007 mov r1, r7 8008330: fa00022a blx 8008be0 <__aeabi_dmul> 8008334: e28f3fb9 add r3, pc, #740 ; 0x2e4 8008338: e893000c ldm r3, {r2, r3} 800833c: fa00014d blx 8008878 <__aeabi_dsub> 8008340: e1a02006 mov r2, r6 8008344: e1a03007 mov r3, r7 8008348: fa000224 blx 8008be0 <__aeabi_dmul> 800834c: e28f3fb5 add r3, pc, #724 ; 0x2d4 8008350: e893000c ldm r3, {r2, r3} 8008354: fa000147 blx 8008878 <__aeabi_dsub> 8008358: e1a02006 mov r2, r6 800835c: e1a03007 mov r3, r7 8008360: fa00021e blx 8008be0 <__aeabi_dmul> 8008364: e28f3fb1 add r3, pc, #708 ; 0x2c4 8008368: e893000c ldm r3, {r2, r3} 800836c: fa000141 blx 8008878 <__aeabi_dsub> 8008370: e1a02006 mov r2, r6 8008374: e1a03007 mov r3, r7 8008378: fa000218 blx 8008be0 <__aeabi_dmul> 800837c: e28f3fad add r3, pc, #692 ; 0x2b4 8008380: e893000c ldm r3, {r2, r3} 8008384: fa00013b blx 8008878 <__aeabi_dsub> 8008388: e1a02006 mov r2, r6 800838c: e1a03007 mov r3, r7 8008390: fa000212 blx 8008be0 <__aeabi_dmul> 8008394: e37a0001 cmn sl, #1 8008398: e1a02000 mov r2, r0 800839c: e1a03001 mov r3, r1 80083a0: 0a00004c beq 80084d8 80083a4: e28d1008 add r1, sp, #8 80083a8: e8910003 ldm r1, {r0, r1} 80083ac: fa000132 blx 800887c <__adddf3> 80083b0: e1a02005 mov r2, r5 80083b4: e1a03004 mov r3, r4 80083b8: fa000208 blx 8008be0 <__aeabi_dmul> 80083bc: e59f729c ldr r7, [pc, #668] ; 8008660 80083c0: e59f329c ldr r3, [pc, #668] ; 8008664 80083c4: e1a0618a lsl r6, sl, #3 80083c8: e0877006 add r7, r7, r6 80083cc: e0836006 add r6, r3, r6 80083d0: e896000c ldm r6, {r2, r3} 80083d4: fa000127 blx 8008878 <__aeabi_dsub> 80083d8: e1a02005 mov r2, r5 80083dc: e1a03004 mov r3, r4 80083e0: fa000124 blx 8008878 <__aeabi_dsub> 80083e4: e1a02000 mov r2, r0 80083e8: e1a03001 mov r3, r1 80083ec: e8970003 ldm r7, {r0, r1} 80083f0: fa000120 blx 8008878 <__aeabi_dsub> 80083f4: e3580000 cmp r8, #0 80083f8: e1a04001 mov r4, r1 80083fc: e1a05000 mov r5, r0 8008400: b2814102 addlt r4, r1, #-2147483648 ; 0x80000000 8008404: ea000006 b 8008424 8008408: e1a00005 mov r0, r5 800840c: e1a02005 mov r2, r5 8008410: e1a01004 mov r1, r4 8008414: e1a03004 mov r3, r4 8008418: fa000117 blx 800887c <__adddf3> 800841c: e1a05000 mov r5, r0 8008420: e1a04001 mov r4, r1 8008424: e1a00005 mov r0, r5 8008428: e1a01004 mov r1, r4 800842c: e28dd010 add sp, sp, #16 8008430: e8bd4df0 pop {r4, r5, r6, r7, r8, sl, fp, lr} 8008434: e12fff1e bx lr 8008438: e28f3c02 add r3, pc, #512 ; 0x200 800843c: e893000c ldm r3, {r2, r3} 8008440: fa00010d blx 800887c <__adddf3> 8008444: e3a02000 mov r2, #0 8008448: e59f3218 ldr r3, [pc, #536] ; 8008668 800844c: fa00032b blx 8009100 <__aeabi_dcmpgt> 8008450: e3500000 cmp r0, #0 8008454: 0affff80 beq 800825c 8008458: eafffff1 b 8008424 800845c: eb000087 bl 8008680 8008460: e59f3204 ldr r3, [pc, #516] ; 800866c 8008464: e1560003 cmp r6, r3 8008468: e1a04000 mov r4, r0 800846c: e1a05001 mov r5, r1 8008470: ca000026 bgt 8008510 8008474: e243380d sub r3, r3, #851968 ; 0xd0000 8008478: e1560003 cmp r6, r3 800847c: ca000045 bgt 8008598 8008480: e1a02000 mov r2, r0 8008484: e1a03001 mov r3, r1 8008488: fa0000fb blx 800887c <__adddf3> 800848c: e3a02000 mov r2, #0 8008490: e59f31d0 ldr r3, [pc, #464] ; 8008668 8008494: fa0000f7 blx 8008878 <__aeabi_dsub> 8008498: e3a02000 mov r2, #0 800849c: e1a06000 mov r6, r0 80084a0: e1a07001 mov r7, r1 80084a4: e1a00004 mov r0, r4 80084a8: e1a01005 mov r1, r5 80084ac: e3a03101 mov r3, #1073741824 ; 0x40000000 80084b0: fa0000f1 blx 800887c <__adddf3> 80084b4: e1a02000 mov r2, r0 80084b8: e1a03001 mov r3, r1 80084bc: e1a00006 mov r0, r6 80084c0: e1a01007 mov r1, r7 80084c4: fa00025a blx 8008e34 <__aeabi_ddiv> 80084c8: e3a0a000 mov sl, #0 80084cc: e1a05000 mov r5, r0 80084d0: e1a04001 mov r4, r1 80084d4: eaffff61 b 8008260 80084d8: e28d1008 add r1, sp, #8 80084dc: e8910003 ldm r1, {r0, r1} 80084e0: fa0000e5 blx 800887c <__adddf3> 80084e4: e1a02005 mov r2, r5 80084e8: e1a03004 mov r3, r4 80084ec: fa0001bb blx 8008be0 <__aeabi_dmul> 80084f0: e1a02000 mov r2, r0 80084f4: e1a03001 mov r3, r1 80084f8: e1a00005 mov r0, r5 80084fc: e1a01004 mov r1, r4 8008500: fa0000dc blx 8008878 <__aeabi_dsub> 8008504: e1a05000 mov r5, r0 8008508: e1a04001 mov r4, r1 800850c: eaffffc4 b 8008424 8008510: e59f3158 ldr r3, [pc, #344] ; 8008670 8008514: e1560003 cmp r6, r3 8008518: ca000015 bgt 8008574 800851c: e3a02000 mov r2, #0 8008520: e59f314c ldr r3, [pc, #332] ; 8008674 8008524: fa0000d3 blx 8008878 <__aeabi_dsub> 8008528: e3a02000 mov r2, #0 800852c: e1a06000 mov r6, r0 8008530: e1a07001 mov r7, r1 8008534: e1a00004 mov r0, r4 8008538: e1a01005 mov r1, r5 800853c: e59f3130 ldr r3, [pc, #304] ; 8008674 8008540: fa0001a6 blx 8008be0 <__aeabi_dmul> 8008544: e3a02000 mov r2, #0 8008548: e59f3118 ldr r3, [pc, #280] ; 8008668 800854c: fa0000ca blx 800887c <__adddf3> 8008550: e1a02000 mov r2, r0 8008554: e1a03001 mov r3, r1 8008558: e1a00006 mov r0, r6 800855c: e1a01007 mov r1, r7 8008560: fa000233 blx 8008e34 <__aeabi_ddiv> 8008564: e3a0a002 mov sl, #2 8008568: e1a05000 mov r5, r0 800856c: e1a04001 mov r4, r1 8008570: eaffff3a b 8008260 8008574: e1a02004 mov r2, r4 8008578: e1a03005 mov r3, r5 800857c: e3a00000 mov r0, #0 8008580: e59f10f0 ldr r1, [pc, #240] ; 8008678 8008584: fa00022a blx 8008e34 <__aeabi_ddiv> 8008588: e3a0a003 mov sl, #3 800858c: e1a05000 mov r5, r0 8008590: e1a04001 mov r4, r1 8008594: eaffff31 b 8008260 8008598: e3a02000 mov r2, #0 800859c: e59f30c4 ldr r3, [pc, #196] ; 8008668 80085a0: fa0000b4 blx 8008878 <__aeabi_dsub> 80085a4: e3a02000 mov r2, #0 80085a8: e1a06000 mov r6, r0 80085ac: e1a07001 mov r7, r1 80085b0: e1a00004 mov r0, r4 80085b4: e1a01005 mov r1, r5 80085b8: e59f30a8 ldr r3, [pc, #168] ; 8008668 80085bc: fa0000ae blx 800887c <__adddf3> 80085c0: e1a02000 mov r2, r0 80085c4: e1a03001 mov r3, r1 80085c8: e1a00006 mov r0, r6 80085cc: e1a01007 mov r1, r7 80085d0: fa000217 blx 8008e34 <__aeabi_ddiv> 80085d4: e3a0a001 mov sl, #1 80085d8: e1a05000 mov r5, r0 80085dc: e1a04001 mov r4, r1 80085e0: eaffff1e b 8008260 80085e4: e1a00000 nop ; (mov r0, r0) 80085e8: e322da11 .word 0xe322da11 80085ec: 3f90ad3a .word 0x3f90ad3a 80085f0: 24760deb .word 0x24760deb 80085f4: 3fa97b4b .word 0x3fa97b4b 80085f8: a0d03d51 .word 0xa0d03d51 80085fc: 3fb10d66 .word 0x3fb10d66 8008600: c54c206e .word 0xc54c206e 8008604: 3fb745cd .word 0x3fb745cd 8008608: 920083ff .word 0x920083ff 800860c: 3fc24924 .word 0x3fc24924 8008610: 5555550d .word 0x5555550d 8008614: 3fd55555 .word 0x3fd55555 8008618: 2c6a6c2f .word 0x2c6a6c2f 800861c: bfa2b444 .word 0xbfa2b444 8008620: 52defd9a .word 0x52defd9a 8008624: 3fadde2d .word 0x3fadde2d 8008628: af749a6d .word 0xaf749a6d 800862c: 3fb3b0f2 .word 0x3fb3b0f2 8008630: fe231671 .word 0xfe231671 8008634: 3fbc71c6 .word 0x3fbc71c6 8008638: 9998ebc4 .word 0x9998ebc4 800863c: 3fc99999 .word 0x3fc99999 8008640: 8800759c .word 0x8800759c 8008644: 7e37e43c .word 0x7e37e43c 8008648: 440fffff .word 0x440fffff 800864c: 7ff00000 .word 0x7ff00000 8008650: 3ff921fb .word 0x3ff921fb 8008654: bff921fb .word 0xbff921fb 8008658: 54442d18 .word 0x54442d18 800865c: 3fdbffff .word 0x3fdbffff 8008660: 0800afb8 .word 0x0800afb8 8008664: 0800af98 .word 0x0800af98 8008668: 3ff00000 .word 0x3ff00000 800866c: 3ff2ffff .word 0x3ff2ffff 8008670: 40037fff .word 0x40037fff 8008674: 3ff80000 .word 0x3ff80000 8008678: bff00000 .word 0xbff00000 800867c: e1a00000 nop ; (mov r0, r0) 08008680 : 8008680: e3c11102 bic r1, r1, #-2147483648 ; 0x80000000 8008684: e12fff1e bx lr 08008688 : 8008688: e3c10102 bic r0, r1, #-2147483648 ; 0x80000000 800868c: e2800102 add r0, r0, #-2147483648 ; 0x80000000 8008690: e2800601 add r0, r0, #1048576 ; 0x100000 8008694: e1a00fa0 lsr r0, r0, #31 8008698: e12fff1e bx lr 0800869c : 800869c: e3a00000 mov r0, #0 80086a0: e12fff1e bx lr 80086a4: 00000000 andeq r0, r0, r0 080086a8 : 80086a8: e59f3180 ldr r3, [pc, #384] ; 8008830 80086ac: e0013003 and r3, r1, r3 80086b0: e1b03a43 asrs r3, r3, #20 80086b4: e92d4370 push {r4, r5, r6, r8, r9, lr} 80086b8: e1a0c001 mov ip, r1 80086bc: e1a04000 mov r4, r0 80086c0: e1a05001 mov r5, r1 80086c4: e1a08000 mov r8, r0 80086c8: e1a09001 mov r9, r1 80086cc: e1a06002 mov r6, r2 80086d0: 1a000021 bne 800875c 80086d4: e3c1c102 bic ip, r1, #-2147483648 ; 0x80000000 80086d8: e19cc000 orrs ip, ip, r0 80086dc: 0a00001a beq 800874c 80086e0: e59f314c ldr r3, [pc, #332] ; 8008834 80086e4: e3a02000 mov r2, #0 80086e8: fa00013c blx 8008be0 <__aeabi_dmul> 80086ec: e59f3144 ldr r3, [pc, #324] ; 8008838 80086f0: e1560003 cmp r6, r3 80086f4: e1a04000 mov r4, r0 80086f8: e1a05001 mov r5, r1 80086fc: ba00002e blt 80087bc 8008700: e59f2128 ldr r2, [pc, #296] ; 8008830 8008704: e0012002 and r2, r1, r2 8008708: e1a03a42 asr r3, r2, #20 800870c: e2433036 sub r3, r3, #54 ; 0x36 8008710: e59f2124 ldr r2, [pc, #292] ; 800883c 8008714: e0833006 add r3, r3, r6 8008718: e1530002 cmp r3, r2 800871c: e1a0c001 mov ip, r1 8008720: c1a02004 movgt r2, r4 8008724: c1a03005 movgt r3, r5 8008728: da000014 ble 8008780 800872c: e28f10ec add r1, pc, #236 ; 0xec 8008730: e8910003 ldm r1, {r0, r1} 8008734: eb000045 bl 8008850 8008738: e28f30e0 add r3, pc, #224 ; 0xe0 800873c: e893000c ldm r3, {r2, r3} 8008740: fa000126 blx 8008be0 <__aeabi_dmul> 8008744: e1a04000 mov r4, r0 8008748: e1a05001 mov r5, r1 800874c: e1a00004 mov r0, r4 8008750: e1a01005 mov r1, r5 8008754: e8bd4370 pop {r4, r5, r6, r8, r9, lr} 8008758: e12fff1e bx lr 800875c: e59f20dc ldr r2, [pc, #220] ; 8008840 8008760: e1530002 cmp r3, r2 8008764: 0a00001a beq 80087d4 8008768: e59f20cc ldr r2, [pc, #204] ; 800883c 800876c: e0833006 add r3, r3, r6 8008770: e1530002 cmp r3, r2 8008774: c1a02004 movgt r2, r4 8008778: c1a03005 movgt r3, r5 800877c: caffffea bgt 800872c 8008780: e3530000 cmp r3, #0 8008784: c3ccc47f bicgt ip, ip, #2130706432 ; 0x7f000000 8008788: c3ccc60f bicgt ip, ip, #15728640 ; 0xf00000 800878c: c18c5a03 orrgt r5, ip, r3, lsl #20 8008790: caffffed bgt 800874c 8008794: e3730035 cmn r3, #53 ; 0x35 8008798: aa000013 bge 80087ec 800879c: e59f30a0 ldr r3, [pc, #160] ; 8008844 80087a0: e1560003 cmp r6, r3 80087a4: e1a02004 mov r2, r4 80087a8: e1a03005 mov r3, r5 80087ac: caffffde bgt 800872c 80087b0: e28f1070 add r1, pc, #112 ; 0x70 80087b4: e8910003 ldm r1, {r0, r1} 80087b8: eb000024 bl 8008850 80087bc: e28f3064 add r3, pc, #100 ; 0x64 80087c0: e893000c ldm r3, {r2, r3} 80087c4: fa000105 blx 8008be0 <__aeabi_dmul> 80087c8: e1a04000 mov r4, r0 80087cc: e1a05001 mov r5, r1 80087d0: eaffffdd b 800874c 80087d4: e1a02000 mov r2, r0 80087d8: e1a03001 mov r3, r1 80087dc: fa000026 blx 800887c <__adddf3> 80087e0: e1a04000 mov r4, r0 80087e4: e1a05001 mov r5, r1 80087e8: eaffffd7 b 800874c 80087ec: e3ccc47f bic ip, ip, #2130706432 ; 0x7f000000 80087f0: e2833036 add r3, r3, #54 ; 0x36 80087f4: e3ccc60f bic ip, ip, #15728640 ; 0xf00000 80087f8: e18c5a03 orr r5, ip, r3, lsl #20 80087fc: e1a00004 mov r0, r4 8008800: e1a01005 mov r1, r5 8008804: e3a02000 mov r2, #0 8008808: e59f3038 ldr r3, [pc, #56] ; 8008848 800880c: fa0000f3 blx 8008be0 <__aeabi_dmul> 8008810: e1a04000 mov r4, r0 8008814: e1a05001 mov r5, r1 8008818: eaffffcb b 800874c 800881c: e1a00000 nop ; (mov r0, r0) 8008820: 8800759c .word 0x8800759c 8008824: 7e37e43c .word 0x7e37e43c 8008828: c2f8f359 .word 0xc2f8f359 800882c: 01a56e1f .word 0x01a56e1f 8008830: 7ff00000 .word 0x7ff00000 8008834: 43500000 .word 0x43500000 8008838: ffff3cb0 .word 0xffff3cb0 800883c: 000007fe .word 0x000007fe 8008840: 000007ff .word 0x000007ff 8008844: 0000c350 .word 0x0000c350 8008848: 3c900000 .word 0x3c900000 800884c: e1a00000 nop ; (mov r0, r0) 08008850 : 8008850: e2033102 and r3, r3, #-2147483648 ; 0x80000000 8008854: e3c12102 bic r2, r1, #-2147483648 ; 0x80000000 8008858: e92d0030 push {r4, r5} 800885c: e1a05001 mov r5, r1 8008860: e1a04000 mov r4, r0 8008864: e1831002 orr r1, r3, r2 8008868: e8bd0030 pop {r4, r5} 800886c: e12fff1e bx lr 08008870 <__aeabi_drsub>: 8008870: f081 4100 eor.w r1, r1, #2147483648 ; 0x80000000 8008874: e002 b.n 800887c <__adddf3> 8008876: bf00 nop 08008878 <__aeabi_dsub>: 8008878: f083 4300 eor.w r3, r3, #2147483648 ; 0x80000000 0800887c <__adddf3>: 800887c: b530 push {r4, r5, lr} 800887e: ea4f 0441 mov.w r4, r1, lsl #1 8008882: ea4f 0543 mov.w r5, r3, lsl #1 8008886: ea94 0f05 teq r4, r5 800888a: bf08 it eq 800888c: ea90 0f02 teqeq r0, r2 8008890: bf1f itttt ne 8008892: ea54 0c00 orrsne.w ip, r4, r0 8008896: ea55 0c02 orrsne.w ip, r5, r2 800889a: ea7f 5c64 mvnsne.w ip, r4, asr #21 800889e: ea7f 5c65 mvnsne.w ip, r5, asr #21 80088a2: f000 80e2 beq.w 8008a6a <__adddf3+0x1ee> 80088a6: ea4f 5454 mov.w r4, r4, lsr #21 80088aa: ebd4 5555 rsbs r5, r4, r5, lsr #21 80088ae: bfb8 it lt 80088b0: 426d neglt r5, r5 80088b2: dd0c ble.n 80088ce <__adddf3+0x52> 80088b4: 442c add r4, r5 80088b6: ea80 0202 eor.w r2, r0, r2 80088ba: ea81 0303 eor.w r3, r1, r3 80088be: ea82 0000 eor.w r0, r2, r0 80088c2: ea83 0101 eor.w r1, r3, r1 80088c6: ea80 0202 eor.w r2, r0, r2 80088ca: ea81 0303 eor.w r3, r1, r3 80088ce: 2d36 cmp r5, #54 ; 0x36 80088d0: bf88 it hi 80088d2: bd30 pophi {r4, r5, pc} 80088d4: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 80088d8: ea4f 3101 mov.w r1, r1, lsl #12 80088dc: f44f 1c80 mov.w ip, #1048576 ; 0x100000 80088e0: ea4c 3111 orr.w r1, ip, r1, lsr #12 80088e4: d002 beq.n 80088ec <__adddf3+0x70> 80088e6: 4240 negs r0, r0 80088e8: eb61 0141 sbc.w r1, r1, r1, lsl #1 80088ec: f013 4f00 tst.w r3, #2147483648 ; 0x80000000 80088f0: ea4f 3303 mov.w r3, r3, lsl #12 80088f4: ea4c 3313 orr.w r3, ip, r3, lsr #12 80088f8: d002 beq.n 8008900 <__adddf3+0x84> 80088fa: 4252 negs r2, r2 80088fc: eb63 0343 sbc.w r3, r3, r3, lsl #1 8008900: ea94 0f05 teq r4, r5 8008904: f000 80a7 beq.w 8008a56 <__adddf3+0x1da> 8008908: f1a4 0401 sub.w r4, r4, #1 800890c: f1d5 0e20 rsbs lr, r5, #32 8008910: db0d blt.n 800892e <__adddf3+0xb2> 8008912: fa02 fc0e lsl.w ip, r2, lr 8008916: fa22 f205 lsr.w r2, r2, r5 800891a: 1880 adds r0, r0, r2 800891c: f141 0100 adc.w r1, r1, #0 8008920: fa03 f20e lsl.w r2, r3, lr 8008924: 1880 adds r0, r0, r2 8008926: fa43 f305 asr.w r3, r3, r5 800892a: 4159 adcs r1, r3 800892c: e00e b.n 800894c <__adddf3+0xd0> 800892e: f1a5 0520 sub.w r5, r5, #32 8008932: f10e 0e20 add.w lr, lr, #32 8008936: 2a01 cmp r2, #1 8008938: fa03 fc0e lsl.w ip, r3, lr 800893c: bf28 it cs 800893e: f04c 0c02 orrcs.w ip, ip, #2 8008942: fa43 f305 asr.w r3, r3, r5 8008946: 18c0 adds r0, r0, r3 8008948: eb51 71e3 adcs.w r1, r1, r3, asr #31 800894c: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8008950: d507 bpl.n 8008962 <__adddf3+0xe6> 8008952: f04f 0e00 mov.w lr, #0 8008956: f1dc 0c00 rsbs ip, ip, #0 800895a: eb7e 0000 sbcs.w r0, lr, r0 800895e: eb6e 0101 sbc.w r1, lr, r1 8008962: f5b1 1f80 cmp.w r1, #1048576 ; 0x100000 8008966: d31b bcc.n 80089a0 <__adddf3+0x124> 8008968: f5b1 1f00 cmp.w r1, #2097152 ; 0x200000 800896c: d30c bcc.n 8008988 <__adddf3+0x10c> 800896e: 0849 lsrs r1, r1, #1 8008970: ea5f 0030 movs.w r0, r0, rrx 8008974: ea4f 0c3c mov.w ip, ip, rrx 8008978: f104 0401 add.w r4, r4, #1 800897c: ea4f 5244 mov.w r2, r4, lsl #21 8008980: f512 0f80 cmn.w r2, #4194304 ; 0x400000 8008984: f080 809a bcs.w 8008abc <__adddf3+0x240> 8008988: f1bc 4f00 cmp.w ip, #2147483648 ; 0x80000000 800898c: bf08 it eq 800898e: ea5f 0c50 movseq.w ip, r0, lsr #1 8008992: f150 0000 adcs.w r0, r0, #0 8008996: eb41 5104 adc.w r1, r1, r4, lsl #20 800899a: ea41 0105 orr.w r1, r1, r5 800899e: bd30 pop {r4, r5, pc} 80089a0: ea5f 0c4c movs.w ip, ip, lsl #1 80089a4: 4140 adcs r0, r0 80089a6: eb41 0101 adc.w r1, r1, r1 80089aa: f411 1f80 tst.w r1, #1048576 ; 0x100000 80089ae: f1a4 0401 sub.w r4, r4, #1 80089b2: d1e9 bne.n 8008988 <__adddf3+0x10c> 80089b4: f091 0f00 teq r1, #0 80089b8: bf04 itt eq 80089ba: 4601 moveq r1, r0 80089bc: 2000 moveq r0, #0 80089be: fab1 f381 clz r3, r1 80089c2: bf08 it eq 80089c4: 3320 addeq r3, #32 80089c6: f1a3 030b sub.w r3, r3, #11 80089ca: f1b3 0220 subs.w r2, r3, #32 80089ce: da0c bge.n 80089ea <__adddf3+0x16e> 80089d0: 320c adds r2, #12 80089d2: dd08 ble.n 80089e6 <__adddf3+0x16a> 80089d4: f102 0c14 add.w ip, r2, #20 80089d8: f1c2 020c rsb r2, r2, #12 80089dc: fa01 f00c lsl.w r0, r1, ip 80089e0: fa21 f102 lsr.w r1, r1, r2 80089e4: e00c b.n 8008a00 <__adddf3+0x184> 80089e6: f102 0214 add.w r2, r2, #20 80089ea: bfd8 it le 80089ec: f1c2 0c20 rsble ip, r2, #32 80089f0: fa01 f102 lsl.w r1, r1, r2 80089f4: fa20 fc0c lsr.w ip, r0, ip 80089f8: bfdc itt le 80089fa: ea41 010c orrle.w r1, r1, ip 80089fe: 4090 lslle r0, r2 8008a00: 1ae4 subs r4, r4, r3 8008a02: bfa2 ittt ge 8008a04: eb01 5104 addge.w r1, r1, r4, lsl #20 8008a08: 4329 orrge r1, r5 8008a0a: bd30 popge {r4, r5, pc} 8008a0c: ea6f 0404 mvn.w r4, r4 8008a10: 3c1f subs r4, #31 8008a12: da1c bge.n 8008a4e <__adddf3+0x1d2> 8008a14: 340c adds r4, #12 8008a16: dc0e bgt.n 8008a36 <__adddf3+0x1ba> 8008a18: f104 0414 add.w r4, r4, #20 8008a1c: f1c4 0220 rsb r2, r4, #32 8008a20: fa20 f004 lsr.w r0, r0, r4 8008a24: fa01 f302 lsl.w r3, r1, r2 8008a28: ea40 0003 orr.w r0, r0, r3 8008a2c: fa21 f304 lsr.w r3, r1, r4 8008a30: ea45 0103 orr.w r1, r5, r3 8008a34: bd30 pop {r4, r5, pc} 8008a36: f1c4 040c rsb r4, r4, #12 8008a3a: f1c4 0220 rsb r2, r4, #32 8008a3e: fa20 f002 lsr.w r0, r0, r2 8008a42: fa01 f304 lsl.w r3, r1, r4 8008a46: ea40 0003 orr.w r0, r0, r3 8008a4a: 4629 mov r1, r5 8008a4c: bd30 pop {r4, r5, pc} 8008a4e: fa21 f004 lsr.w r0, r1, r4 8008a52: 4629 mov r1, r5 8008a54: bd30 pop {r4, r5, pc} 8008a56: f094 0f00 teq r4, #0 8008a5a: f483 1380 eor.w r3, r3, #1048576 ; 0x100000 8008a5e: bf06 itte eq 8008a60: f481 1180 eoreq.w r1, r1, #1048576 ; 0x100000 8008a64: 3401 addeq r4, #1 8008a66: 3d01 subne r5, #1 8008a68: e74e b.n 8008908 <__adddf3+0x8c> 8008a6a: ea7f 5c64 mvns.w ip, r4, asr #21 8008a6e: bf18 it ne 8008a70: ea7f 5c65 mvnsne.w ip, r5, asr #21 8008a74: d029 beq.n 8008aca <__adddf3+0x24e> 8008a76: ea94 0f05 teq r4, r5 8008a7a: bf08 it eq 8008a7c: ea90 0f02 teqeq r0, r2 8008a80: d005 beq.n 8008a8e <__adddf3+0x212> 8008a82: ea54 0c00 orrs.w ip, r4, r0 8008a86: bf04 itt eq 8008a88: 4619 moveq r1, r3 8008a8a: 4610 moveq r0, r2 8008a8c: bd30 pop {r4, r5, pc} 8008a8e: ea91 0f03 teq r1, r3 8008a92: bf1e ittt ne 8008a94: 2100 movne r1, #0 8008a96: 2000 movne r0, #0 8008a98: bd30 popne {r4, r5, pc} 8008a9a: ea5f 5c54 movs.w ip, r4, lsr #21 8008a9e: d105 bne.n 8008aac <__adddf3+0x230> 8008aa0: 0040 lsls r0, r0, #1 8008aa2: 4149 adcs r1, r1 8008aa4: bf28 it cs 8008aa6: f041 4100 orrcs.w r1, r1, #2147483648 ; 0x80000000 8008aaa: bd30 pop {r4, r5, pc} 8008aac: f514 0480 adds.w r4, r4, #4194304 ; 0x400000 8008ab0: bf3c itt cc 8008ab2: f501 1180 addcc.w r1, r1, #1048576 ; 0x100000 8008ab6: bd30 popcc {r4, r5, pc} 8008ab8: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8008abc: f045 41fe orr.w r1, r5, #2130706432 ; 0x7f000000 8008ac0: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 8008ac4: f04f 0000 mov.w r0, #0 8008ac8: bd30 pop {r4, r5, pc} 8008aca: ea7f 5c64 mvns.w ip, r4, asr #21 8008ace: bf1a itte ne 8008ad0: 4619 movne r1, r3 8008ad2: 4610 movne r0, r2 8008ad4: ea7f 5c65 mvnseq.w ip, r5, asr #21 8008ad8: bf1c itt ne 8008ada: 460b movne r3, r1 8008adc: 4602 movne r2, r0 8008ade: ea50 3401 orrs.w r4, r0, r1, lsl #12 8008ae2: bf06 itte eq 8008ae4: ea52 3503 orrseq.w r5, r2, r3, lsl #12 8008ae8: ea91 0f03 teqeq r1, r3 8008aec: f441 2100 orrne.w r1, r1, #524288 ; 0x80000 8008af0: bd30 pop {r4, r5, pc} 8008af2: bf00 nop 08008af4 <__aeabi_ui2d>: 8008af4: f090 0f00 teq r0, #0 8008af8: bf04 itt eq 8008afa: 2100 moveq r1, #0 8008afc: 4770 bxeq lr 8008afe: b530 push {r4, r5, lr} 8008b00: f44f 6480 mov.w r4, #1024 ; 0x400 8008b04: f104 0432 add.w r4, r4, #50 ; 0x32 8008b08: f04f 0500 mov.w r5, #0 8008b0c: f04f 0100 mov.w r1, #0 8008b10: e750 b.n 80089b4 <__adddf3+0x138> 8008b12: bf00 nop 08008b14 <__aeabi_i2d>: 8008b14: f090 0f00 teq r0, #0 8008b18: bf04 itt eq 8008b1a: 2100 moveq r1, #0 8008b1c: 4770 bxeq lr 8008b1e: b530 push {r4, r5, lr} 8008b20: f44f 6480 mov.w r4, #1024 ; 0x400 8008b24: f104 0432 add.w r4, r4, #50 ; 0x32 8008b28: f010 4500 ands.w r5, r0, #2147483648 ; 0x80000000 8008b2c: bf48 it mi 8008b2e: 4240 negmi r0, r0 8008b30: f04f 0100 mov.w r1, #0 8008b34: e73e b.n 80089b4 <__adddf3+0x138> 8008b36: bf00 nop 08008b38 <__aeabi_f2d>: 8008b38: 0042 lsls r2, r0, #1 8008b3a: ea4f 01e2 mov.w r1, r2, asr #3 8008b3e: ea4f 0131 mov.w r1, r1, rrx 8008b42: ea4f 7002 mov.w r0, r2, lsl #28 8008b46: bf1f itttt ne 8008b48: f012 437f andsne.w r3, r2, #4278190080 ; 0xff000000 8008b4c: f093 4f7f teqne r3, #4278190080 ; 0xff000000 8008b50: f081 5160 eorne.w r1, r1, #939524096 ; 0x38000000 8008b54: 4770 bxne lr 8008b56: f092 0f00 teq r2, #0 8008b5a: bf14 ite ne 8008b5c: f093 4f7f teqne r3, #4278190080 ; 0xff000000 8008b60: 4770 bxeq lr 8008b62: b530 push {r4, r5, lr} 8008b64: f44f 7460 mov.w r4, #896 ; 0x380 8008b68: f001 4500 and.w r5, r1, #2147483648 ; 0x80000000 8008b6c: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 8008b70: e720 b.n 80089b4 <__adddf3+0x138> 8008b72: bf00 nop 08008b74 <__aeabi_ul2d>: 8008b74: ea50 0201 orrs.w r2, r0, r1 8008b78: bf08 it eq 8008b7a: 4770 bxeq lr 8008b7c: b530 push {r4, r5, lr} 8008b7e: f04f 0500 mov.w r5, #0 8008b82: e00a b.n 8008b9a <__aeabi_l2d+0x16> 08008b84 <__aeabi_l2d>: 8008b84: ea50 0201 orrs.w r2, r0, r1 8008b88: bf08 it eq 8008b8a: 4770 bxeq lr 8008b8c: b530 push {r4, r5, lr} 8008b8e: f011 4500 ands.w r5, r1, #2147483648 ; 0x80000000 8008b92: d502 bpl.n 8008b9a <__aeabi_l2d+0x16> 8008b94: 4240 negs r0, r0 8008b96: eb61 0141 sbc.w r1, r1, r1, lsl #1 8008b9a: f44f 6480 mov.w r4, #1024 ; 0x400 8008b9e: f104 0432 add.w r4, r4, #50 ; 0x32 8008ba2: ea5f 5c91 movs.w ip, r1, lsr #22 8008ba6: f43f aedc beq.w 8008962 <__adddf3+0xe6> 8008baa: f04f 0203 mov.w r2, #3 8008bae: ea5f 0cdc movs.w ip, ip, lsr #3 8008bb2: bf18 it ne 8008bb4: 3203 addne r2, #3 8008bb6: ea5f 0cdc movs.w ip, ip, lsr #3 8008bba: bf18 it ne 8008bbc: 3203 addne r2, #3 8008bbe: eb02 02dc add.w r2, r2, ip, lsr #3 8008bc2: f1c2 0320 rsb r3, r2, #32 8008bc6: fa00 fc03 lsl.w ip, r0, r3 8008bca: fa20 f002 lsr.w r0, r0, r2 8008bce: fa01 fe03 lsl.w lr, r1, r3 8008bd2: ea40 000e orr.w r0, r0, lr 8008bd6: fa21 f102 lsr.w r1, r1, r2 8008bda: 4414 add r4, r2 8008bdc: e6c1 b.n 8008962 <__adddf3+0xe6> 8008bde: bf00 nop 08008be0 <__aeabi_dmul>: 8008be0: b570 push {r4, r5, r6, lr} 8008be2: f04f 0cff mov.w ip, #255 ; 0xff 8008be6: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 8008bea: ea1c 5411 ands.w r4, ip, r1, lsr #20 8008bee: bf1d ittte ne 8008bf0: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8008bf4: ea94 0f0c teqne r4, ip 8008bf8: ea95 0f0c teqne r5, ip 8008bfc: f000 f8de bleq 8008dbc <__aeabi_dmul+0x1dc> 8008c00: 442c add r4, r5 8008c02: ea81 0603 eor.w r6, r1, r3 8008c06: ea21 514c bic.w r1, r1, ip, lsl #21 8008c0a: ea23 534c bic.w r3, r3, ip, lsl #21 8008c0e: ea50 3501 orrs.w r5, r0, r1, lsl #12 8008c12: bf18 it ne 8008c14: ea52 3503 orrsne.w r5, r2, r3, lsl #12 8008c18: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8008c1c: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 8008c20: d038 beq.n 8008c94 <__aeabi_dmul+0xb4> 8008c22: fba0 ce02 umull ip, lr, r0, r2 8008c26: f04f 0500 mov.w r5, #0 8008c2a: fbe1 e502 umlal lr, r5, r1, r2 8008c2e: f006 4200 and.w r2, r6, #2147483648 ; 0x80000000 8008c32: fbe0 e503 umlal lr, r5, r0, r3 8008c36: f04f 0600 mov.w r6, #0 8008c3a: fbe1 5603 umlal r5, r6, r1, r3 8008c3e: f09c 0f00 teq ip, #0 8008c42: bf18 it ne 8008c44: f04e 0e01 orrne.w lr, lr, #1 8008c48: f1a4 04ff sub.w r4, r4, #255 ; 0xff 8008c4c: f5b6 7f00 cmp.w r6, #512 ; 0x200 8008c50: f564 7440 sbc.w r4, r4, #768 ; 0x300 8008c54: d204 bcs.n 8008c60 <__aeabi_dmul+0x80> 8008c56: ea5f 0e4e movs.w lr, lr, lsl #1 8008c5a: 416d adcs r5, r5 8008c5c: eb46 0606 adc.w r6, r6, r6 8008c60: ea42 21c6 orr.w r1, r2, r6, lsl #11 8008c64: ea41 5155 orr.w r1, r1, r5, lsr #21 8008c68: ea4f 20c5 mov.w r0, r5, lsl #11 8008c6c: ea40 505e orr.w r0, r0, lr, lsr #21 8008c70: ea4f 2ece mov.w lr, lr, lsl #11 8008c74: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 8008c78: bf88 it hi 8008c7a: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 8008c7e: d81e bhi.n 8008cbe <__aeabi_dmul+0xde> 8008c80: f1be 4f00 cmp.w lr, #2147483648 ; 0x80000000 8008c84: bf08 it eq 8008c86: ea5f 0e50 movseq.w lr, r0, lsr #1 8008c8a: f150 0000 adcs.w r0, r0, #0 8008c8e: eb41 5104 adc.w r1, r1, r4, lsl #20 8008c92: bd70 pop {r4, r5, r6, pc} 8008c94: f006 4600 and.w r6, r6, #2147483648 ; 0x80000000 8008c98: ea46 0101 orr.w r1, r6, r1 8008c9c: ea40 0002 orr.w r0, r0, r2 8008ca0: ea81 0103 eor.w r1, r1, r3 8008ca4: ebb4 045c subs.w r4, r4, ip, lsr #1 8008ca8: bfc2 ittt gt 8008caa: ebd4 050c rsbsgt r5, r4, ip 8008cae: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8008cb2: bd70 popgt {r4, r5, r6, pc} 8008cb4: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8008cb8: f04f 0e00 mov.w lr, #0 8008cbc: 3c01 subs r4, #1 8008cbe: f300 80ab bgt.w 8008e18 <__aeabi_dmul+0x238> 8008cc2: f114 0f36 cmn.w r4, #54 ; 0x36 8008cc6: bfde ittt le 8008cc8: 2000 movle r0, #0 8008cca: f001 4100 andle.w r1, r1, #2147483648 ; 0x80000000 8008cce: bd70 pople {r4, r5, r6, pc} 8008cd0: f1c4 0400 rsb r4, r4, #0 8008cd4: 3c20 subs r4, #32 8008cd6: da35 bge.n 8008d44 <__aeabi_dmul+0x164> 8008cd8: 340c adds r4, #12 8008cda: dc1b bgt.n 8008d14 <__aeabi_dmul+0x134> 8008cdc: f104 0414 add.w r4, r4, #20 8008ce0: f1c4 0520 rsb r5, r4, #32 8008ce4: fa00 f305 lsl.w r3, r0, r5 8008ce8: fa20 f004 lsr.w r0, r0, r4 8008cec: fa01 f205 lsl.w r2, r1, r5 8008cf0: ea40 0002 orr.w r0, r0, r2 8008cf4: f001 4200 and.w r2, r1, #2147483648 ; 0x80000000 8008cf8: f021 4100 bic.w r1, r1, #2147483648 ; 0x80000000 8008cfc: eb10 70d3 adds.w r0, r0, r3, lsr #31 8008d00: fa21 f604 lsr.w r6, r1, r4 8008d04: eb42 0106 adc.w r1, r2, r6 8008d08: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8008d0c: bf08 it eq 8008d0e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8008d12: bd70 pop {r4, r5, r6, pc} 8008d14: f1c4 040c rsb r4, r4, #12 8008d18: f1c4 0520 rsb r5, r4, #32 8008d1c: fa00 f304 lsl.w r3, r0, r4 8008d20: fa20 f005 lsr.w r0, r0, r5 8008d24: fa01 f204 lsl.w r2, r1, r4 8008d28: ea40 0002 orr.w r0, r0, r2 8008d2c: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 8008d30: eb10 70d3 adds.w r0, r0, r3, lsr #31 8008d34: f141 0100 adc.w r1, r1, #0 8008d38: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8008d3c: bf08 it eq 8008d3e: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8008d42: bd70 pop {r4, r5, r6, pc} 8008d44: f1c4 0520 rsb r5, r4, #32 8008d48: fa00 f205 lsl.w r2, r0, r5 8008d4c: ea4e 0e02 orr.w lr, lr, r2 8008d50: fa20 f304 lsr.w r3, r0, r4 8008d54: fa01 f205 lsl.w r2, r1, r5 8008d58: ea43 0302 orr.w r3, r3, r2 8008d5c: fa21 f004 lsr.w r0, r1, r4 8008d60: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 8008d64: fa21 f204 lsr.w r2, r1, r4 8008d68: ea20 0002 bic.w r0, r0, r2 8008d6c: eb00 70d3 add.w r0, r0, r3, lsr #31 8008d70: ea5e 0e43 orrs.w lr, lr, r3, lsl #1 8008d74: bf08 it eq 8008d76: ea20 70d3 biceq.w r0, r0, r3, lsr #31 8008d7a: bd70 pop {r4, r5, r6, pc} 8008d7c: f094 0f00 teq r4, #0 8008d80: d10f bne.n 8008da2 <__aeabi_dmul+0x1c2> 8008d82: f001 4600 and.w r6, r1, #2147483648 ; 0x80000000 8008d86: 0040 lsls r0, r0, #1 8008d88: eb41 0101 adc.w r1, r1, r1 8008d8c: f411 1f80 tst.w r1, #1048576 ; 0x100000 8008d90: bf08 it eq 8008d92: 3c01 subeq r4, #1 8008d94: d0f7 beq.n 8008d86 <__aeabi_dmul+0x1a6> 8008d96: ea41 0106 orr.w r1, r1, r6 8008d9a: f095 0f00 teq r5, #0 8008d9e: bf18 it ne 8008da0: 4770 bxne lr 8008da2: f003 4600 and.w r6, r3, #2147483648 ; 0x80000000 8008da6: 0052 lsls r2, r2, #1 8008da8: eb43 0303 adc.w r3, r3, r3 8008dac: f413 1f80 tst.w r3, #1048576 ; 0x100000 8008db0: bf08 it eq 8008db2: 3d01 subeq r5, #1 8008db4: d0f7 beq.n 8008da6 <__aeabi_dmul+0x1c6> 8008db6: ea43 0306 orr.w r3, r3, r6 8008dba: 4770 bx lr 8008dbc: ea94 0f0c teq r4, ip 8008dc0: ea0c 5513 and.w r5, ip, r3, lsr #20 8008dc4: bf18 it ne 8008dc6: ea95 0f0c teqne r5, ip 8008dca: d00c beq.n 8008de6 <__aeabi_dmul+0x206> 8008dcc: ea50 0641 orrs.w r6, r0, r1, lsl #1 8008dd0: bf18 it ne 8008dd2: ea52 0643 orrsne.w r6, r2, r3, lsl #1 8008dd6: d1d1 bne.n 8008d7c <__aeabi_dmul+0x19c> 8008dd8: ea81 0103 eor.w r1, r1, r3 8008ddc: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 8008de0: f04f 0000 mov.w r0, #0 8008de4: bd70 pop {r4, r5, r6, pc} 8008de6: ea50 0641 orrs.w r6, r0, r1, lsl #1 8008dea: bf06 itte eq 8008dec: 4610 moveq r0, r2 8008dee: 4619 moveq r1, r3 8008df0: ea52 0643 orrsne.w r6, r2, r3, lsl #1 8008df4: d019 beq.n 8008e2a <__aeabi_dmul+0x24a> 8008df6: ea94 0f0c teq r4, ip 8008dfa: d102 bne.n 8008e02 <__aeabi_dmul+0x222> 8008dfc: ea50 3601 orrs.w r6, r0, r1, lsl #12 8008e00: d113 bne.n 8008e2a <__aeabi_dmul+0x24a> 8008e02: ea95 0f0c teq r5, ip 8008e06: d105 bne.n 8008e14 <__aeabi_dmul+0x234> 8008e08: ea52 3603 orrs.w r6, r2, r3, lsl #12 8008e0c: bf1c itt ne 8008e0e: 4610 movne r0, r2 8008e10: 4619 movne r1, r3 8008e12: d10a bne.n 8008e2a <__aeabi_dmul+0x24a> 8008e14: ea81 0103 eor.w r1, r1, r3 8008e18: f001 4100 and.w r1, r1, #2147483648 ; 0x80000000 8008e1c: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 8008e20: f441 0170 orr.w r1, r1, #15728640 ; 0xf00000 8008e24: f04f 0000 mov.w r0, #0 8008e28: bd70 pop {r4, r5, r6, pc} 8008e2a: f041 41fe orr.w r1, r1, #2130706432 ; 0x7f000000 8008e2e: f441 0178 orr.w r1, r1, #16252928 ; 0xf80000 8008e32: bd70 pop {r4, r5, r6, pc} 08008e34 <__aeabi_ddiv>: 8008e34: b570 push {r4, r5, r6, lr} 8008e36: f04f 0cff mov.w ip, #255 ; 0xff 8008e3a: f44c 6ce0 orr.w ip, ip, #1792 ; 0x700 8008e3e: ea1c 5411 ands.w r4, ip, r1, lsr #20 8008e42: bf1d ittte ne 8008e44: ea1c 5513 andsne.w r5, ip, r3, lsr #20 8008e48: ea94 0f0c teqne r4, ip 8008e4c: ea95 0f0c teqne r5, ip 8008e50: f000 f8a7 bleq 8008fa2 <__aeabi_ddiv+0x16e> 8008e54: eba4 0405 sub.w r4, r4, r5 8008e58: ea81 0e03 eor.w lr, r1, r3 8008e5c: ea52 3503 orrs.w r5, r2, r3, lsl #12 8008e60: ea4f 3101 mov.w r1, r1, lsl #12 8008e64: f000 8088 beq.w 8008f78 <__aeabi_ddiv+0x144> 8008e68: ea4f 3303 mov.w r3, r3, lsl #12 8008e6c: f04f 5580 mov.w r5, #268435456 ; 0x10000000 8008e70: ea45 1313 orr.w r3, r5, r3, lsr #4 8008e74: ea43 6312 orr.w r3, r3, r2, lsr #24 8008e78: ea4f 2202 mov.w r2, r2, lsl #8 8008e7c: ea45 1511 orr.w r5, r5, r1, lsr #4 8008e80: ea45 6510 orr.w r5, r5, r0, lsr #24 8008e84: ea4f 2600 mov.w r6, r0, lsl #8 8008e88: f00e 4100 and.w r1, lr, #2147483648 ; 0x80000000 8008e8c: 429d cmp r5, r3 8008e8e: bf08 it eq 8008e90: 4296 cmpeq r6, r2 8008e92: f144 04fd adc.w r4, r4, #253 ; 0xfd 8008e96: f504 7440 add.w r4, r4, #768 ; 0x300 8008e9a: d202 bcs.n 8008ea2 <__aeabi_ddiv+0x6e> 8008e9c: 085b lsrs r3, r3, #1 8008e9e: ea4f 0232 mov.w r2, r2, rrx 8008ea2: 1ab6 subs r6, r6, r2 8008ea4: eb65 0503 sbc.w r5, r5, r3 8008ea8: 085b lsrs r3, r3, #1 8008eaa: ea4f 0232 mov.w r2, r2, rrx 8008eae: f44f 1080 mov.w r0, #1048576 ; 0x100000 8008eb2: f44f 2c00 mov.w ip, #524288 ; 0x80000 8008eb6: ebb6 0e02 subs.w lr, r6, r2 8008eba: eb75 0e03 sbcs.w lr, r5, r3 8008ebe: bf22 ittt cs 8008ec0: 1ab6 subcs r6, r6, r2 8008ec2: 4675 movcs r5, lr 8008ec4: ea40 000c orrcs.w r0, r0, ip 8008ec8: 085b lsrs r3, r3, #1 8008eca: ea4f 0232 mov.w r2, r2, rrx 8008ece: ebb6 0e02 subs.w lr, r6, r2 8008ed2: eb75 0e03 sbcs.w lr, r5, r3 8008ed6: bf22 ittt cs 8008ed8: 1ab6 subcs r6, r6, r2 8008eda: 4675 movcs r5, lr 8008edc: ea40 005c orrcs.w r0, r0, ip, lsr #1 8008ee0: 085b lsrs r3, r3, #1 8008ee2: ea4f 0232 mov.w r2, r2, rrx 8008ee6: ebb6 0e02 subs.w lr, r6, r2 8008eea: eb75 0e03 sbcs.w lr, r5, r3 8008eee: bf22 ittt cs 8008ef0: 1ab6 subcs r6, r6, r2 8008ef2: 4675 movcs r5, lr 8008ef4: ea40 009c orrcs.w r0, r0, ip, lsr #2 8008ef8: 085b lsrs r3, r3, #1 8008efa: ea4f 0232 mov.w r2, r2, rrx 8008efe: ebb6 0e02 subs.w lr, r6, r2 8008f02: eb75 0e03 sbcs.w lr, r5, r3 8008f06: bf22 ittt cs 8008f08: 1ab6 subcs r6, r6, r2 8008f0a: 4675 movcs r5, lr 8008f0c: ea40 00dc orrcs.w r0, r0, ip, lsr #3 8008f10: ea55 0e06 orrs.w lr, r5, r6 8008f14: d018 beq.n 8008f48 <__aeabi_ddiv+0x114> 8008f16: ea4f 1505 mov.w r5, r5, lsl #4 8008f1a: ea45 7516 orr.w r5, r5, r6, lsr #28 8008f1e: ea4f 1606 mov.w r6, r6, lsl #4 8008f22: ea4f 03c3 mov.w r3, r3, lsl #3 8008f26: ea43 7352 orr.w r3, r3, r2, lsr #29 8008f2a: ea4f 02c2 mov.w r2, r2, lsl #3 8008f2e: ea5f 1c1c movs.w ip, ip, lsr #4 8008f32: d1c0 bne.n 8008eb6 <__aeabi_ddiv+0x82> 8008f34: f411 1f80 tst.w r1, #1048576 ; 0x100000 8008f38: d10b bne.n 8008f52 <__aeabi_ddiv+0x11e> 8008f3a: ea41 0100 orr.w r1, r1, r0 8008f3e: f04f 0000 mov.w r0, #0 8008f42: f04f 4c00 mov.w ip, #2147483648 ; 0x80000000 8008f46: e7b6 b.n 8008eb6 <__aeabi_ddiv+0x82> 8008f48: f411 1f80 tst.w r1, #1048576 ; 0x100000 8008f4c: bf04 itt eq 8008f4e: 4301 orreq r1, r0 8008f50: 2000 moveq r0, #0 8008f52: f1b4 0cfd subs.w ip, r4, #253 ; 0xfd 8008f56: bf88 it hi 8008f58: f5bc 6fe0 cmphi.w ip, #1792 ; 0x700 8008f5c: f63f aeaf bhi.w 8008cbe <__aeabi_dmul+0xde> 8008f60: ebb5 0c03 subs.w ip, r5, r3 8008f64: bf04 itt eq 8008f66: ebb6 0c02 subseq.w ip, r6, r2 8008f6a: ea5f 0c50 movseq.w ip, r0, lsr #1 8008f6e: f150 0000 adcs.w r0, r0, #0 8008f72: eb41 5104 adc.w r1, r1, r4, lsl #20 8008f76: bd70 pop {r4, r5, r6, pc} 8008f78: f00e 4e00 and.w lr, lr, #2147483648 ; 0x80000000 8008f7c: ea4e 3111 orr.w r1, lr, r1, lsr #12 8008f80: eb14 045c adds.w r4, r4, ip, lsr #1 8008f84: bfc2 ittt gt 8008f86: ebd4 050c rsbsgt r5, r4, ip 8008f8a: ea41 5104 orrgt.w r1, r1, r4, lsl #20 8008f8e: bd70 popgt {r4, r5, r6, pc} 8008f90: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 8008f94: f04f 0e00 mov.w lr, #0 8008f98: 3c01 subs r4, #1 8008f9a: e690 b.n 8008cbe <__aeabi_dmul+0xde> 8008f9c: ea45 0e06 orr.w lr, r5, r6 8008fa0: e68d b.n 8008cbe <__aeabi_dmul+0xde> 8008fa2: ea0c 5513 and.w r5, ip, r3, lsr #20 8008fa6: ea94 0f0c teq r4, ip 8008faa: bf08 it eq 8008fac: ea95 0f0c teqeq r5, ip 8008fb0: f43f af3b beq.w 8008e2a <__aeabi_dmul+0x24a> 8008fb4: ea94 0f0c teq r4, ip 8008fb8: d10a bne.n 8008fd0 <__aeabi_ddiv+0x19c> 8008fba: ea50 3401 orrs.w r4, r0, r1, lsl #12 8008fbe: f47f af34 bne.w 8008e2a <__aeabi_dmul+0x24a> 8008fc2: ea95 0f0c teq r5, ip 8008fc6: f47f af25 bne.w 8008e14 <__aeabi_dmul+0x234> 8008fca: 4610 mov r0, r2 8008fcc: 4619 mov r1, r3 8008fce: e72c b.n 8008e2a <__aeabi_dmul+0x24a> 8008fd0: ea95 0f0c teq r5, ip 8008fd4: d106 bne.n 8008fe4 <__aeabi_ddiv+0x1b0> 8008fd6: ea52 3503 orrs.w r5, r2, r3, lsl #12 8008fda: f43f aefd beq.w 8008dd8 <__aeabi_dmul+0x1f8> 8008fde: 4610 mov r0, r2 8008fe0: 4619 mov r1, r3 8008fe2: e722 b.n 8008e2a <__aeabi_dmul+0x24a> 8008fe4: ea50 0641 orrs.w r6, r0, r1, lsl #1 8008fe8: bf18 it ne 8008fea: ea52 0643 orrsne.w r6, r2, r3, lsl #1 8008fee: f47f aec5 bne.w 8008d7c <__aeabi_dmul+0x19c> 8008ff2: ea50 0441 orrs.w r4, r0, r1, lsl #1 8008ff6: f47f af0d bne.w 8008e14 <__aeabi_dmul+0x234> 8008ffa: ea52 0543 orrs.w r5, r2, r3, lsl #1 8008ffe: f47f aeeb bne.w 8008dd8 <__aeabi_dmul+0x1f8> 8009002: e712 b.n 8008e2a <__aeabi_dmul+0x24a> 08009004 <__gedf2>: 8009004: f04f 3cff mov.w ip, #4294967295 8009008: e006 b.n 8009018 <__cmpdf2+0x4> 800900a: bf00 nop 0800900c <__ledf2>: 800900c: f04f 0c01 mov.w ip, #1 8009010: e002 b.n 8009018 <__cmpdf2+0x4> 8009012: bf00 nop 08009014 <__cmpdf2>: 8009014: f04f 0c01 mov.w ip, #1 8009018: f84d cd04 str.w ip, [sp, #-4]! 800901c: ea4f 0c41 mov.w ip, r1, lsl #1 8009020: ea7f 5c6c mvns.w ip, ip, asr #21 8009024: ea4f 0c43 mov.w ip, r3, lsl #1 8009028: bf18 it ne 800902a: ea7f 5c6c mvnsne.w ip, ip, asr #21 800902e: d01b beq.n 8009068 <__cmpdf2+0x54> 8009030: b001 add sp, #4 8009032: ea50 0c41 orrs.w ip, r0, r1, lsl #1 8009036: bf0c ite eq 8009038: ea52 0c43 orrseq.w ip, r2, r3, lsl #1 800903c: ea91 0f03 teqne r1, r3 8009040: bf02 ittt eq 8009042: ea90 0f02 teqeq r0, r2 8009046: 2000 moveq r0, #0 8009048: 4770 bxeq lr 800904a: f110 0f00 cmn.w r0, #0 800904e: ea91 0f03 teq r1, r3 8009052: bf58 it pl 8009054: 4299 cmppl r1, r3 8009056: bf08 it eq 8009058: 4290 cmpeq r0, r2 800905a: bf2c ite cs 800905c: 17d8 asrcs r0, r3, #31 800905e: ea6f 70e3 mvncc.w r0, r3, asr #31 8009062: f040 0001 orr.w r0, r0, #1 8009066: 4770 bx lr 8009068: ea4f 0c41 mov.w ip, r1, lsl #1 800906c: ea7f 5c6c mvns.w ip, ip, asr #21 8009070: d102 bne.n 8009078 <__cmpdf2+0x64> 8009072: ea50 3c01 orrs.w ip, r0, r1, lsl #12 8009076: d107 bne.n 8009088 <__cmpdf2+0x74> 8009078: ea4f 0c43 mov.w ip, r3, lsl #1 800907c: ea7f 5c6c mvns.w ip, ip, asr #21 8009080: d1d6 bne.n 8009030 <__cmpdf2+0x1c> 8009082: ea52 3c03 orrs.w ip, r2, r3, lsl #12 8009086: d0d3 beq.n 8009030 <__cmpdf2+0x1c> 8009088: f85d 0b04 ldr.w r0, [sp], #4 800908c: 4770 bx lr 800908e: bf00 nop 08009090 <__aeabi_cdrcmple>: 8009090: 4684 mov ip, r0 8009092: 4610 mov r0, r2 8009094: 4662 mov r2, ip 8009096: 468c mov ip, r1 8009098: 4619 mov r1, r3 800909a: 4663 mov r3, ip 800909c: e000 b.n 80090a0 <__aeabi_cdcmpeq> 800909e: bf00 nop 080090a0 <__aeabi_cdcmpeq>: 80090a0: b501 push {r0, lr} 80090a2: f7ff ffb7 bl 8009014 <__cmpdf2> 80090a6: 2800 cmp r0, #0 80090a8: bf48 it mi 80090aa: f110 0f00 cmnmi.w r0, #0 80090ae: bd01 pop {r0, pc} 080090b0 <__aeabi_dcmpeq>: 80090b0: f84d ed08 str.w lr, [sp, #-8]! 80090b4: f7ff fff4 bl 80090a0 <__aeabi_cdcmpeq> 80090b8: bf0c ite eq 80090ba: 2001 moveq r0, #1 80090bc: 2000 movne r0, #0 80090be: f85d fb08 ldr.w pc, [sp], #8 80090c2: bf00 nop 080090c4 <__aeabi_dcmplt>: 80090c4: f84d ed08 str.w lr, [sp, #-8]! 80090c8: f7ff ffea bl 80090a0 <__aeabi_cdcmpeq> 80090cc: bf34 ite cc 80090ce: 2001 movcc r0, #1 80090d0: 2000 movcs r0, #0 80090d2: f85d fb08 ldr.w pc, [sp], #8 80090d6: bf00 nop 080090d8 <__aeabi_dcmple>: 80090d8: f84d ed08 str.w lr, [sp, #-8]! 80090dc: f7ff ffe0 bl 80090a0 <__aeabi_cdcmpeq> 80090e0: bf94 ite ls 80090e2: 2001 movls r0, #1 80090e4: 2000 movhi r0, #0 80090e6: f85d fb08 ldr.w pc, [sp], #8 80090ea: bf00 nop 080090ec <__aeabi_dcmpge>: 80090ec: f84d ed08 str.w lr, [sp, #-8]! 80090f0: f7ff ffce bl 8009090 <__aeabi_cdrcmple> 80090f4: bf94 ite ls 80090f6: 2001 movls r0, #1 80090f8: 2000 movhi r0, #0 80090fa: f85d fb08 ldr.w pc, [sp], #8 80090fe: bf00 nop 08009100 <__aeabi_dcmpgt>: 8009100: f84d ed08 str.w lr, [sp, #-8]! 8009104: f7ff ffc4 bl 8009090 <__aeabi_cdrcmple> 8009108: bf34 ite cc 800910a: 2001 movcc r0, #1 800910c: 2000 movcs r0, #0 800910e: f85d fb08 ldr.w pc, [sp], #8 8009112: bf00 nop 08009114 <__aeabi_d2iz>: 8009114: ea4f 0241 mov.w r2, r1, lsl #1 8009118: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 800911c: d215 bcs.n 800914a <__aeabi_d2iz+0x36> 800911e: d511 bpl.n 8009144 <__aeabi_d2iz+0x30> 8009120: f46f 7378 mvn.w r3, #992 ; 0x3e0 8009124: ebb3 5262 subs.w r2, r3, r2, asr #21 8009128: d912 bls.n 8009150 <__aeabi_d2iz+0x3c> 800912a: ea4f 23c1 mov.w r3, r1, lsl #11 800912e: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 8009132: ea43 5350 orr.w r3, r3, r0, lsr #21 8009136: f011 4f00 tst.w r1, #2147483648 ; 0x80000000 800913a: fa23 f002 lsr.w r0, r3, r2 800913e: bf18 it ne 8009140: 4240 negne r0, r0 8009142: 4770 bx lr 8009144: f04f 0000 mov.w r0, #0 8009148: 4770 bx lr 800914a: ea50 3001 orrs.w r0, r0, r1, lsl #12 800914e: d105 bne.n 800915c <__aeabi_d2iz+0x48> 8009150: f011 4000 ands.w r0, r1, #2147483648 ; 0x80000000 8009154: bf08 it eq 8009156: f06f 4000 mvneq.w r0, #2147483648 ; 0x80000000 800915a: 4770 bx lr 800915c: f04f 0000 mov.w r0, #0 8009160: 4770 bx lr 8009162: bf00 nop 08009164 <__aeabi_d2uiz>: 8009164: 004a lsls r2, r1, #1 8009166: d211 bcs.n 800918c <__aeabi_d2uiz+0x28> 8009168: f512 1200 adds.w r2, r2, #2097152 ; 0x200000 800916c: d211 bcs.n 8009192 <__aeabi_d2uiz+0x2e> 800916e: d50d bpl.n 800918c <__aeabi_d2uiz+0x28> 8009170: f46f 7378 mvn.w r3, #992 ; 0x3e0 8009174: ebb3 5262 subs.w r2, r3, r2, asr #21 8009178: d40e bmi.n 8009198 <__aeabi_d2uiz+0x34> 800917a: ea4f 23c1 mov.w r3, r1, lsl #11 800917e: f043 4300 orr.w r3, r3, #2147483648 ; 0x80000000 8009182: ea43 5350 orr.w r3, r3, r0, lsr #21 8009186: fa23 f002 lsr.w r0, r3, r2 800918a: 4770 bx lr 800918c: f04f 0000 mov.w r0, #0 8009190: 4770 bx lr 8009192: ea50 3001 orrs.w r0, r0, r1, lsl #12 8009196: d102 bne.n 800919e <__aeabi_d2uiz+0x3a> 8009198: f04f 30ff mov.w r0, #4294967295 800919c: 4770 bx lr 800919e: f04f 0000 mov.w r0, #0 80091a2: 4770 bx lr 080091a4 <__aeabi_d2f>: 80091a4: ea4f 0241 mov.w r2, r1, lsl #1 80091a8: f1b2 43e0 subs.w r3, r2, #1879048192 ; 0x70000000 80091ac: bf24 itt cs 80091ae: f5b3 1c00 subscs.w ip, r3, #2097152 ; 0x200000 80091b2: f1dc 5cfe rsbscs ip, ip, #532676608 ; 0x1fc00000 80091b6: d90d bls.n 80091d4 <__aeabi_d2f+0x30> 80091b8: f001 4c00 and.w ip, r1, #2147483648 ; 0x80000000 80091bc: ea4f 02c0 mov.w r2, r0, lsl #3 80091c0: ea4c 7050 orr.w r0, ip, r0, lsr #29 80091c4: f1b2 4f00 cmp.w r2, #2147483648 ; 0x80000000 80091c8: eb40 0083 adc.w r0, r0, r3, lsl #2 80091cc: bf08 it eq 80091ce: f020 0001 biceq.w r0, r0, #1 80091d2: 4770 bx lr 80091d4: f011 4f80 tst.w r1, #1073741824 ; 0x40000000 80091d8: d121 bne.n 800921e <__aeabi_d2f+0x7a> 80091da: f113 7238 adds.w r2, r3, #48234496 ; 0x2e00000 80091de: bfbc itt lt 80091e0: f001 4000 andlt.w r0, r1, #2147483648 ; 0x80000000 80091e4: 4770 bxlt lr 80091e6: f441 1180 orr.w r1, r1, #1048576 ; 0x100000 80091ea: ea4f 5252 mov.w r2, r2, lsr #21 80091ee: f1c2 0218 rsb r2, r2, #24 80091f2: f1c2 0c20 rsb ip, r2, #32 80091f6: fa10 f30c lsls.w r3, r0, ip 80091fa: fa20 f002 lsr.w r0, r0, r2 80091fe: bf18 it ne 8009200: f040 0001 orrne.w r0, r0, #1 8009204: ea4f 23c1 mov.w r3, r1, lsl #11 8009208: ea4f 23d3 mov.w r3, r3, lsr #11 800920c: fa03 fc0c lsl.w ip, r3, ip 8009210: ea40 000c orr.w r0, r0, ip 8009214: fa23 f302 lsr.w r3, r3, r2 8009218: ea4f 0343 mov.w r3, r3, lsl #1 800921c: e7cc b.n 80091b8 <__aeabi_d2f+0x14> 800921e: ea7f 5362 mvns.w r3, r2, asr #21 8009222: d107 bne.n 8009234 <__aeabi_d2f+0x90> 8009224: ea50 3301 orrs.w r3, r0, r1, lsl #12 8009228: bf1e ittt ne 800922a: f04f 40fe movne.w r0, #2130706432 ; 0x7f000000 800922e: f440 0040 orrne.w r0, r0, #12582912 ; 0xc00000 8009232: 4770 bxne lr 8009234: f001 4000 and.w r0, r1, #2147483648 ; 0x80000000 8009238: f040 40fe orr.w r0, r0, #2130706432 ; 0x7f000000 800923c: f440 0000 orr.w r0, r0, #8388608 ; 0x800000 8009240: 4770 bx lr 8009242: bf00 nop 08009244 <__aeabi_uldivmod>: 8009244: b94b cbnz r3, 800925a <__aeabi_uldivmod+0x16> 8009246: b942 cbnz r2, 800925a <__aeabi_uldivmod+0x16> 8009248: 2900 cmp r1, #0 800924a: bf08 it eq 800924c: 2800 cmpeq r0, #0 800924e: d002 beq.n 8009256 <__aeabi_uldivmod+0x12> 8009250: f04f 31ff mov.w r1, #4294967295 8009254: 4608 mov r0, r1 8009256: f001 b871 b.w 800a33c <__aeabi_idiv0> 800925a: b082 sub sp, #8 800925c: 46ec mov ip, sp 800925e: e92d 5000 stmdb sp!, {ip, lr} 8009262: f000 f81b bl 800929c <__gnu_uldivmod_helper> 8009266: f8dd e004 ldr.w lr, [sp, #4] 800926a: b002 add sp, #8 800926c: bc0c pop {r2, r3} 800926e: 4770 bx lr 08009270 <__gnu_ldivmod_helper>: 8009270: b5f8 push {r3, r4, r5, r6, r7, lr} 8009272: 4614 mov r4, r2 8009274: 4606 mov r6, r0 8009276: 460f mov r7, r1 8009278: 461d mov r5, r3 800927a: f001 f861 bl 800a340 <__divdi3> 800927e: fb04 f301 mul.w r3, r4, r1 8009282: fb00 3505 mla r5, r0, r5, r3 8009286: fba4 2300 umull r2, r3, r4, r0 800928a: 18eb adds r3, r5, r3 800928c: 9c06 ldr r4, [sp, #24] 800928e: 1ab2 subs r2, r6, r2 8009290: eb67 0303 sbc.w r3, r7, r3 8009294: e9c4 2300 strd r2, r3, [r4] 8009298: bdf8 pop {r3, r4, r5, r6, r7, pc} 800929a: bf00 nop 0800929c <__gnu_uldivmod_helper>: 800929c: b5f8 push {r3, r4, r5, r6, r7, lr} 800929e: 4614 mov r4, r2 80092a0: 4606 mov r6, r0 80092a2: 460f mov r7, r1 80092a4: 461d mov r5, r3 80092a6: f001 f9af bl 800a608 <__udivdi3> 80092aa: fb00 f505 mul.w r5, r0, r5 80092ae: fba0 2304 umull r2, r3, r0, r4 80092b2: fb04 5501 mla r5, r4, r1, r5 80092b6: 18eb adds r3, r5, r3 80092b8: 9c06 ldr r4, [sp, #24] 80092ba: 1ab2 subs r2, r6, r2 80092bc: eb67 0303 sbc.w r3, r7, r3 80092c0: e9c4 2300 strd r2, r3, [r4] 80092c4: bdf8 pop {r3, r4, r5, r6, r7, pc} 80092c6: bf00 nop 080092c8 <_Unwind_decode_target2>: 80092c8: 6803 ldr r3, [r0, #0] 80092ca: b103 cbz r3, 80092ce <_Unwind_decode_target2+0x6> 80092cc: 181b adds r3, r3, r0 80092ce: 4618 mov r0, r3 80092d0: 4770 bx lr 80092d2: bf00 nop 080092d4 : 80092d4: 6803 ldr r3, [r0, #0] 80092d6: 005a lsls r2, r3, #1 80092d8: bf4c ite mi 80092da: f043 4300 orrmi.w r3, r3, #2147483648 ; 0x80000000 80092de: f023 4300 bicpl.w r3, r3, #2147483648 ; 0x80000000 80092e2: 18c0 adds r0, r0, r3 80092e4: 4770 bx lr 80092e6: bf00 nop 080092e8 : 80092e8: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} 80092ec: 4604 mov r4, r0 80092ee: 4691 mov r9, r2 80092f0: b341 cbz r1, 8009344 80092f2: f101 3bff add.w fp, r1, #4294967295 80092f6: 46da mov sl, fp 80092f8: 2700 movs r7, #0 80092fa: eb07 010a add.w r1, r7, sl 80092fe: eb01 75d1 add.w r5, r1, r1, lsr #31 8009302: 106d asrs r5, r5, #1 8009304: eb04 06c5 add.w r6, r4, r5, lsl #3 8009308: 4630 mov r0, r6 800930a: f7ff ffe3 bl 80092d4 800930e: 4680 mov r8, r0 8009310: 1c68 adds r0, r5, #1 8009312: 45ab cmp fp, r5 8009314: eb04 00c0 add.w r0, r4, r0, lsl #3 8009318: d00d beq.n 8009336 800931a: f7ff ffdb bl 80092d4 800931e: 3801 subs r0, #1 8009320: 45c8 cmp r8, r9 8009322: d904 bls.n 800932e 8009324: 42bd cmp r5, r7 8009326: d009 beq.n 800933c 8009328: f105 3aff add.w sl, r5, #4294967295 800932c: e7e5 b.n 80092fa 800932e: 4548 cmp r0, r9 8009330: d205 bcs.n 800933e 8009332: 1c6f adds r7, r5, #1 8009334: e7e1 b.n 80092fa 8009336: f04f 30ff mov.w r0, #4294967295 800933a: e7f1 b.n 8009320 800933c: 2600 movs r6, #0 800933e: 4630 mov r0, r6 8009340: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} 8009344: 460e mov r6, r1 8009346: 4630 mov r0, r6 8009348: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} 0800934c : 800934c: b530 push {r4, r5, lr} 800934e: 4b2b ldr r3, [pc, #172] ; (80093fc ) 8009350: b083 sub sp, #12 8009352: 4604 mov r4, r0 8009354: 1e8d subs r5, r1, #2 8009356: 2b00 cmp r3, #0 8009358: d049 beq.n 80093ee 800935a: 4628 mov r0, r5 800935c: a901 add r1, sp, #4 800935e: f3af 8000 nop.w 8009362: 4603 mov r3, r0 8009364: 2800 cmp r0, #0 8009366: d022 beq.n 80093ae 8009368: 462a mov r2, r5 800936a: 4618 mov r0, r3 800936c: 9901 ldr r1, [sp, #4] 800936e: f7ff ffbb bl 80092e8 8009372: 4605 mov r5, r0 8009374: 2800 cmp r0, #0 8009376: d01d beq.n 80093b4 8009378: f7ff ffac bl 80092d4 800937c: 686b ldr r3, [r5, #4] 800937e: 64a0 str r0, [r4, #72] ; 0x48 8009380: 2b01 cmp r3, #1 8009382: d010 beq.n 80093a6 8009384: 1d28 adds r0, r5, #4 8009386: 2b00 cmp r3, #0 8009388: db22 blt.n 80093d0 800938a: f7ff ffa3 bl 80092d4 800938e: 2100 movs r1, #0 8009390: 64e0 str r0, [r4, #76] ; 0x4c 8009392: 6521 str r1, [r4, #80] ; 0x50 8009394: 6803 ldr r3, [r0, #0] 8009396: 2b00 cmp r3, #0 8009398: db0f blt.n 80093ba 800939a: f7ff ff9b bl 80092d4 800939e: 6120 str r0, [r4, #16] 80093a0: 2000 movs r0, #0 80093a2: b003 add sp, #12 80093a4: bd30 pop {r4, r5, pc} 80093a6: 2300 movs r3, #0 80093a8: 6123 str r3, [r4, #16] 80093aa: 2005 movs r0, #5 80093ac: e7f9 b.n 80093a2 80093ae: 6120 str r0, [r4, #16] 80093b0: 2009 movs r0, #9 80093b2: e7f6 b.n 80093a2 80093b4: 6120 str r0, [r4, #16] 80093b6: 2009 movs r0, #9 80093b8: e7f3 b.n 80093a2 80093ba: f3c3 6003 ubfx r0, r3, #24, #4 80093be: b158 cbz r0, 80093d8 80093c0: 2801 cmp r0, #1 80093c2: d00c beq.n 80093de 80093c4: 2802 cmp r0, #2 80093c6: d00e beq.n 80093e6 80093c8: 2000 movs r0, #0 80093ca: 6120 str r0, [r4, #16] 80093cc: 2009 movs r0, #9 80093ce: e7e8 b.n 80093a2 80093d0: 2201 movs r2, #1 80093d2: 64e0 str r0, [r4, #76] ; 0x4c 80093d4: 6522 str r2, [r4, #80] ; 0x50 80093d6: e7dd b.n 8009394 80093d8: 4b09 ldr r3, [pc, #36] ; (8009400 ) 80093da: 6123 str r3, [r4, #16] 80093dc: e7e1 b.n 80093a2 80093de: 4a09 ldr r2, [pc, #36] ; (8009404 ) 80093e0: 2000 movs r0, #0 80093e2: 6122 str r2, [r4, #16] 80093e4: e7dd b.n 80093a2 80093e6: 4908 ldr r1, [pc, #32] ; (8009408 ) 80093e8: 2000 movs r0, #0 80093ea: 6121 str r1, [r4, #16] 80093ec: e7d9 b.n 80093a2 80093ee: 4b07 ldr r3, [pc, #28] ; (800940c ) 80093f0: 4907 ldr r1, [pc, #28] ; (8009410 ) 80093f2: 1ac8 subs r0, r1, r3 80093f4: 10c2 asrs r2, r0, #3 80093f6: 9201 str r2, [sp, #4] 80093f8: e7b6 b.n 8009368 80093fa: bf00 nop 80093fc: 00000000 .word 0x00000000 8009400: 08009919 .word 0x08009919 8009404: 08009915 .word 0x08009915 8009408: 08009911 .word 0x08009911 800940c: 0800b008 .word 0x0800b008 8009410: 0800b0e8 .word 0x0800b0e8 08009414 : 8009414: 6803 ldr r3, [r0, #0] 8009416: b510 push {r4, lr} 8009418: 4604 mov r4, r0 800941a: 07d8 lsls r0, r3, #31 800941c: d406 bmi.n 800942c 800941e: 0799 lsls r1, r3, #30 8009420: f104 0048 add.w r0, r4, #72 ; 0x48 8009424: d509 bpl.n 800943a 8009426: f000 fd0d bl 8009e44 <__gnu_Unwind_Restore_VFP_D> 800942a: 6823 ldr r3, [r4, #0] 800942c: 075a lsls r2, r3, #29 800942e: d509 bpl.n 8009444 8009430: 0718 lsls r0, r3, #28 8009432: d50e bpl.n 8009452 8009434: 06d9 lsls r1, r3, #27 8009436: d513 bpl.n 8009460 8009438: bd10 pop {r4, pc} 800943a: f000 fcfb bl 8009e34 <__gnu_Unwind_Restore_VFP> 800943e: 6823 ldr r3, [r4, #0] 8009440: 075a lsls r2, r3, #29 8009442: d4f5 bmi.n 8009430 8009444: f104 00d0 add.w r0, r4, #208 ; 0xd0 8009448: f000 fd04 bl 8009e54 <__gnu_Unwind_Restore_VFP_D_16_to_31> 800944c: 6823 ldr r3, [r4, #0] 800944e: 0718 lsls r0, r3, #28 8009450: d4f0 bmi.n 8009434 8009452: f504 70d8 add.w r0, r4, #432 ; 0x1b0 8009456: f000 fd05 bl 8009e64 <__gnu_Unwind_Restore_WMMXD> 800945a: 6823 ldr r3, [r4, #0] 800945c: 06d9 lsls r1, r3, #27 800945e: d4eb bmi.n 8009438 8009460: f504 700c add.w r0, r4, #560 ; 0x230 8009464: e8bd 4010 ldmia.w sp!, {r4, lr} 8009468: f000 bd40 b.w 8009eec <__gnu_Unwind_Restore_WMMXC> 0800946c : 800946c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8009470: 1d0f adds r7, r1, #4 8009472: 4605 mov r5, r0 8009474: 4691 mov r9, r2 8009476: cf0f ldmia r7!, {r0, r1, r2, r3} 8009478: f5ad 6d91 sub.w sp, sp, #1160 ; 0x488 800947c: ac02 add r4, sp, #8 800947e: 1d26 adds r6, r4, #4 8009480: c60f stmia r6!, {r0, r1, r2, r3} 8009482: cf0f ldmia r7!, {r0, r1, r2, r3} 8009484: c60f stmia r6!, {r0, r1, r2, r3} 8009486: cf0f ldmia r7!, {r0, r1, r2, r3} 8009488: c60f stmia r6!, {r0, r1, r2, r3} 800948a: e897 000f ldmia.w r7, {r0, r1, r2, r3} 800948e: f8d5 800c ldr.w r8, [r5, #12] 8009492: f8d5 a018 ldr.w sl, [r5, #24] 8009496: 2700 movs r7, #0 8009498: e886 000f stmia.w r6, {r0, r1, r2, r3} 800949c: 6c21 ldr r1, [r4, #64] ; 0x40 800949e: 6027 str r7, [r4, #0] 80094a0: 4628 mov r0, r5 80094a2: f7ff ff53 bl 800934c 80094a6: 4606 mov r6, r0 80094a8: 45b9 cmp r9, r7 80094aa: bf14 ite ne 80094ac: f04f 090a movne.w r9, #10 80094b0: f04f 0909 moveq.w r9, #9 80094b4: b1fe cbz r6, 80094f6 80094b6: 6ba1 ldr r1, [r4, #56] ; 0x38 80094b8: f049 0910 orr.w r9, r9, #16 80094bc: 6461 str r1, [r4, #68] ; 0x44 80094be: 2001 movs r0, #1 80094c0: e88d 0410 stmia.w sp, {r4, sl} 80094c4: 4649 mov r1, r9 80094c6: 462a mov r2, r5 80094c8: 462b mov r3, r5 80094ca: 47c0 blx r8 80094cc: 2800 cmp r0, #0 80094ce: d12b bne.n 8009528 80094d0: 2e00 cmp r6, #0 80094d2: d12a bne.n 800952a 80094d4: 4620 mov r0, r4 80094d6: a992 add r1, sp, #584 ; 0x248 80094d8: f44f 7210 mov.w r2, #576 ; 0x240 80094dc: f001 e9ea blx 800a8b4 80094e0: 2f08 cmp r7, #8 80094e2: d128 bne.n 8009536 80094e4: 6c21 ldr r1, [r4, #64] ; 0x40 80094e6: 4628 mov r0, r5 80094e8: f7ff ff30 bl 800934c 80094ec: 4606 mov r6, r0 80094ee: f04f 0909 mov.w r9, #9 80094f2: 2e00 cmp r6, #0 80094f4: d1df bne.n 80094b6 80094f6: 6c20 ldr r0, [r4, #64] ; 0x40 80094f8: 4621 mov r1, r4 80094fa: f44f 7210 mov.w r2, #576 ; 0x240 80094fe: 6168 str r0, [r5, #20] 8009500: a892 add r0, sp, #584 ; 0x248 8009502: f001 e9d8 blx 800a8b4 8009506: 692f ldr r7, [r5, #16] 8009508: 4629 mov r1, r5 800950a: aa92 add r2, sp, #584 ; 0x248 800950c: 4648 mov r0, r9 800950e: 47b8 blx r7 8009510: 9ba0 ldr r3, [sp, #640] ; 0x280 8009512: 4607 mov r7, r0 8009514: 6463 str r3, [r4, #68] ; 0x44 8009516: 2001 movs r0, #1 8009518: e88d 0410 stmia.w sp, {r4, sl} 800951c: 4649 mov r1, r9 800951e: 462a mov r2, r5 8009520: 462b mov r3, r5 8009522: 47c0 blx r8 8009524: 2800 cmp r0, #0 8009526: d0d3 beq.n 80094d0 8009528: 2609 movs r6, #9 800952a: 4630 mov r0, r6 800952c: b022 add sp, #136 ; 0x88 800952e: f50d 6d80 add.w sp, sp, #1024 ; 0x400 8009532: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8009536: 2f07 cmp r7, #7 8009538: d1f6 bne.n 8009528 800953a: 1d20 adds r0, r4, #4 800953c: f000 fc6e bl 8009e1c <__restore_core_regs> 08009540 : 8009540: b538 push {r3, r4, r5, lr} 8009542: 4604 mov r4, r0 8009544: 460d mov r5, r1 8009546: 6c29 ldr r1, [r5, #64] ; 0x40 8009548: 4620 mov r0, r4 800954a: f7ff feff bl 800934c 800954e: b950 cbnz r0, 8009566 8009550: 6c2a ldr r2, [r5, #64] ; 0x40 8009552: 6923 ldr r3, [r4, #16] 8009554: 6162 str r2, [r4, #20] 8009556: 2001 movs r0, #1 8009558: 4621 mov r1, r4 800955a: 462a mov r2, r5 800955c: 4798 blx r3 800955e: 2808 cmp r0, #8 8009560: d0f1 beq.n 8009546 8009562: 2807 cmp r0, #7 8009564: d001 beq.n 800956a 8009566: f001 e99c blx 800a8a0 800956a: 1d28 adds r0, r5, #4 800956c: f000 fc56 bl 8009e1c <__restore_core_regs> 08009570 <_Unwind_VRS_Get>: 8009570: b911 cbnz r1, 8009578 <_Unwind_VRS_Get+0x8> 8009572: b133 cbz r3, 8009582 <_Unwind_VRS_Get+0x12> 8009574: 2002 movs r0, #2 8009576: 4770 bx lr 8009578: 2904 cmp r1, #4 800957a: bf8c ite hi 800957c: 2002 movhi r0, #2 800957e: 2001 movls r0, #1 8009580: 4770 bx lr 8009582: 2a0f cmp r2, #15 8009584: d901 bls.n 800958a <_Unwind_VRS_Get+0x1a> 8009586: 2002 movs r0, #2 8009588: 4770 bx lr 800958a: eb00 0182 add.w r1, r0, r2, lsl #2 800958e: 4618 mov r0, r3 8009590: 684a ldr r2, [r1, #4] 8009592: 9b00 ldr r3, [sp, #0] 8009594: 601a str r2, [r3, #0] 8009596: 4770 bx lr 08009598 <_Unwind_GetGR>: 8009598: b510 push {r4, lr} 800959a: 460a mov r2, r1 800959c: b084 sub sp, #16 800959e: 2100 movs r1, #0 80095a0: 460b mov r3, r1 80095a2: ac03 add r4, sp, #12 80095a4: 9400 str r4, [sp, #0] 80095a6: f7ff ffe3 bl 8009570 <_Unwind_VRS_Get> 80095aa: 9803 ldr r0, [sp, #12] 80095ac: b004 add sp, #16 80095ae: bd10 pop {r4, pc} 080095b0 <_Unwind_VRS_Set>: 80095b0: b911 cbnz r1, 80095b8 <_Unwind_VRS_Set+0x8> 80095b2: b133 cbz r3, 80095c2 <_Unwind_VRS_Set+0x12> 80095b4: 2002 movs r0, #2 80095b6: 4770 bx lr 80095b8: 2904 cmp r1, #4 80095ba: bf8c ite hi 80095bc: 2002 movhi r0, #2 80095be: 2001 movls r0, #1 80095c0: 4770 bx lr 80095c2: 2a0f cmp r2, #15 80095c4: d901 bls.n 80095ca <_Unwind_VRS_Set+0x1a> 80095c6: 2002 movs r0, #2 80095c8: 4770 bx lr 80095ca: 9900 ldr r1, [sp, #0] 80095cc: eb00 0282 add.w r2, r0, r2, lsl #2 80095d0: 6809 ldr r1, [r1, #0] 80095d2: 4618 mov r0, r3 80095d4: 6051 str r1, [r2, #4] 80095d6: 4770 bx lr 080095d8 <_Unwind_SetGR>: 80095d8: b510 push {r4, lr} 80095da: b084 sub sp, #16 80095dc: ab04 add r3, sp, #16 80095de: 460c mov r4, r1 80095e0: f843 2d04 str.w r2, [r3, #-4]! 80095e4: 2100 movs r1, #0 80095e6: 9300 str r3, [sp, #0] 80095e8: 4622 mov r2, r4 80095ea: 460b mov r3, r1 80095ec: f7ff ffe0 bl 80095b0 <_Unwind_VRS_Set> 80095f0: b004 add sp, #16 80095f2: bd10 pop {r4, pc} 080095f4 <__gnu_unwind_pr_common>: 80095f4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} 80095f8: 6ccd ldr r5, [r1, #76] ; 0x4c 80095fa: b08b sub sp, #44 ; 0x2c 80095fc: 460c mov r4, r1 80095fe: f855 1b04 ldr.w r1, [r5], #4 8009602: 4617 mov r7, r2 8009604: f000 0208 and.w r2, r0, #8 8009608: 461e mov r6, r3 800960a: 9203 str r2, [sp, #12] 800960c: f000 0803 and.w r8, r0, #3 8009610: 9507 str r5, [sp, #28] 8009612: 2b00 cmp r3, #0 8009614: f040 80cf bne.w 80097b6 <__gnu_unwind_pr_common+0x1c2> 8009618: 0209 lsls r1, r1, #8 800961a: 9106 str r1, [sp, #24] 800961c: 6d21 ldr r1, [r4, #80] ; 0x50 800961e: f88d 3021 strb.w r3, [sp, #33] ; 0x21 8009622: 2303 movs r3, #3 8009624: f1b8 0f02 cmp.w r8, #2 8009628: f88d 3020 strb.w r3, [sp, #32] 800962c: bf08 it eq 800962e: 6ba5 ldreq r5, [r4, #56] ; 0x38 8009630: f011 0301 ands.w r3, r1, #1 8009634: f040 80d3 bne.w 80097de <__gnu_unwind_pr_common+0x1ea> 8009638: 9301 str r3, [sp, #4] 800963a: f104 0358 add.w r3, r4, #88 ; 0x58 800963e: 9302 str r3, [sp, #8] 8009640: f8d5 9000 ldr.w r9, [r5] 8009644: f1b9 0f00 cmp.w r9, #0 8009648: f000 80cb beq.w 80097e2 <__gnu_unwind_pr_common+0x1ee> 800964c: 2e02 cmp r6, #2 800964e: f000 80ae beq.w 80097ae <__gnu_unwind_pr_common+0x1ba> 8009652: f8b5 9000 ldrh.w r9, [r5] 8009656: f8b5 a002 ldrh.w sl, [r5, #2] 800965a: 3504 adds r5, #4 800965c: 6ca2 ldr r2, [r4, #72] ; 0x48 800965e: 210f movs r1, #15 8009660: f02a 0b01 bic.w fp, sl, #1 8009664: 4638 mov r0, r7 8009666: 4493 add fp, r2 8009668: f7ff ff96 bl 8009598 <_Unwind_GetGR> 800966c: 4583 cmp fp, r0 800966e: d818 bhi.n 80096a2 <__gnu_unwind_pr_common+0xae> 8009670: f029 0c01 bic.w ip, r9, #1 8009674: 44e3 add fp, ip 8009676: f00a 0a01 and.w sl, sl, #1 800967a: f009 0301 and.w r3, r9, #1 800967e: 4558 cmp r0, fp 8009680: ea43 094a orr.w r9, r3, sl, lsl #1 8009684: bf2c ite cs 8009686: 2000 movcs r0, #0 8009688: 2001 movcc r0, #1 800968a: f1b9 0f01 cmp.w r9, #1 800968e: d012 beq.n 80096b6 <__gnu_unwind_pr_common+0xc2> 8009690: d232 bcs.n 80096f8 <__gnu_unwind_pr_common+0x104> 8009692: f1b8 0f00 cmp.w r8, #0 8009696: d002 beq.n 800969e <__gnu_unwind_pr_common+0xaa> 8009698: 2800 cmp r0, #0 800969a: f040 811d bne.w 80098d8 <__gnu_unwind_pr_common+0x2e4> 800969e: 3504 adds r5, #4 80096a0: e7ce b.n 8009640 <__gnu_unwind_pr_common+0x4c> 80096a2: f00a 0a01 and.w sl, sl, #1 80096a6: f009 0301 and.w r3, r9, #1 80096aa: ea43 094a orr.w r9, r3, sl, lsl #1 80096ae: 2000 movs r0, #0 80096b0: f1b9 0f01 cmp.w r9, #1 80096b4: d1ec bne.n 8009690 <__gnu_unwind_pr_common+0x9c> 80096b6: f1b8 0f00 cmp.w r8, #0 80096ba: f040 80b6 bne.w 800982a <__gnu_unwind_pr_common+0x236> 80096be: b1c8 cbz r0, 80096f4 <__gnu_unwind_pr_common+0x100> 80096c0: 686b ldr r3, [r5, #4] 80096c2: f8d5 9000 ldr.w r9, [r5] 80096c6: 1c9a adds r2, r3, #2 80096c8: d019 beq.n 80096fe <__gnu_unwind_pr_common+0x10a> 80096ca: 9a02 ldr r2, [sp, #8] 80096cc: 3301 adds r3, #1 80096ce: 9209 str r2, [sp, #36] ; 0x24 80096d0: d00d beq.n 80096ee <__gnu_unwind_pr_common+0xfa> 80096d2: 1d28 adds r0, r5, #4 80096d4: f7ff fdf8 bl 80092c8 <_Unwind_decode_target2> 80096d8: ea4f 72d9 mov.w r2, r9, lsr #31 80096dc: 4601 mov r1, r0 80096de: ab09 add r3, sp, #36 ; 0x24 80096e0: 4620 mov r0, r4 80096e2: f3af 8000 nop.w 80096e6: 2800 cmp r0, #0 80096e8: f000 80f2 beq.w 80098d0 <__gnu_unwind_pr_common+0x2dc> 80096ec: 9a09 ldr r2, [sp, #36] ; 0x24 80096ee: 2a00 cmp r2, #0 80096f0: f040 80ba bne.w 8009868 <__gnu_unwind_pr_common+0x274> 80096f4: 3508 adds r5, #8 80096f6: e7a3 b.n 8009640 <__gnu_unwind_pr_common+0x4c> 80096f8: f1b9 0f02 cmp.w r9, #2 80096fc: d003 beq.n 8009706 <__gnu_unwind_pr_common+0x112> 80096fe: 2009 movs r0, #9 8009700: b00b add sp, #44 ; 0x2c 8009702: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} 8009706: 682b ldr r3, [r5, #0] 8009708: f023 4200 bic.w r2, r3, #2147483648 ; 0x80000000 800970c: 9200 str r2, [sp, #0] 800970e: f1b8 0f00 cmp.w r8, #0 8009712: d171 bne.n 80097f8 <__gnu_unwind_pr_common+0x204> 8009714: 2800 cmp r0, #0 8009716: d043 beq.n 80097a0 <__gnu_unwind_pr_common+0x1ac> 8009718: 9803 ldr r0, [sp, #12] 800971a: 2800 cmp r0, #0 800971c: f040 80a1 bne.w 8009862 <__gnu_unwind_pr_common+0x26e> 8009720: 9800 ldr r0, [sp, #0] 8009722: 2800 cmp r0, #0 8009724: f000 80a0 beq.w 8009868 <__gnu_unwind_pr_common+0x274> 8009728: 9b00 ldr r3, [sp, #0] 800972a: f8dd 900c ldr.w r9, [sp, #12] 800972e: 07db lsls r3, r3, #31 8009730: f105 0a04 add.w sl, r5, #4 8009734: f140 80b4 bpl.w 80098a0 <__gnu_unwind_pr_common+0x2ac> 8009738: f8cd 8010 str.w r8, [sp, #16] 800973c: 9605 str r6, [sp, #20] 800973e: 46a8 mov r8, r5 8009740: 9e02 ldr r6, [sp, #8] 8009742: e012 b.n 800976a <__gnu_unwind_pr_common+0x176> 8009744: 9900 ldr r1, [sp, #0] 8009746: 428d cmp r5, r1 8009748: f000 80d9 beq.w 80098fe <__gnu_unwind_pr_common+0x30a> 800974c: 9609 str r6, [sp, #36] ; 0x24 800974e: f7ff fdbb bl 80092c8 <_Unwind_decode_target2> 8009752: 465a mov r2, fp 8009754: 4601 mov r1, r0 8009756: ab09 add r3, sp, #36 ; 0x24 8009758: 4620 mov r0, r4 800975a: f3af 8000 nop.w 800975e: 46a9 mov r9, r5 8009760: b9b0 cbnz r0, 8009790 <__gnu_unwind_pr_common+0x19c> 8009762: f10a 0a04 add.w sl, sl, #4 8009766: f105 0901 add.w r9, r5, #1 800976a: 4650 mov r0, sl 800976c: 9609 str r6, [sp, #36] ; 0x24 800976e: f7ff fdab bl 80092c8 <_Unwind_decode_target2> 8009772: ab09 add r3, sp, #36 ; 0x24 8009774: 4601 mov r1, r0 8009776: 2200 movs r2, #0 8009778: 4620 mov r0, r4 800977a: f3af 8000 nop.w 800977e: f10a 0a04 add.w sl, sl, #4 8009782: 4683 mov fp, r0 8009784: f109 0501 add.w r5, r9, #1 8009788: 4650 mov r0, sl 800978a: f1bb 0f00 cmp.w fp, #0 800978e: d0d9 beq.n 8009744 <__gnu_unwind_pr_common+0x150> 8009790: 4645 mov r5, r8 8009792: 9e05 ldr r6, [sp, #20] 8009794: f8dd 8010 ldr.w r8, [sp, #16] 8009798: 9a00 ldr r2, [sp, #0] 800979a: 454a cmp r2, r9 800979c: d064 beq.n 8009868 <__gnu_unwind_pr_common+0x274> 800979e: 682b ldr r3, [r5, #0] 80097a0: 2b00 cmp r3, #0 80097a2: db7b blt.n 800989c <__gnu_unwind_pr_common+0x2a8> 80097a4: 9900 ldr r1, [sp, #0] 80097a6: 1c48 adds r0, r1, #1 80097a8: eb05 0580 add.w r5, r5, r0, lsl #2 80097ac: e748 b.n 8009640 <__gnu_unwind_pr_common+0x4c> 80097ae: f8d5 a004 ldr.w sl, [r5, #4] 80097b2: 3508 adds r5, #8 80097b4: e752 b.n 800965c <__gnu_unwind_pr_common+0x68> 80097b6: 040b lsls r3, r1, #16 80097b8: f3c1 4007 ubfx r0, r1, #16, #8 80097bc: 6d21 ldr r1, [r4, #80] ; 0x50 80097be: 9306 str r3, [sp, #24] 80097c0: 2202 movs r2, #2 80097c2: f1b8 0f02 cmp.w r8, #2 80097c6: eb05 0580 add.w r5, r5, r0, lsl #2 80097ca: bf08 it eq 80097cc: 6ba5 ldreq r5, [r4, #56] ; 0x38 80097ce: f88d 0021 strb.w r0, [sp, #33] ; 0x21 80097d2: f011 0301 ands.w r3, r1, #1 80097d6: f88d 2020 strb.w r2, [sp, #32] 80097da: f43f af2d beq.w 8009638 <__gnu_unwind_pr_common+0x44> 80097de: 2000 movs r0, #0 80097e0: 9001 str r0, [sp, #4] 80097e2: 4638 mov r0, r7 80097e4: a906 add r1, sp, #24 80097e6: f000 fc19 bl 800a01c <__gnu_unwind_execute> 80097ea: 2800 cmp r0, #0 80097ec: d187 bne.n 80096fe <__gnu_unwind_pr_common+0x10a> 80097ee: 9a01 ldr r2, [sp, #4] 80097f0: 2a00 cmp r2, #0 80097f2: d143 bne.n 800987c <__gnu_unwind_pr_common+0x288> 80097f4: 2008 movs r0, #8 80097f6: e783 b.n 8009700 <__gnu_unwind_pr_common+0x10c> 80097f8: 210d movs r1, #13 80097fa: 4638 mov r0, r7 80097fc: f8d4 9020 ldr.w r9, [r4, #32] 8009800: f7ff feca bl 8009598 <_Unwind_GetGR> 8009804: 4581 cmp r9, r0 8009806: d1ca bne.n 800979e <__gnu_unwind_pr_common+0x1aa> 8009808: 6aa2 ldr r2, [r4, #40] ; 0x28 800980a: 4295 cmp r5, r2 800980c: d1c7 bne.n 800979e <__gnu_unwind_pr_common+0x1aa> 800980e: 9800 ldr r0, [sp, #0] 8009810: 1d29 adds r1, r5, #4 8009812: 2200 movs r2, #0 8009814: 2304 movs r3, #4 8009816: 62a0 str r0, [r4, #40] ; 0x28 8009818: 62e2 str r2, [r4, #44] ; 0x2c 800981a: 6323 str r3, [r4, #48] ; 0x30 800981c: 6361 str r1, [r4, #52] ; 0x34 800981e: 6828 ldr r0, [r5, #0] 8009820: 2800 cmp r0, #0 8009822: db6e blt.n 8009902 <__gnu_unwind_pr_common+0x30e> 8009824: 2201 movs r2, #1 8009826: 9201 str r2, [sp, #4] 8009828: e7bc b.n 80097a4 <__gnu_unwind_pr_common+0x1b0> 800982a: 210d movs r1, #13 800982c: 4638 mov r0, r7 800982e: f8d4 9020 ldr.w r9, [r4, #32] 8009832: f7ff feb1 bl 8009598 <_Unwind_GetGR> 8009836: 4581 cmp r9, r0 8009838: f47f af5c bne.w 80096f4 <__gnu_unwind_pr_common+0x100> 800983c: 6aa1 ldr r1, [r4, #40] ; 0x28 800983e: 428d cmp r5, r1 8009840: f47f af58 bne.w 80096f4 <__gnu_unwind_pr_common+0x100> 8009844: 4628 mov r0, r5 8009846: f7ff fd45 bl 80092d4 800984a: 210f movs r1, #15 800984c: 4602 mov r2, r0 800984e: 4638 mov r0, r7 8009850: f7ff fec2 bl 80095d8 <_Unwind_SetGR> 8009854: 4638 mov r0, r7 8009856: 2100 movs r1, #0 8009858: 4622 mov r2, r4 800985a: f7ff febd bl 80095d8 <_Unwind_SetGR> 800985e: 2007 movs r0, #7 8009860: e74e b.n 8009700 <__gnu_unwind_pr_common+0x10c> 8009862: 9900 ldr r1, [sp, #0] 8009864: 2900 cmp r1, #0 8009866: d19b bne.n 80097a0 <__gnu_unwind_pr_common+0x1ac> 8009868: 4638 mov r0, r7 800986a: 210d movs r1, #13 800986c: f7ff fe94 bl 8009598 <_Unwind_GetGR> 8009870: 9b09 ldr r3, [sp, #36] ; 0x24 8009872: 6220 str r0, [r4, #32] 8009874: 6263 str r3, [r4, #36] ; 0x24 8009876: 62a5 str r5, [r4, #40] ; 0x28 8009878: 2006 movs r0, #6 800987a: e741 b.n 8009700 <__gnu_unwind_pr_common+0x10c> 800987c: 210f movs r1, #15 800987e: 4638 mov r0, r7 8009880: f7ff fe8a bl 8009598 <_Unwind_GetGR> 8009884: 210e movs r1, #14 8009886: 4602 mov r2, r0 8009888: 4638 mov r0, r7 800988a: f7ff fea5 bl 80095d8 <_Unwind_SetGR> 800988e: 4638 mov r0, r7 8009890: 210f movs r1, #15 8009892: 4a1e ldr r2, [pc, #120] ; (800990c <__gnu_unwind_pr_common+0x318>) 8009894: f7ff fea0 bl 80095d8 <_Unwind_SetGR> 8009898: 2007 movs r0, #7 800989a: e731 b.n 8009700 <__gnu_unwind_pr_common+0x10c> 800989c: 3504 adds r5, #4 800989e: e781 b.n 80097a4 <__gnu_unwind_pr_common+0x1b0> 80098a0: 9902 ldr r1, [sp, #8] 80098a2: 4650 mov r0, sl 80098a4: 9109 str r1, [sp, #36] ; 0x24 80098a6: f7ff fd0f bl 80092c8 <_Unwind_decode_target2> 80098aa: 9a03 ldr r2, [sp, #12] 80098ac: 4601 mov r1, r0 80098ae: ab09 add r3, sp, #36 ; 0x24 80098b0: 4620 mov r0, r4 80098b2: f3af 8000 nop.w 80098b6: 2800 cmp r0, #0 80098b8: f47f af6e bne.w 8009798 <__gnu_unwind_pr_common+0x1a4> 80098bc: f8cd 8010 str.w r8, [sp, #16] 80098c0: 9605 str r6, [sp, #20] 80098c2: f10a 0a04 add.w sl, sl, #4 80098c6: f04f 0901 mov.w r9, #1 80098ca: 46a8 mov r8, r5 80098cc: 9e02 ldr r6, [sp, #8] 80098ce: e74c b.n 800976a <__gnu_unwind_pr_common+0x176> 80098d0: f8cd 8024 str.w r8, [sp, #36] ; 0x24 80098d4: 3508 adds r5, #8 80098d6: e6b3 b.n 8009640 <__gnu_unwind_pr_common+0x4c> 80098d8: 4628 mov r0, r5 80098da: f7ff fcfb bl 80092d4 80098de: 3504 adds r5, #4 80098e0: 4606 mov r6, r0 80098e2: 63a5 str r5, [r4, #56] ; 0x38 80098e4: 4620 mov r0, r4 80098e6: f3af 8000 nop.w 80098ea: 2800 cmp r0, #0 80098ec: f43f af07 beq.w 80096fe <__gnu_unwind_pr_common+0x10a> 80098f0: 4638 mov r0, r7 80098f2: 210f movs r1, #15 80098f4: 4632 mov r2, r6 80098f6: f7ff fe6f bl 80095d8 <_Unwind_SetGR> 80098fa: 2007 movs r0, #7 80098fc: e700 b.n 8009700 <__gnu_unwind_pr_common+0x10c> 80098fe: 4645 mov r5, r8 8009900: e7b2 b.n 8009868 <__gnu_unwind_pr_common+0x274> 8009902: 9b00 ldr r3, [sp, #0] 8009904: 1c59 adds r1, r3, #1 8009906: eb05 0081 add.w r0, r5, r1, lsl #2 800990a: e79c b.n 8009846 <__gnu_unwind_pr_common+0x252> 800990c: 00000000 .word 0x00000000 08009910 <__aeabi_unwind_cpp_pr2>: 8009910: 2302 movs r3, #2 8009912: e66f b.n 80095f4 <__gnu_unwind_pr_common> 08009914 <__aeabi_unwind_cpp_pr1>: 8009914: 2301 movs r3, #1 8009916: e66d b.n 80095f4 <__gnu_unwind_pr_common> 08009918 <__aeabi_unwind_cpp_pr0>: 8009918: 2300 movs r3, #0 800991a: e66b b.n 80095f4 <__gnu_unwind_pr_common> 0800991c <_Unwind_VRS_Pop>: 800991c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8009920: 4604 mov r4, r0 8009922: b0e8 sub sp, #416 ; 0x1a0 8009924: 2904 cmp r1, #4 8009926: d80c bhi.n 8009942 <_Unwind_VRS_Pop+0x26> 8009928: e8df f001 tbb [pc, r1] 800992c: 93910338 .word 0x93910338 8009930: 0f .byte 0x0f 8009931: 00 .byte 0x00 8009932: 0c15 lsrs r5, r2, #16 8009934: 2b01 cmp r3, #1 8009936: b296 uxth r6, r2 8009938: f000 8178 beq.w 8009c2c <_Unwind_VRS_Pop+0x310> 800993c: 2b05 cmp r3, #5 800993e: f000 80c7 beq.w 8009ad0 <_Unwind_VRS_Pop+0x1b4> 8009942: 2002 movs r0, #2 8009944: b068 add sp, #416 ; 0x1a0 8009946: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 800994a: 2b00 cmp r3, #0 800994c: d1f9 bne.n 8009942 <_Unwind_VRS_Pop+0x26> 800994e: 2a10 cmp r2, #16 8009950: d8f7 bhi.n 8009942 <_Unwind_VRS_Pop+0x26> 8009952: 6823 ldr r3, [r4, #0] 8009954: 06d9 lsls r1, r3, #27 8009956: f100 8173 bmi.w 8009c40 <_Unwind_VRS_Pop+0x324> 800995a: a864 add r0, sp, #400 ; 0x190 800995c: 9201 str r2, [sp, #4] 800995e: f000 facf bl 8009f00 <__gnu_Unwind_Save_WMMXC> 8009962: 9a01 ldr r2, [sp, #4] 8009964: 6ba3 ldr r3, [r4, #56] ; 0x38 8009966: 07d0 lsls r0, r2, #31 8009968: bf44 itt mi 800996a: f853 0b04 ldrmi.w r0, [r3], #4 800996e: 9064 strmi r0, [sp, #400] ; 0x190 8009970: 0791 lsls r1, r2, #30 8009972: bf44 itt mi 8009974: f853 1b04 ldrmi.w r1, [r3], #4 8009978: 9165 strmi r1, [sp, #404] ; 0x194 800997a: 0750 lsls r0, r2, #29 800997c: bf44 itt mi 800997e: f853 1b04 ldrmi.w r1, [r3], #4 8009982: 9166 strmi r1, [sp, #408] ; 0x198 8009984: 0711 lsls r1, r2, #28 8009986: bf48 it mi 8009988: f853 2b04 ldrmi.w r2, [r3], #4 800998c: a864 add r0, sp, #400 ; 0x190 800998e: 63a3 str r3, [r4, #56] ; 0x38 8009990: bf48 it mi 8009992: 9267 strmi r2, [sp, #412] ; 0x19c 8009994: f000 faaa bl 8009eec <__gnu_Unwind_Restore_WMMXC> 8009998: 2000 movs r0, #0 800999a: e7d3 b.n 8009944 <_Unwind_VRS_Pop+0x28> 800999c: 2b00 cmp r3, #0 800999e: d1d0 bne.n 8009942 <_Unwind_VRS_Pop+0x26> 80099a0: 6ba3 ldr r3, [r4, #56] ; 0x38 80099a2: 07d0 lsls r0, r2, #31 80099a4: b291 uxth r1, r2 80099a6: bf44 itt mi 80099a8: f853 2b04 ldrmi.w r2, [r3], #4 80099ac: 6062 strmi r2, [r4, #4] 80099ae: 078a lsls r2, r1, #30 80099b0: bf44 itt mi 80099b2: f853 2b04 ldrmi.w r2, [r3], #4 80099b6: 60a2 strmi r2, [r4, #8] 80099b8: 0748 lsls r0, r1, #29 80099ba: bf44 itt mi 80099bc: f853 2b04 ldrmi.w r2, [r3], #4 80099c0: 60e2 strmi r2, [r4, #12] 80099c2: 070a lsls r2, r1, #28 80099c4: bf44 itt mi 80099c6: f853 2b04 ldrmi.w r2, [r3], #4 80099ca: 6122 strmi r2, [r4, #16] 80099cc: 06c8 lsls r0, r1, #27 80099ce: bf44 itt mi 80099d0: f853 2b04 ldrmi.w r2, [r3], #4 80099d4: 6162 strmi r2, [r4, #20] 80099d6: 068a lsls r2, r1, #26 80099d8: bf44 itt mi 80099da: f853 2b04 ldrmi.w r2, [r3], #4 80099de: 61a2 strmi r2, [r4, #24] 80099e0: 0648 lsls r0, r1, #25 80099e2: bf44 itt mi 80099e4: f853 2b04 ldrmi.w r2, [r3], #4 80099e8: 61e2 strmi r2, [r4, #28] 80099ea: 060a lsls r2, r1, #24 80099ec: bf44 itt mi 80099ee: f853 2b04 ldrmi.w r2, [r3], #4 80099f2: 6222 strmi r2, [r4, #32] 80099f4: 05c8 lsls r0, r1, #23 80099f6: bf44 itt mi 80099f8: f853 2b04 ldrmi.w r2, [r3], #4 80099fc: 6262 strmi r2, [r4, #36] ; 0x24 80099fe: 058a lsls r2, r1, #22 8009a00: bf44 itt mi 8009a02: f853 2b04 ldrmi.w r2, [r3], #4 8009a06: 62a2 strmi r2, [r4, #40] ; 0x28 8009a08: 0548 lsls r0, r1, #21 8009a0a: bf44 itt mi 8009a0c: f853 2b04 ldrmi.w r2, [r3], #4 8009a10: 62e2 strmi r2, [r4, #44] ; 0x2c 8009a12: 050a lsls r2, r1, #20 8009a14: bf44 itt mi 8009a16: f853 2b04 ldrmi.w r2, [r3], #4 8009a1a: 6322 strmi r2, [r4, #48] ; 0x30 8009a1c: 04c8 lsls r0, r1, #19 8009a1e: bf44 itt mi 8009a20: f853 2b04 ldrmi.w r2, [r3], #4 8009a24: 6362 strmi r2, [r4, #52] ; 0x34 8009a26: f411 5000 ands.w r0, r1, #8192 ; 0x2000 8009a2a: bf1c itt ne 8009a2c: f853 2b04 ldrne.w r2, [r3], #4 8009a30: 63a2 strne r2, [r4, #56] ; 0x38 8009a32: 044a lsls r2, r1, #17 8009a34: bf44 itt mi 8009a36: f853 2b04 ldrmi.w r2, [r3], #4 8009a3a: 63e2 strmi r2, [r4, #60] ; 0x3c 8009a3c: 040a lsls r2, r1, #16 8009a3e: bf44 itt mi 8009a40: f853 2b04 ldrmi.w r2, [r3], #4 8009a44: 6422 strmi r2, [r4, #64] ; 0x40 8009a46: 2800 cmp r0, #0 8009a48: d140 bne.n 8009acc <_Unwind_VRS_Pop+0x1b0> 8009a4a: 63a3 str r3, [r4, #56] ; 0x38 8009a4c: e77a b.n 8009944 <_Unwind_VRS_Pop+0x28> 8009a4e: 2001 movs r0, #1 8009a50: e778 b.n 8009944 <_Unwind_VRS_Pop+0x28> 8009a52: 2b03 cmp r3, #3 8009a54: f47f af75 bne.w 8009942 <_Unwind_VRS_Pop+0x26> 8009a58: 0c16 lsrs r6, r2, #16 8009a5a: b295 uxth r5, r2 8009a5c: 19aa adds r2, r5, r6 8009a5e: 2a10 cmp r2, #16 8009a60: f63f af6f bhi.w 8009942 <_Unwind_VRS_Pop+0x26> 8009a64: 6823 ldr r3, [r4, #0] 8009a66: 0718 lsls r0, r3, #28 8009a68: f100 810b bmi.w 8009c82 <_Unwind_VRS_Pop+0x366> 8009a6c: a844 add r0, sp, #272 ; 0x110 8009a6e: f000 fa1b bl 8009ea8 <__gnu_Unwind_Save_WMMXD> 8009a72: 6ba7 ldr r7, [r4, #56] ; 0x38 8009a74: ea4f 0e45 mov.w lr, r5, lsl #1 8009a78: 463b mov r3, r7 8009a7a: b30d cbz r5, 8009ac0 <_Unwind_VRS_Pop+0x1a4> 8009a7c: a944 add r1, sp, #272 ; 0x110 8009a7e: f10e 3cff add.w ip, lr, #4294967295 8009a82: eb01 06c6 add.w r6, r1, r6, lsl #3 8009a86: f853 0b04 ldr.w r0, [r3], #4 8009a8a: 4662 mov r2, ip 8009a8c: f00c 0101 and.w r1, ip, #1 8009a90: f846 0b04 str.w r0, [r6], #4 8009a94: b192 cbz r2, 8009abc <_Unwind_VRS_Pop+0x1a0> 8009a96: b129 cbz r1, 8009aa4 <_Unwind_VRS_Pop+0x188> 8009a98: f853 1b04 ldr.w r1, [r3], #4 8009a9c: 3a01 subs r2, #1 8009a9e: f846 1b04 str.w r1, [r6], #4 8009aa2: d00b beq.n 8009abc <_Unwind_VRS_Pop+0x1a0> 8009aa4: 4618 mov r0, r3 8009aa6: 4631 mov r1, r6 8009aa8: f850 5b04 ldr.w r5, [r0], #4 8009aac: f841 5b04 str.w r5, [r1], #4 8009ab0: 685d ldr r5, [r3, #4] 8009ab2: 1d03 adds r3, r0, #4 8009ab4: 6075 str r5, [r6, #4] 8009ab6: 1d0e adds r6, r1, #4 8009ab8: 3a02 subs r2, #2 8009aba: d1f3 bne.n 8009aa4 <_Unwind_VRS_Pop+0x188> 8009abc: eb07 038e add.w r3, r7, lr, lsl #2 8009ac0: a844 add r0, sp, #272 ; 0x110 8009ac2: 63a3 str r3, [r4, #56] ; 0x38 8009ac4: f000 f9ce bl 8009e64 <__gnu_Unwind_Restore_WMMXD> 8009ac8: 2000 movs r0, #0 8009aca: e73b b.n 8009944 <_Unwind_VRS_Pop+0x28> 8009acc: 2000 movs r0, #0 8009ace: e739 b.n 8009944 <_Unwind_VRS_Pop+0x28> 8009ad0: 1977 adds r7, r6, r5 8009ad2: 2220 movs r2, #32 8009ad4: 42ba cmp r2, r7 8009ad6: f4ff af34 bcc.w 8009942 <_Unwind_VRS_Pop+0x26> 8009ada: 2b01 cmp r3, #1 8009adc: f000 80a9 beq.w 8009c32 <_Unwind_VRS_Pop+0x316> 8009ae0: 2d0f cmp r5, #15 8009ae2: f240 80a9 bls.w 8009c38 <_Unwind_VRS_Pop+0x31c> 8009ae6: 4637 mov r7, r6 8009ae8: b1f6 cbz r6, 8009b28 <_Unwind_VRS_Pop+0x20c> 8009aea: 2b05 cmp r3, #5 8009aec: f47f af29 bne.w 8009942 <_Unwind_VRS_Pop+0x26> 8009af0: 2d0f cmp r5, #15 8009af2: d811 bhi.n 8009b18 <_Unwind_VRS_Pop+0x1fc> 8009af4: 6822 ldr r2, [r4, #0] 8009af6: 07d0 lsls r0, r2, #31 8009af8: d50e bpl.n 8009b18 <_Unwind_VRS_Pop+0x1fc> 8009afa: f022 0101 bic.w r1, r2, #1 8009afe: 2b05 cmp r3, #5 8009b00: 6021 str r1, [r4, #0] 8009b02: 4620 mov r0, r4 8009b04: f000 80da beq.w 8009cbc <_Unwind_VRS_Pop+0x3a0> 8009b08: f022 0203 bic.w r2, r2, #3 8009b0c: f840 2b48 str.w r2, [r0], #72 8009b10: 9301 str r3, [sp, #4] 8009b12: f000 f993 bl 8009e3c <__gnu_Unwind_Save_VFP> 8009b16: 9b01 ldr r3, [sp, #4] 8009b18: b11f cbz r7, 8009b22 <_Unwind_VRS_Pop+0x206> 8009b1a: 6822 ldr r2, [r4, #0] 8009b1c: 0751 lsls r1, r2, #29 8009b1e: f100 80b8 bmi.w 8009c92 <_Unwind_VRS_Pop+0x376> 8009b22: 2b01 cmp r3, #1 8009b24: f000 80bf beq.w 8009ca6 <_Unwind_VRS_Pop+0x38a> 8009b28: 2d0f cmp r5, #15 8009b2a: d975 bls.n 8009c18 <_Unwind_VRS_Pop+0x2fc> 8009b2c: 2f00 cmp r7, #0 8009b2e: f040 80a0 bne.w 8009c72 <_Unwind_VRS_Pop+0x356> 8009b32: f8d4 9038 ldr.w r9, [r4, #56] ; 0x38 8009b36: 2e00 cmp r6, #0 8009b38: 46c8 mov r8, r9 8009b3a: dd2e ble.n 8009b9a <_Unwind_VRS_Pop+0x27e> 8009b3c: 4649 mov r1, r9 8009b3e: f10d 0a08 add.w sl, sp, #8 8009b42: ea4f 0846 mov.w r8, r6, lsl #1 8009b46: eb0a 02c5 add.w r2, sl, r5, lsl #3 8009b4a: f851 6b04 ldr.w r6, [r1], #4 8009b4e: f108 30ff add.w r0, r8, #4294967295 8009b52: f000 0a01 and.w sl, r0, #1 8009b56: f842 6b04 str.w r6, [r2], #4 8009b5a: f1a8 0c02 sub.w ip, r8, #2 8009b5e: b1d0 cbz r0, 8009b96 <_Unwind_VRS_Pop+0x27a> 8009b60: f1ba 0f00 cmp.w sl, #0 8009b64: d008 beq.n 8009b78 <_Unwind_VRS_Pop+0x25c> 8009b66: f851 0b04 ldr.w r0, [r1], #4 8009b6a: f10c 3cff add.w ip, ip, #4294967295 8009b6e: f1bc 3fff cmp.w ip, #4294967295 8009b72: f842 0b04 str.w r0, [r2], #4 8009b76: d00e beq.n 8009b96 <_Unwind_VRS_Pop+0x27a> 8009b78: 460e mov r6, r1 8009b7a: 4610 mov r0, r2 8009b7c: f856 ab04 ldr.w sl, [r6], #4 8009b80: f840 ab04 str.w sl, [r0], #4 8009b84: 6849 ldr r1, [r1, #4] 8009b86: f1ac 0c02 sub.w ip, ip, #2 8009b8a: 6051 str r1, [r2, #4] 8009b8c: 1d31 adds r1, r6, #4 8009b8e: 1d02 adds r2, r0, #4 8009b90: f1bc 3fff cmp.w ip, #4294967295 8009b94: d1f0 bne.n 8009b78 <_Unwind_VRS_Pop+0x25c> 8009b96: eb09 0888 add.w r8, r9, r8, lsl #2 8009b9a: b3a7 cbz r7, 8009c06 <_Unwind_VRS_Pop+0x2ea> 8009b9c: 2d10 cmp r5, #16 8009b9e: bf2c ite cs 8009ba0: 462e movcs r6, r5 8009ba2: 2610 movcc r6, #16 8009ba4: f50d 79d0 add.w r9, sp, #416 ; 0x1a0 8009ba8: 4641 mov r1, r8 8009baa: eb09 0cc6 add.w ip, r9, r6, lsl #3 8009bae: f5ac 72c8 sub.w r2, ip, #400 ; 0x190 8009bb2: ea4f 0947 mov.w r9, r7, lsl #1 8009bb6: f851 6b04 ldr.w r6, [r1], #4 8009bba: f109 30ff add.w r0, r9, #4294967295 8009bbe: f000 0a01 and.w sl, r0, #1 8009bc2: f842 6b04 str.w r6, [r2], #4 8009bc6: f1a9 0c02 sub.w ip, r9, #2 8009bca: b1d0 cbz r0, 8009c02 <_Unwind_VRS_Pop+0x2e6> 8009bcc: f1ba 0f00 cmp.w sl, #0 8009bd0: d008 beq.n 8009be4 <_Unwind_VRS_Pop+0x2c8> 8009bd2: f851 0b04 ldr.w r0, [r1], #4 8009bd6: f10c 3cff add.w ip, ip, #4294967295 8009bda: f1bc 3fff cmp.w ip, #4294967295 8009bde: f842 0b04 str.w r0, [r2], #4 8009be2: d00e beq.n 8009c02 <_Unwind_VRS_Pop+0x2e6> 8009be4: 460e mov r6, r1 8009be6: 4610 mov r0, r2 8009be8: f856 ab04 ldr.w sl, [r6], #4 8009bec: f840 ab04 str.w sl, [r0], #4 8009bf0: 6849 ldr r1, [r1, #4] 8009bf2: f1ac 0c02 sub.w ip, ip, #2 8009bf6: 6051 str r1, [r2, #4] 8009bf8: 1d31 adds r1, r6, #4 8009bfa: 1d02 adds r2, r0, #4 8009bfc: f1bc 3fff cmp.w ip, #4294967295 8009c00: d1f0 bne.n 8009be4 <_Unwind_VRS_Pop+0x2c8> 8009c02: eb08 0889 add.w r8, r8, r9, lsl #2 8009c06: 2b01 cmp r3, #1 8009c08: d02b beq.n 8009c62 <_Unwind_VRS_Pop+0x346> 8009c0a: 2d0f cmp r5, #15 8009c0c: f8c4 8038 str.w r8, [r4, #56] ; 0x38 8009c10: d908 bls.n 8009c24 <_Unwind_VRS_Pop+0x308> 8009c12: b9ff cbnz r7, 8009c54 <_Unwind_VRS_Pop+0x338> 8009c14: 4638 mov r0, r7 8009c16: e695 b.n 8009944 <_Unwind_VRS_Pop+0x28> 8009c18: a802 add r0, sp, #8 8009c1a: 9301 str r3, [sp, #4] 8009c1c: f000 f916 bl 8009e4c <__gnu_Unwind_Save_VFP_D> 8009c20: 9b01 ldr r3, [sp, #4] 8009c22: e783 b.n 8009b2c <_Unwind_VRS_Pop+0x210> 8009c24: a802 add r0, sp, #8 8009c26: f000 f90d bl 8009e44 <__gnu_Unwind_Restore_VFP_D> 8009c2a: e7f2 b.n 8009c12 <_Unwind_VRS_Pop+0x2f6> 8009c2c: 1977 adds r7, r6, r5 8009c2e: 2210 movs r2, #16 8009c30: e750 b.n 8009ad4 <_Unwind_VRS_Pop+0x1b8> 8009c32: 2d0f cmp r5, #15 8009c34: f63f ae85 bhi.w 8009942 <_Unwind_VRS_Pop+0x26> 8009c38: 2f10 cmp r7, #16 8009c3a: d910 bls.n 8009c5e <_Unwind_VRS_Pop+0x342> 8009c3c: 3f10 subs r7, #16 8009c3e: e754 b.n 8009aea <_Unwind_VRS_Pop+0x1ce> 8009c40: f023 0310 bic.w r3, r3, #16 8009c44: 6023 str r3, [r4, #0] 8009c46: f504 700c add.w r0, r4, #560 ; 0x230 8009c4a: 9201 str r2, [sp, #4] 8009c4c: f000 f958 bl 8009f00 <__gnu_Unwind_Save_WMMXC> 8009c50: 9a01 ldr r2, [sp, #4] 8009c52: e682 b.n 800995a <_Unwind_VRS_Pop+0x3e> 8009c54: a824 add r0, sp, #144 ; 0x90 8009c56: f000 f8fd bl 8009e54 <__gnu_Unwind_Restore_VFP_D_16_to_31> 8009c5a: 2000 movs r0, #0 8009c5c: e672 b.n 8009944 <_Unwind_VRS_Pop+0x28> 8009c5e: 2700 movs r7, #0 8009c60: e746 b.n 8009af0 <_Unwind_VRS_Pop+0x1d4> 8009c62: f108 0304 add.w r3, r8, #4 8009c66: a802 add r0, sp, #8 8009c68: 63a3 str r3, [r4, #56] ; 0x38 8009c6a: f000 f8e3 bl 8009e34 <__gnu_Unwind_Restore_VFP> 8009c6e: 2000 movs r0, #0 8009c70: e668 b.n 8009944 <_Unwind_VRS_Pop+0x28> 8009c72: a824 add r0, sp, #144 ; 0x90 8009c74: 9301 str r3, [sp, #4] 8009c76: f1c5 0610 rsb r6, r5, #16 8009c7a: f000 f8ef bl 8009e5c <__gnu_Unwind_Save_VFP_D_16_to_31> 8009c7e: 9b01 ldr r3, [sp, #4] 8009c80: e757 b.n 8009b32 <_Unwind_VRS_Pop+0x216> 8009c82: f023 0708 bic.w r7, r3, #8 8009c86: f504 70d8 add.w r0, r4, #432 ; 0x1b0 8009c8a: 6027 str r7, [r4, #0] 8009c8c: f000 f90c bl 8009ea8 <__gnu_Unwind_Save_WMMXD> 8009c90: e6ec b.n 8009a6c <_Unwind_VRS_Pop+0x150> 8009c92: 4620 mov r0, r4 8009c94: f022 0104 bic.w r1, r2, #4 8009c98: f840 1bd0 str.w r1, [r0], #208 8009c9c: 9301 str r3, [sp, #4] 8009c9e: f000 f8dd bl 8009e5c <__gnu_Unwind_Save_VFP_D_16_to_31> 8009ca2: 9b01 ldr r3, [sp, #4] 8009ca4: e73d b.n 8009b22 <_Unwind_VRS_Pop+0x206> 8009ca6: a802 add r0, sp, #8 8009ca8: 9301 str r3, [sp, #4] 8009caa: f000 f8c7 bl 8009e3c <__gnu_Unwind_Save_VFP> 8009cae: 9b01 ldr r3, [sp, #4] 8009cb0: 2f00 cmp r7, #0 8009cb2: f43f af3e beq.w 8009b32 <_Unwind_VRS_Pop+0x216> 8009cb6: f1c5 0610 rsb r6, r5, #16 8009cba: e73a b.n 8009b32 <_Unwind_VRS_Pop+0x216> 8009cbc: f041 0102 orr.w r1, r1, #2 8009cc0: f840 1b48 str.w r1, [r0], #72 8009cc4: 9301 str r3, [sp, #4] 8009cc6: f000 f8c1 bl 8009e4c <__gnu_Unwind_Save_VFP_D> 8009cca: 9b01 ldr r3, [sp, #4] 8009ccc: e724 b.n 8009b18 <_Unwind_VRS_Pop+0x1fc> 8009cce: bf00 nop 08009cd0 <_Unwind_GetCFA>: 8009cd0: 6c40 ldr r0, [r0, #68] ; 0x44 8009cd2: 4770 bx lr 08009cd4 <__gnu_Unwind_RaiseException>: 8009cd4: b5f0 push {r4, r5, r6, r7, lr} 8009cd6: 460d mov r5, r1 8009cd8: 1d0f adds r7, r1, #4 8009cda: 6bc9 ldr r1, [r1, #60] ; 0x3c 8009cdc: 6429 str r1, [r5, #64] ; 0x40 8009cde: 4604 mov r4, r0 8009ce0: cf0f ldmia r7!, {r0, r1, r2, r3} 8009ce2: f5ad 7d11 sub.w sp, sp, #580 ; 0x244 8009ce6: ae01 add r6, sp, #4 8009ce8: c60f stmia r6!, {r0, r1, r2, r3} 8009cea: cf0f ldmia r7!, {r0, r1, r2, r3} 8009cec: c60f stmia r6!, {r0, r1, r2, r3} 8009cee: cf0f ldmia r7!, {r0, r1, r2, r3} 8009cf0: c60f stmia r6!, {r0, r1, r2, r3} 8009cf2: e897 000f ldmia.w r7, {r0, r1, r2, r3} 8009cf6: e886 000f stmia.w r6, {r0, r1, r2, r3} 8009cfa: f04f 33ff mov.w r3, #4294967295 8009cfe: 9300 str r3, [sp, #0] 8009d00: 9910 ldr r1, [sp, #64] ; 0x40 8009d02: 4620 mov r0, r4 8009d04: f7ff fb22 bl 800934c 8009d08: b958 cbnz r0, 8009d22 <__gnu_Unwind_RaiseException+0x4e> 8009d0a: 6926 ldr r6, [r4, #16] 8009d0c: 4621 mov r1, r4 8009d0e: 466a mov r2, sp 8009d10: 47b0 blx r6 8009d12: 2808 cmp r0, #8 8009d14: 4606 mov r6, r0 8009d16: d0f3 beq.n 8009d00 <__gnu_Unwind_RaiseException+0x2c> 8009d18: 4668 mov r0, sp 8009d1a: f7ff fb7b bl 8009414 8009d1e: 2e06 cmp r6, #6 8009d20: d003 beq.n 8009d2a <__gnu_Unwind_RaiseException+0x56> 8009d22: 2009 movs r0, #9 8009d24: f50d 7d11 add.w sp, sp, #580 ; 0x244 8009d28: bdf0 pop {r4, r5, r6, r7, pc} 8009d2a: 4620 mov r0, r4 8009d2c: 4629 mov r1, r5 8009d2e: f7ff fc07 bl 8009540 8009d32: bf00 nop 08009d34 <__gnu_Unwind_ForcedUnwind>: 8009d34: b410 push {r4} 8009d36: 6bdc ldr r4, [r3, #60] ; 0x3c 8009d38: 60c1 str r1, [r0, #12] 8009d3a: 6182 str r2, [r0, #24] 8009d3c: 4619 mov r1, r3 8009d3e: 2200 movs r2, #0 8009d40: 641c str r4, [r3, #64] ; 0x40 8009d42: bc10 pop {r4} 8009d44: f7ff bb92 b.w 800946c 08009d48 <__gnu_Unwind_Resume>: 8009d48: b538 push {r3, r4, r5, lr} 8009d4a: 6942 ldr r2, [r0, #20] 8009d4c: 68c3 ldr r3, [r0, #12] 8009d4e: 640a str r2, [r1, #64] ; 0x40 8009d50: 4604 mov r4, r0 8009d52: 460d mov r5, r1 8009d54: b123 cbz r3, 8009d60 <__gnu_Unwind_Resume+0x18> 8009d56: 2201 movs r2, #1 8009d58: f7ff fb88 bl 800946c 8009d5c: f000 eda0 blx 800a8a0 8009d60: 6903 ldr r3, [r0, #16] 8009d62: 4621 mov r1, r4 8009d64: 2002 movs r0, #2 8009d66: 462a mov r2, r5 8009d68: 4798 blx r3 8009d6a: 2807 cmp r0, #7 8009d6c: d003 beq.n 8009d76 <__gnu_Unwind_Resume+0x2e> 8009d6e: 2808 cmp r0, #8 8009d70: d004 beq.n 8009d7c <__gnu_Unwind_Resume+0x34> 8009d72: f000 ed96 blx 800a8a0 8009d76: 1d28 adds r0, r5, #4 8009d78: f000 f850 bl 8009e1c <__restore_core_regs> 8009d7c: 4620 mov r0, r4 8009d7e: 4629 mov r1, r5 8009d80: f7ff fbde bl 8009540 08009d84 <__gnu_Unwind_Resume_or_Rethrow>: 8009d84: 68c3 ldr r3, [r0, #12] 8009d86: b123 cbz r3, 8009d92 <__gnu_Unwind_Resume_or_Rethrow+0xe> 8009d88: 6bca ldr r2, [r1, #60] ; 0x3c 8009d8a: 640a str r2, [r1, #64] ; 0x40 8009d8c: 2200 movs r2, #0 8009d8e: f7ff bb6d b.w 800946c 8009d92: e79f b.n 8009cd4 <__gnu_Unwind_RaiseException> 08009d94 <_Unwind_Complete>: 8009d94: 4770 bx lr 8009d96: bf00 nop 08009d98 <_Unwind_DeleteException>: 8009d98: b508 push {r3, lr} 8009d9a: 6883 ldr r3, [r0, #8] 8009d9c: 4601 mov r1, r0 8009d9e: b10b cbz r3, 8009da4 <_Unwind_DeleteException+0xc> 8009da0: 2001 movs r0, #1 8009da2: 4798 blx r3 8009da4: bd08 pop {r3, pc} 8009da6: bf00 nop 08009da8 <__gnu_Unwind_Backtrace>: 8009da8: b5f0 push {r4, r5, r6, r7, lr} 8009daa: 6bd4 ldr r4, [r2, #60] ; 0x3c 8009dac: 1d17 adds r7, r2, #4 8009dae: 6414 str r4, [r2, #64] ; 0x40 8009db0: 4605 mov r5, r0 8009db2: 460c mov r4, r1 8009db4: cf0f ldmia r7!, {r0, r1, r2, r3} 8009db6: f5ad 7d27 sub.w sp, sp, #668 ; 0x29c 8009dba: ae01 add r6, sp, #4 8009dbc: c60f stmia r6!, {r0, r1, r2, r3} 8009dbe: cf0f ldmia r7!, {r0, r1, r2, r3} 8009dc0: c60f stmia r6!, {r0, r1, r2, r3} 8009dc2: cf0f ldmia r7!, {r0, r1, r2, r3} 8009dc4: c60f stmia r6!, {r0, r1, r2, r3} 8009dc6: e897 000f ldmia.w r7, {r0, r1, r2, r3} 8009dca: e886 000f stmia.w r6, {r0, r1, r2, r3} 8009dce: f04f 33ff mov.w r3, #4294967295 8009dd2: 9300 str r3, [sp, #0] 8009dd4: 9910 ldr r1, [sp, #64] ; 0x40 8009dd6: a890 add r0, sp, #576 ; 0x240 8009dd8: f7ff fab8 bl 800934c 8009ddc: 4603 mov r3, r0 8009dde: aa90 add r2, sp, #576 ; 0x240 8009de0: 4668 mov r0, sp 8009de2: 210c movs r1, #12 8009de4: b9bb cbnz r3, 8009e16 <__gnu_Unwind_Backtrace+0x6e> 8009de6: f7ff fbf7 bl 80095d8 <_Unwind_SetGR> 8009dea: 4621 mov r1, r4 8009dec: 4668 mov r0, sp 8009dee: 47a8 blx r5 8009df0: 4606 mov r6, r0 8009df2: a990 add r1, sp, #576 ; 0x240 8009df4: 2008 movs r0, #8 8009df6: 466a mov r2, sp 8009df8: b96e cbnz r6, 8009e16 <__gnu_Unwind_Backtrace+0x6e> 8009dfa: 9b94 ldr r3, [sp, #592] ; 0x250 8009dfc: 4798 blx r3 8009dfe: 2805 cmp r0, #5 8009e00: 4606 mov r6, r0 8009e02: d001 beq.n 8009e08 <__gnu_Unwind_Backtrace+0x60> 8009e04: 2809 cmp r0, #9 8009e06: d1e5 bne.n 8009dd4 <__gnu_Unwind_Backtrace+0x2c> 8009e08: 4668 mov r0, sp 8009e0a: f7ff fb03 bl 8009414 8009e0e: 4630 mov r0, r6 8009e10: f50d 7d27 add.w sp, sp, #668 ; 0x29c 8009e14: bdf0 pop {r4, r5, r6, r7, pc} 8009e16: 2609 movs r6, #9 8009e18: e7f6 b.n 8009e08 <__gnu_Unwind_Backtrace+0x60> 8009e1a: bf00 nop 08009e1c <__restore_core_regs>: 8009e1c: f100 0134 add.w r1, r0, #52 ; 0x34 8009e20: e891 0038 ldmia.w r1, {r3, r4, r5} 8009e24: 469c mov ip, r3 8009e26: 46a6 mov lr, r4 8009e28: f84c 5d04 str.w r5, [ip, #-4]! 8009e2c: e890 0fff ldmia.w r0, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp} 8009e30: 46e5 mov sp, ip 8009e32: bd00 pop {pc} 08009e34 <__gnu_Unwind_Restore_VFP>: 8009e34: ec90 0b21 fldmiax r0, {d0-d15} ;@ Deprecated 8009e38: 4770 bx lr 8009e3a: bf00 nop 08009e3c <__gnu_Unwind_Save_VFP>: 8009e3c: ec80 0b21 fstmiax r0, {d0-d15} ;@ Deprecated 8009e40: 4770 bx lr 8009e42: bf00 nop 08009e44 <__gnu_Unwind_Restore_VFP_D>: 8009e44: ec90 0b20 vldmia r0, {d0-d15} 8009e48: 4770 bx lr 8009e4a: bf00 nop 08009e4c <__gnu_Unwind_Save_VFP_D>: 8009e4c: ec80 0b20 vstmia r0, {d0-d15} 8009e50: 4770 bx lr 8009e52: bf00 nop 08009e54 <__gnu_Unwind_Restore_VFP_D_16_to_31>: 8009e54: ecd0 0b20 vldmia r0, {d16-d31} 8009e58: 4770 bx lr 8009e5a: bf00 nop 08009e5c <__gnu_Unwind_Save_VFP_D_16_to_31>: 8009e5c: ecc0 0b20 vstmia r0, {d16-d31} 8009e60: 4770 bx lr 8009e62: bf00 nop 08009e64 <__gnu_Unwind_Restore_WMMXD>: 8009e64: ecf0 0102 ldfe f0, [r0], #8 8009e68: ecf0 1102 ldfe f1, [r0], #8 8009e6c: ecf0 2102 ldfe f2, [r0], #8 8009e70: ecf0 3102 ldfe f3, [r0], #8 8009e74: ecf0 4102 ldfe f4, [r0], #8 8009e78: ecf0 5102 ldfe f5, [r0], #8 8009e7c: ecf0 6102 ldfe f6, [r0], #8 8009e80: ecf0 7102 ldfe f7, [r0], #8 8009e84: ecf0 8102 ldfp f0, [r0], #8 8009e88: ecf0 9102 ldfp f1, [r0], #8 8009e8c: ecf0 a102 ldfp f2, [r0], #8 8009e90: ecf0 b102 ldfp f3, [r0], #8 8009e94: ecf0 c102 ldfp f4, [r0], #8 8009e98: ecf0 d102 ldfp f5, [r0], #8 8009e9c: ecf0 e102 ldfp f6, [r0], #8 8009ea0: ecf0 f102 ldfp f7, [r0], #8 8009ea4: 4770 bx lr 8009ea6: bf00 nop 08009ea8 <__gnu_Unwind_Save_WMMXD>: 8009ea8: ece0 0102 stfe f0, [r0], #8 8009eac: ece0 1102 stfe f1, [r0], #8 8009eb0: ece0 2102 stfe f2, [r0], #8 8009eb4: ece0 3102 stfe f3, [r0], #8 8009eb8: ece0 4102 stfe f4, [r0], #8 8009ebc: ece0 5102 stfe f5, [r0], #8 8009ec0: ece0 6102 stfe f6, [r0], #8 8009ec4: ece0 7102 stfe f7, [r0], #8 8009ec8: ece0 8102 stfp f0, [r0], #8 8009ecc: ece0 9102 stfp f1, [r0], #8 8009ed0: ece0 a102 stfp f2, [r0], #8 8009ed4: ece0 b102 stfp f3, [r0], #8 8009ed8: ece0 c102 stfp f4, [r0], #8 8009edc: ece0 d102 stfp f5, [r0], #8 8009ee0: ece0 e102 stfp f6, [r0], #8 8009ee4: ece0 f102 stfp f7, [r0], #8 8009ee8: 4770 bx lr 8009eea: bf00 nop 08009eec <__gnu_Unwind_Restore_WMMXC>: 8009eec: fcb0 8101 ldc2 1, cr8, [r0], #4 8009ef0: fcb0 9101 ldc2 1, cr9, [r0], #4 8009ef4: fcb0 a101 ldc2 1, cr10, [r0], #4 8009ef8: fcb0 b101 ldc2 1, cr11, [r0], #4 8009efc: 4770 bx lr 8009efe: bf00 nop 08009f00 <__gnu_Unwind_Save_WMMXC>: 8009f00: fca0 8101 stc2 1, cr8, [r0], #4 8009f04: fca0 9101 stc2 1, cr9, [r0], #4 8009f08: fca0 a101 stc2 1, cr10, [r0], #4 8009f0c: fca0 b101 stc2 1, cr11, [r0], #4 8009f10: 4770 bx lr 8009f12: bf00 nop 08009f14 <_Unwind_RaiseException>: 8009f14: 46ec mov ip, sp 8009f16: b500 push {lr} 8009f18: e92d 5000 stmdb sp!, {ip, lr} 8009f1c: e92d 1fff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip} 8009f20: f04f 0300 mov.w r3, #0 8009f24: e92d 000c stmdb sp!, {r2, r3} 8009f28: a901 add r1, sp, #4 8009f2a: f7ff fed3 bl 8009cd4 <__gnu_Unwind_RaiseException> 8009f2e: f8dd e040 ldr.w lr, [sp, #64] ; 0x40 8009f32: b012 add sp, #72 ; 0x48 8009f34: 4770 bx lr 8009f36: bf00 nop 08009f38 <_Unwind_Resume>: 8009f38: 46ec mov ip, sp 8009f3a: b500 push {lr} 8009f3c: e92d 5000 stmdb sp!, {ip, lr} 8009f40: e92d 1fff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip} 8009f44: f04f 0300 mov.w r3, #0 8009f48: e92d 000c stmdb sp!, {r2, r3} 8009f4c: a901 add r1, sp, #4 8009f4e: f7ff fefb bl 8009d48 <__gnu_Unwind_Resume> 8009f52: f8dd e040 ldr.w lr, [sp, #64] ; 0x40 8009f56: b012 add sp, #72 ; 0x48 8009f58: 4770 bx lr 8009f5a: bf00 nop 08009f5c <_Unwind_Resume_or_Rethrow>: 8009f5c: 46ec mov ip, sp 8009f5e: b500 push {lr} 8009f60: e92d 5000 stmdb sp!, {ip, lr} 8009f64: e92d 1fff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip} 8009f68: f04f 0300 mov.w r3, #0 8009f6c: e92d 000c stmdb sp!, {r2, r3} 8009f70: a901 add r1, sp, #4 8009f72: f7ff ff07 bl 8009d84 <__gnu_Unwind_Resume_or_Rethrow> 8009f76: f8dd e040 ldr.w lr, [sp, #64] ; 0x40 8009f7a: b012 add sp, #72 ; 0x48 8009f7c: 4770 bx lr 8009f7e: bf00 nop 08009f80 <_Unwind_ForcedUnwind>: 8009f80: 46ec mov ip, sp 8009f82: b500 push {lr} 8009f84: e92d 5000 stmdb sp!, {ip, lr} 8009f88: e92d 1fff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip} 8009f8c: f04f 0300 mov.w r3, #0 8009f90: e92d 000c stmdb sp!, {r2, r3} 8009f94: ab01 add r3, sp, #4 8009f96: f7ff fecd bl 8009d34 <__gnu_Unwind_ForcedUnwind> 8009f9a: f8dd e040 ldr.w lr, [sp, #64] ; 0x40 8009f9e: b012 add sp, #72 ; 0x48 8009fa0: 4770 bx lr 8009fa2: bf00 nop 08009fa4 <_Unwind_Backtrace>: 8009fa4: 46ec mov ip, sp 8009fa6: b500 push {lr} 8009fa8: e92d 5000 stmdb sp!, {ip, lr} 8009fac: e92d 1fff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, fp, ip} 8009fb0: f04f 0300 mov.w r3, #0 8009fb4: e92d 000c stmdb sp!, {r2, r3} 8009fb8: aa01 add r2, sp, #4 8009fba: f7ff fef5 bl 8009da8 <__gnu_Unwind_Backtrace> 8009fbe: f8dd e040 ldr.w lr, [sp, #64] ; 0x40 8009fc2: b012 add sp, #72 ; 0x48 8009fc4: 4770 bx lr 8009fc6: bf00 nop 08009fc8 : 8009fc8: 7a02 ldrb r2, [r0, #8] 8009fca: 4603 mov r3, r0 8009fcc: b91a cbnz r2, 8009fd6 8009fce: 7a42 ldrb r2, [r0, #9] 8009fd0: b942 cbnz r2, 8009fe4 8009fd2: 20b0 movs r0, #176 ; 0xb0 8009fd4: 4770 bx lr 8009fd6: 6800 ldr r0, [r0, #0] 8009fd8: 3a01 subs r2, #1 8009fda: 0201 lsls r1, r0, #8 8009fdc: 721a strb r2, [r3, #8] 8009fde: 0e00 lsrs r0, r0, #24 8009fe0: 6019 str r1, [r3, #0] 8009fe2: 4770 bx lr 8009fe4: 6841 ldr r1, [r0, #4] 8009fe6: 1e50 subs r0, r2, #1 8009fe8: 7258 strb r0, [r3, #9] 8009fea: f851 0b04 ldr.w r0, [r1], #4 8009fee: 2203 movs r2, #3 8009ff0: 6059 str r1, [r3, #4] 8009ff2: 0201 lsls r1, r0, #8 8009ff4: 721a strb r2, [r3, #8] 8009ff6: 0e00 lsrs r0, r0, #24 8009ff8: 6019 str r1, [r3, #0] 8009ffa: 4770 bx lr 08009ffc <_Unwind_GetGR.constprop.0>: 8009ffc: b510 push {r4, lr} 8009ffe: 2100 movs r1, #0 800a000: b084 sub sp, #16 800a002: 220c movs r2, #12 800a004: eb0d 0402 add.w r4, sp, r2 800a008: 460b mov r3, r1 800a00a: 9400 str r4, [sp, #0] 800a00c: f7ff fab0 bl 8009570 <_Unwind_VRS_Get> 800a010: 9803 ldr r0, [sp, #12] 800a012: b004 add sp, #16 800a014: bd10 pop {r4, pc} 800a016: bf00 nop 0800a018 : 800a018: e7f0 b.n 8009ffc <_Unwind_GetGR.constprop.0> 800a01a: bf00 nop 0800a01c <__gnu_unwind_execute>: 800a01c: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} 800a020: 4606 mov r6, r0 800a022: b085 sub sp, #20 800a024: 460d mov r5, r1 800a026: f04f 0900 mov.w r9, #0 800a02a: f44f 677f mov.w r7, #4080 ; 0xff0 800a02e: 4628 mov r0, r5 800a030: f7ff ffca bl 8009fc8 800a034: 28b0 cmp r0, #176 ; 0xb0 800a036: 4604 mov r4, r0 800a038: f000 80b0 beq.w 800a19c <__gnu_unwind_execute+0x180> 800a03c: f010 0180 ands.w r1, r0, #128 ; 0x80 800a040: d020 beq.n 800a084 <__gnu_unwind_execute+0x68> 800a042: f000 03f0 and.w r3, r0, #240 ; 0xf0 800a046: 2b80 cmp r3, #128 ; 0x80 800a048: d074 beq.n 800a134 <__gnu_unwind_execute+0x118> 800a04a: 2b90 cmp r3, #144 ; 0x90 800a04c: d037 beq.n 800a0be <__gnu_unwind_execute+0xa2> 800a04e: 2ba0 cmp r3, #160 ; 0xa0 800a050: d045 beq.n 800a0de <__gnu_unwind_execute+0xc2> 800a052: 2bb0 cmp r3, #176 ; 0xb0 800a054: d056 beq.n 800a104 <__gnu_unwind_execute+0xe8> 800a056: 2bc0 cmp r3, #192 ; 0xc0 800a058: f000 8085 beq.w 800a166 <__gnu_unwind_execute+0x14a> 800a05c: f000 00f8 and.w r0, r0, #248 ; 0xf8 800a060: 28d0 cmp r0, #208 ; 0xd0 800a062: d10b bne.n 800a07c <__gnu_unwind_execute+0x60> 800a064: f004 0207 and.w r2, r4, #7 800a068: 1c51 adds r1, r2, #1 800a06a: f441 2200 orr.w r2, r1, #524288 ; 0x80000 800a06e: 4630 mov r0, r6 800a070: 2101 movs r1, #1 800a072: 2305 movs r3, #5 800a074: f7ff fc52 bl 800991c <_Unwind_VRS_Pop> 800a078: 2800 cmp r0, #0 800a07a: d0d8 beq.n 800a02e <__gnu_unwind_execute+0x12> 800a07c: 2009 movs r0, #9 800a07e: b005 add sp, #20 800a080: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} 800a084: ea4f 0280 mov.w r2, r0, lsl #2 800a088: a803 add r0, sp, #12 800a08a: fa5f f882 uxtb.w r8, r2 800a08e: 9000 str r0, [sp, #0] 800a090: 220d movs r2, #13 800a092: 460b mov r3, r1 800a094: 4630 mov r0, r6 800a096: f7ff fa6b bl 8009570 <_Unwind_VRS_Get> 800a09a: 9b03 ldr r3, [sp, #12] 800a09c: 0660 lsls r0, r4, #25 800a09e: f108 0804 add.w r8, r8, #4 800a0a2: bf4c ite mi 800a0a4: ebc8 0303 rsbmi r3, r8, r3 800a0a8: 4443 addpl r3, r8 800a0aa: ac03 add r4, sp, #12 800a0ac: 9303 str r3, [sp, #12] 800a0ae: 9400 str r4, [sp, #0] 800a0b0: 2100 movs r1, #0 800a0b2: 4630 mov r0, r6 800a0b4: 220d movs r2, #13 800a0b6: 460b mov r3, r1 800a0b8: f7ff fa7a bl 80095b0 <_Unwind_VRS_Set> 800a0bc: e7b7 b.n 800a02e <__gnu_unwind_execute+0x12> 800a0be: f000 020f and.w r2, r0, #15 800a0c2: 2a0d cmp r2, #13 800a0c4: d0da beq.n 800a07c <__gnu_unwind_execute+0x60> 800a0c6: 2a0f cmp r2, #15 800a0c8: d0d8 beq.n 800a07c <__gnu_unwind_execute+0x60> 800a0ca: 2100 movs r1, #0 800a0cc: ac03 add r4, sp, #12 800a0ce: 9400 str r4, [sp, #0] 800a0d0: 4630 mov r0, r6 800a0d2: 460b mov r3, r1 800a0d4: ac03 add r4, sp, #12 800a0d6: f7ff fa4b bl 8009570 <_Unwind_VRS_Get> 800a0da: 9400 str r4, [sp, #0] 800a0dc: e7e8 b.n 800a0b0 <__gnu_unwind_execute+0x94> 800a0de: 43c2 mvns r2, r0 800a0e0: f002 0c07 and.w ip, r2, #7 800a0e4: fa47 f00c asr.w r0, r7, ip 800a0e8: 0721 lsls r1, r4, #28 800a0ea: f400 627f and.w r2, r0, #4080 ; 0xff0 800a0ee: bf48 it mi 800a0f0: f442 4280 orrmi.w r2, r2, #16384 ; 0x4000 800a0f4: 2100 movs r1, #0 800a0f6: 4630 mov r0, r6 800a0f8: 460b mov r3, r1 800a0fa: f7ff fc0f bl 800991c <_Unwind_VRS_Pop> 800a0fe: 2800 cmp r0, #0 800a100: d1bc bne.n 800a07c <__gnu_unwind_execute+0x60> 800a102: e794 b.n 800a02e <__gnu_unwind_execute+0x12> 800a104: 28b1 cmp r0, #177 ; 0xb1 800a106: d05d beq.n 800a1c4 <__gnu_unwind_execute+0x1a8> 800a108: 28b2 cmp r0, #178 ; 0xb2 800a10a: d06e beq.n 800a1ea <__gnu_unwind_execute+0x1ce> 800a10c: 28b3 cmp r0, #179 ; 0xb3 800a10e: f000 8095 beq.w 800a23c <__gnu_unwind_execute+0x220> 800a112: f000 02fc and.w r2, r0, #252 ; 0xfc 800a116: 2ab4 cmp r2, #180 ; 0xb4 800a118: d046 beq.n 800a1a8 <__gnu_unwind_execute+0x18c> 800a11a: f000 0207 and.w r2, r0, #7 800a11e: 1c53 adds r3, r2, #1 800a120: f443 2200 orr.w r2, r3, #524288 ; 0x80000 800a124: 2101 movs r1, #1 800a126: 4630 mov r0, r6 800a128: 460b mov r3, r1 800a12a: f7ff fbf7 bl 800991c <_Unwind_VRS_Pop> 800a12e: 2800 cmp r0, #0 800a130: d1a4 bne.n 800a07c <__gnu_unwind_execute+0x60> 800a132: e77c b.n 800a02e <__gnu_unwind_execute+0x12> 800a134: 4628 mov r0, r5 800a136: f7ff ff47 bl 8009fc8 800a13a: 0221 lsls r1, r4, #8 800a13c: ea40 0401 orr.w r4, r0, r1 800a140: f5b4 4f00 cmp.w r4, #32768 ; 0x8000 800a144: d09a beq.n 800a07c <__gnu_unwind_execute+0x60> 800a146: 0523 lsls r3, r4, #20 800a148: 2100 movs r1, #0 800a14a: 0c1a lsrs r2, r3, #16 800a14c: 4630 mov r0, r6 800a14e: 460b mov r3, r1 800a150: 0124 lsls r4, r4, #4 800a152: f7ff fbe3 bl 800991c <_Unwind_VRS_Pop> 800a156: 2800 cmp r0, #0 800a158: d190 bne.n 800a07c <__gnu_unwind_execute+0x60> 800a15a: f414 4f00 tst.w r4, #32768 ; 0x8000 800a15e: bf18 it ne 800a160: f04f 0901 movne.w r9, #1 800a164: e763 b.n 800a02e <__gnu_unwind_execute+0x12> 800a166: 28c6 cmp r0, #198 ; 0xc6 800a168: d073 beq.n 800a252 <__gnu_unwind_execute+0x236> 800a16a: 28c7 cmp r0, #199 ; 0xc7 800a16c: f000 8084 beq.w 800a278 <__gnu_unwind_execute+0x25c> 800a170: f000 02f8 and.w r2, r0, #248 ; 0xf8 800a174: 2ac0 cmp r2, #192 ; 0xc0 800a176: f000 8092 beq.w 800a29e <__gnu_unwind_execute+0x282> 800a17a: 28c8 cmp r0, #200 ; 0xc8 800a17c: f000 80a6 beq.w 800a2cc <__gnu_unwind_execute+0x2b0> 800a180: 28c9 cmp r0, #201 ; 0xc9 800a182: f47f af7b bne.w 800a07c <__gnu_unwind_execute+0x60> 800a186: 4628 mov r0, r5 800a188: f7ff ff1e bl 8009fc8 800a18c: f000 030f and.w r3, r0, #15 800a190: f000 01f0 and.w r1, r0, #240 ; 0xf0 800a194: 1c5a adds r2, r3, #1 800a196: ea42 3201 orr.w r2, r2, r1, lsl #12 800a19a: e768 b.n 800a06e <__gnu_unwind_execute+0x52> 800a19c: f1b9 0f00 cmp.w r9, #0 800a1a0: f000 8083 beq.w 800a2aa <__gnu_unwind_execute+0x28e> 800a1a4: 2000 movs r0, #0 800a1a6: e76a b.n 800a07e <__gnu_unwind_execute+0x62> 800a1a8: f000 0103 and.w r1, r0, #3 800a1ac: 1c48 adds r0, r1, #1 800a1ae: 2102 movs r1, #2 800a1b0: f440 2280 orr.w r2, r0, #262144 ; 0x40000 800a1b4: 460b mov r3, r1 800a1b6: 4630 mov r0, r6 800a1b8: f7ff fbb0 bl 800991c <_Unwind_VRS_Pop> 800a1bc: 2800 cmp r0, #0 800a1be: f47f af5d bne.w 800a07c <__gnu_unwind_execute+0x60> 800a1c2: e734 b.n 800a02e <__gnu_unwind_execute+0x12> 800a1c4: 4628 mov r0, r5 800a1c6: f7ff feff bl 8009fc8 800a1ca: 4602 mov r2, r0 800a1cc: 2800 cmp r0, #0 800a1ce: f43f af55 beq.w 800a07c <__gnu_unwind_execute+0x60> 800a1d2: f010 01f0 ands.w r1, r0, #240 ; 0xf0 800a1d6: f47f af51 bne.w 800a07c <__gnu_unwind_execute+0x60> 800a1da: 4630 mov r0, r6 800a1dc: 460b mov r3, r1 800a1de: f7ff fb9d bl 800991c <_Unwind_VRS_Pop> 800a1e2: 2800 cmp r0, #0 800a1e4: f47f af4a bne.w 800a07c <__gnu_unwind_execute+0x60> 800a1e8: e721 b.n 800a02e <__gnu_unwind_execute+0x12> 800a1ea: 2100 movs r1, #0 800a1ec: 220d movs r2, #13 800a1ee: 460b mov r3, r1 800a1f0: ac03 add r4, sp, #12 800a1f2: 4630 mov r0, r6 800a1f4: 9400 str r4, [sp, #0] 800a1f6: f7ff f9bb bl 8009570 <_Unwind_VRS_Get> 800a1fa: 4628 mov r0, r5 800a1fc: f7ff fee4 bl 8009fc8 800a200: 2402 movs r4, #2 800a202: 0602 lsls r2, r0, #24 800a204: d50d bpl.n 800a222 <__gnu_unwind_execute+0x206> 800a206: 9b03 ldr r3, [sp, #12] 800a208: f000 007f and.w r0, r0, #127 ; 0x7f 800a20c: fa00 fe04 lsl.w lr, r0, r4 800a210: eb03 010e add.w r1, r3, lr 800a214: 4628 mov r0, r5 800a216: 9103 str r1, [sp, #12] 800a218: f7ff fed6 bl 8009fc8 800a21c: 3407 adds r4, #7 800a21e: 0603 lsls r3, r0, #24 800a220: d4f1 bmi.n 800a206 <__gnu_unwind_execute+0x1ea> 800a222: 9b03 ldr r3, [sp, #12] 800a224: f000 017f and.w r1, r0, #127 ; 0x7f 800a228: aa03 add r2, sp, #12 800a22a: f503 7c01 add.w ip, r3, #516 ; 0x204 800a22e: fa01 f404 lsl.w r4, r1, r4 800a232: 9200 str r2, [sp, #0] 800a234: eb0c 0204 add.w r2, ip, r4 800a238: 9203 str r2, [sp, #12] 800a23a: e739 b.n 800a0b0 <__gnu_unwind_execute+0x94> 800a23c: 4628 mov r0, r5 800a23e: f7ff fec3 bl 8009fc8 800a242: f000 030f and.w r3, r0, #15 800a246: 1c59 adds r1, r3, #1 800a248: f000 00f0 and.w r0, r0, #240 ; 0xf0 800a24c: ea41 3200 orr.w r2, r1, r0, lsl #12 800a250: e768 b.n 800a124 <__gnu_unwind_execute+0x108> 800a252: 4628 mov r0, r5 800a254: f7ff feb8 bl 8009fc8 800a258: f000 030f and.w r3, r0, #15 800a25c: 1c59 adds r1, r3, #1 800a25e: f000 00f0 and.w r0, r0, #240 ; 0xf0 800a262: ea41 3200 orr.w r2, r1, r0, lsl #12 800a266: 2103 movs r1, #3 800a268: 4630 mov r0, r6 800a26a: 460b mov r3, r1 800a26c: f7ff fb56 bl 800991c <_Unwind_VRS_Pop> 800a270: 2800 cmp r0, #0 800a272: f47f af03 bne.w 800a07c <__gnu_unwind_execute+0x60> 800a276: e6da b.n 800a02e <__gnu_unwind_execute+0x12> 800a278: 4628 mov r0, r5 800a27a: f7ff fea5 bl 8009fc8 800a27e: 4602 mov r2, r0 800a280: 2800 cmp r0, #0 800a282: f43f aefb beq.w 800a07c <__gnu_unwind_execute+0x60> 800a286: f010 03f0 ands.w r3, r0, #240 ; 0xf0 800a28a: f47f aef7 bne.w 800a07c <__gnu_unwind_execute+0x60> 800a28e: 4630 mov r0, r6 800a290: 2104 movs r1, #4 800a292: f7ff fb43 bl 800991c <_Unwind_VRS_Pop> 800a296: 2800 cmp r0, #0 800a298: f47f aef0 bne.w 800a07c <__gnu_unwind_execute+0x60> 800a29c: e6c7 b.n 800a02e <__gnu_unwind_execute+0x12> 800a29e: f000 010f and.w r1, r0, #15 800a2a2: 1c48 adds r0, r1, #1 800a2a4: f440 2220 orr.w r2, r0, #655360 ; 0xa0000 800a2a8: e7dd b.n 800a266 <__gnu_unwind_execute+0x24a> 800a2aa: ac03 add r4, sp, #12 800a2ac: 4649 mov r1, r9 800a2ae: 220e movs r2, #14 800a2b0: 464b mov r3, r9 800a2b2: 4630 mov r0, r6 800a2b4: 9400 str r4, [sp, #0] 800a2b6: f7ff f95b bl 8009570 <_Unwind_VRS_Get> 800a2ba: 4630 mov r0, r6 800a2bc: 4649 mov r1, r9 800a2be: 220f movs r2, #15 800a2c0: 464b mov r3, r9 800a2c2: 9400 str r4, [sp, #0] 800a2c4: f7ff f974 bl 80095b0 <_Unwind_VRS_Set> 800a2c8: 4648 mov r0, r9 800a2ca: e6d8 b.n 800a07e <__gnu_unwind_execute+0x62> 800a2cc: 4628 mov r0, r5 800a2ce: f7ff fe7b bl 8009fc8 800a2d2: f000 02f0 and.w r2, r0, #240 ; 0xf0 800a2d6: f000 000f and.w r0, r0, #15 800a2da: 3210 adds r2, #16 800a2dc: 1c43 adds r3, r0, #1 800a2de: ea43 3202 orr.w r2, r3, r2, lsl #12 800a2e2: e6c4 b.n 800a06e <__gnu_unwind_execute+0x52> 0800a2e4 <__gnu_unwind_frame>: 800a2e4: b510 push {r4, lr} 800a2e6: 6cc2 ldr r2, [r0, #76] ; 0x4c 800a2e8: b084 sub sp, #16 800a2ea: 2003 movs r0, #3 800a2ec: 6854 ldr r4, [r2, #4] 800a2ee: f88d 000c strb.w r0, [sp, #12] 800a2f2: 79d3 ldrb r3, [r2, #7] 800a2f4: 0224 lsls r4, r4, #8 800a2f6: 3208 adds r2, #8 800a2f8: 4608 mov r0, r1 800a2fa: a901 add r1, sp, #4 800a2fc: 9401 str r4, [sp, #4] 800a2fe: 9202 str r2, [sp, #8] 800a300: f88d 300d strb.w r3, [sp, #13] 800a304: f7ff fe8a bl 800a01c <__gnu_unwind_execute> 800a308: b004 add sp, #16 800a30a: bd10 pop {r4, pc} 0800a30c <_Unwind_GetRegionStart>: 800a30c: b508 push {r3, lr} 800a30e: f7ff fe83 bl 800a018 800a312: 6c80 ldr r0, [r0, #72] ; 0x48 800a314: bd08 pop {r3, pc} 800a316: bf00 nop 0800a318 <_Unwind_GetLanguageSpecificData>: 800a318: b508 push {r3, lr} 800a31a: f7ff fe7d bl 800a018 800a31e: 6cc1 ldr r1, [r0, #76] ; 0x4c 800a320: 79c8 ldrb r0, [r1, #7] 800a322: eb01 0380 add.w r3, r1, r0, lsl #2 800a326: f103 0008 add.w r0, r3, #8 800a32a: bd08 pop {r3, pc} 0800a32c <_Unwind_GetDataRelBase>: 800a32c: b508 push {r3, lr} 800a32e: f000 eab8 blx 800a8a0 800a332: bf00 nop 0800a334 <_Unwind_GetTextRelBase>: 800a334: b508 push {r3, lr} 800a336: f000 eab4 blx 800a8a0 800a33a: bf00 nop 0800a33c <__aeabi_idiv0>: 800a33c: 4770 bx lr 800a33e: bf00 nop 0800a340 <__divdi3>: 800a340: e92d 07f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl} 800a344: 2900 cmp r1, #0 800a346: 461d mov r5, r3 800a348: f2c0 809d blt.w 800a486 <__divdi3+0x146> 800a34c: 2400 movs r4, #0 800a34e: 2d00 cmp r5, #0 800a350: f2c0 8094 blt.w 800a47c <__divdi3+0x13c> 800a354: 4607 mov r7, r0 800a356: 460d mov r5, r1 800a358: 4616 mov r6, r2 800a35a: 469c mov ip, r3 800a35c: 2b00 cmp r3, #0 800a35e: d13d bne.n 800a3dc <__divdi3+0x9c> 800a360: 428a cmp r2, r1 800a362: d953 bls.n 800a40c <__divdi3+0xcc> 800a364: fab2 f382 clz r3, r2 800a368: b143 cbz r3, 800a37c <__divdi3+0x3c> 800a36a: f1c3 0620 rsb r6, r3, #32 800a36e: fa20 f506 lsr.w r5, r0, r6 800a372: fa01 f103 lsl.w r1, r1, r3 800a376: 409a lsls r2, r3 800a378: 4329 orrs r1, r5 800a37a: 4098 lsls r0, r3 800a37c: 0c13 lsrs r3, r2, #16 800a37e: fbb1 f6f3 udiv r6, r1, r3 800a382: b297 uxth r7, r2 800a384: fb03 1116 mls r1, r3, r6, r1 800a388: ea4f 4c10 mov.w ip, r0, lsr #16 800a38c: fb07 f506 mul.w r5, r7, r6 800a390: ea4c 4101 orr.w r1, ip, r1, lsl #16 800a394: 428d cmp r5, r1 800a396: d909 bls.n 800a3ac <__divdi3+0x6c> 800a398: 1889 adds r1, r1, r2 800a39a: f106 3cff add.w ip, r6, #4294967295 800a39e: f080 8114 bcs.w 800a5ca <__divdi3+0x28a> 800a3a2: 428d cmp r5, r1 800a3a4: f240 8111 bls.w 800a5ca <__divdi3+0x28a> 800a3a8: 3e02 subs r6, #2 800a3aa: 1889 adds r1, r1, r2 800a3ac: 1b49 subs r1, r1, r5 800a3ae: fbb1 f5f3 udiv r5, r1, r3 800a3b2: fb03 1315 mls r3, r3, r5, r1 800a3b6: b280 uxth r0, r0 800a3b8: fb07 f705 mul.w r7, r7, r5 800a3bc: ea40 4303 orr.w r3, r0, r3, lsl #16 800a3c0: 429f cmp r7, r3 800a3c2: d907 bls.n 800a3d4 <__divdi3+0x94> 800a3c4: 1e69 subs r1, r5, #1 800a3c6: 189b adds r3, r3, r2 800a3c8: f080 8105 bcs.w 800a5d6 <__divdi3+0x296> 800a3cc: 429f cmp r7, r3 800a3ce: f240 8102 bls.w 800a5d6 <__divdi3+0x296> 800a3d2: 3d02 subs r5, #2 800a3d4: ea45 4206 orr.w r2, r5, r6, lsl #16 800a3d8: 2300 movs r3, #0 800a3da: e003 b.n 800a3e4 <__divdi3+0xa4> 800a3dc: 428b cmp r3, r1 800a3de: d90a bls.n 800a3f6 <__divdi3+0xb6> 800a3e0: 2300 movs r3, #0 800a3e2: 461a mov r2, r3 800a3e4: 4610 mov r0, r2 800a3e6: 4619 mov r1, r3 800a3e8: b114 cbz r4, 800a3f0 <__divdi3+0xb0> 800a3ea: 4240 negs r0, r0 800a3ec: eb61 0141 sbc.w r1, r1, r1, lsl #1 800a3f0: e8bd 07f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl} 800a3f4: 4770 bx lr 800a3f6: fab3 f383 clz r3, r3 800a3fa: 2b00 cmp r3, #0 800a3fc: f040 8087 bne.w 800a50e <__divdi3+0x1ce> 800a400: 458c cmp ip, r1 800a402: d301 bcc.n 800a408 <__divdi3+0xc8> 800a404: 4282 cmp r2, r0 800a406: d8ec bhi.n 800a3e2 <__divdi3+0xa2> 800a408: 2201 movs r2, #1 800a40a: e7eb b.n 800a3e4 <__divdi3+0xa4> 800a40c: b912 cbnz r2, 800a414 <__divdi3+0xd4> 800a40e: 2701 movs r7, #1 800a410: fbb7 f2f2 udiv r2, r7, r2 800a414: fab2 f682 clz r6, r2 800a418: 2e00 cmp r6, #0 800a41a: d13a bne.n 800a492 <__divdi3+0x152> 800a41c: 1a89 subs r1, r1, r2 800a41e: 0c15 lsrs r5, r2, #16 800a420: fa1f fc82 uxth.w ip, r2 800a424: 2301 movs r3, #1 800a426: fbb1 f7f5 udiv r7, r1, r5 800a42a: fb05 1117 mls r1, r5, r7, r1 800a42e: ea4f 4810 mov.w r8, r0, lsr #16 800a432: fb0c f607 mul.w r6, ip, r7 800a436: ea48 4101 orr.w r1, r8, r1, lsl #16 800a43a: 428e cmp r6, r1 800a43c: d907 bls.n 800a44e <__divdi3+0x10e> 800a43e: 1889 adds r1, r1, r2 800a440: f107 38ff add.w r8, r7, #4294967295 800a444: d202 bcs.n 800a44c <__divdi3+0x10c> 800a446: 428e cmp r6, r1 800a448: f200 80da bhi.w 800a600 <__divdi3+0x2c0> 800a44c: 4647 mov r7, r8 800a44e: 1b89 subs r1, r1, r6 800a450: fbb1 f6f5 udiv r6, r1, r5 800a454: fb05 1116 mls r1, r5, r6, r1 800a458: b280 uxth r0, r0 800a45a: fb0c fc06 mul.w ip, ip, r6 800a45e: ea40 4001 orr.w r0, r0, r1, lsl #16 800a462: 4584 cmp ip, r0 800a464: d907 bls.n 800a476 <__divdi3+0x136> 800a466: 1e71 subs r1, r6, #1 800a468: 1882 adds r2, r0, r2 800a46a: f080 80b0 bcs.w 800a5ce <__divdi3+0x28e> 800a46e: 4594 cmp ip, r2 800a470: f240 80ad bls.w 800a5ce <__divdi3+0x28e> 800a474: 3e02 subs r6, #2 800a476: ea46 4207 orr.w r2, r6, r7, lsl #16 800a47a: e7b3 b.n 800a3e4 <__divdi3+0xa4> 800a47c: 43e4 mvns r4, r4 800a47e: 4252 negs r2, r2 800a480: eb63 0343 sbc.w r3, r3, r3, lsl #1 800a484: e766 b.n 800a354 <__divdi3+0x14> 800a486: 4240 negs r0, r0 800a488: eb61 0141 sbc.w r1, r1, r1, lsl #1 800a48c: f04f 34ff mov.w r4, #4294967295 800a490: e75d b.n 800a34e <__divdi3+0xe> 800a492: 40b2 lsls r2, r6 800a494: f1c6 0520 rsb r5, r6, #32 800a498: fa21 f305 lsr.w r3, r1, r5 800a49c: fa20 f705 lsr.w r7, r0, r5 800a4a0: fa01 f906 lsl.w r9, r1, r6 800a4a4: 0c15 lsrs r5, r2, #16 800a4a6: fbb3 f8f5 udiv r8, r3, r5 800a4aa: ea47 0909 orr.w r9, r7, r9 800a4ae: fa1f fc82 uxth.w ip, r2 800a4b2: fb05 3718 mls r7, r5, r8, r3 800a4b6: ea4f 4119 mov.w r1, r9, lsr #16 800a4ba: fb0c f308 mul.w r3, ip, r8 800a4be: ea41 4707 orr.w r7, r1, r7, lsl #16 800a4c2: 40b0 lsls r0, r6 800a4c4: 42bb cmp r3, r7 800a4c6: d90a bls.n 800a4de <__divdi3+0x19e> 800a4c8: 18bf adds r7, r7, r2 800a4ca: f108 31ff add.w r1, r8, #4294967295 800a4ce: f080 8095 bcs.w 800a5fc <__divdi3+0x2bc> 800a4d2: 42bb cmp r3, r7 800a4d4: f240 8092 bls.w 800a5fc <__divdi3+0x2bc> 800a4d8: f1a8 0802 sub.w r8, r8, #2 800a4dc: 18bf adds r7, r7, r2 800a4de: 1afe subs r6, r7, r3 800a4e0: fbb6 f3f5 udiv r3, r6, r5 800a4e4: fb05 6113 mls r1, r5, r3, r6 800a4e8: fa1f f989 uxth.w r9, r9 800a4ec: fb0c f603 mul.w r6, ip, r3 800a4f0: ea49 4101 orr.w r1, r9, r1, lsl #16 800a4f4: 428e cmp r6, r1 800a4f6: d906 bls.n 800a506 <__divdi3+0x1c6> 800a4f8: 1e5f subs r7, r3, #1 800a4fa: 1889 adds r1, r1, r2 800a4fc: d278 bcs.n 800a5f0 <__divdi3+0x2b0> 800a4fe: 428e cmp r6, r1 800a500: d976 bls.n 800a5f0 <__divdi3+0x2b0> 800a502: 3b02 subs r3, #2 800a504: 1889 adds r1, r1, r2 800a506: 1b89 subs r1, r1, r6 800a508: ea43 4308 orr.w r3, r3, r8, lsl #16 800a50c: e78b b.n 800a426 <__divdi3+0xe6> 800a50e: f1c3 0720 rsb r7, r3, #32 800a512: fa26 f807 lsr.w r8, r6, r7 800a516: fa0c f203 lsl.w r2, ip, r3 800a51a: ea48 0c02 orr.w ip, r8, r2 800a51e: fa21 f107 lsr.w r1, r1, r7 800a522: fa05 fa03 lsl.w sl, r5, r3 800a526: ea4f 481c mov.w r8, ip, lsr #16 800a52a: fa20 f507 lsr.w r5, r0, r7 800a52e: fbb1 f9f8 udiv r9, r1, r8 800a532: ea45 050a orr.w r5, r5, sl 800a536: fb08 1719 mls r7, r8, r9, r1 800a53a: 0c2a lsrs r2, r5, #16 800a53c: fa1f fa8c uxth.w sl, ip 800a540: fb0a f109 mul.w r1, sl, r9 800a544: ea42 4707 orr.w r7, r2, r7, lsl #16 800a548: 42b9 cmp r1, r7 800a54a: fa06 f603 lsl.w r6, r6, r3 800a54e: d909 bls.n 800a564 <__divdi3+0x224> 800a550: eb17 070c adds.w r7, r7, ip 800a554: f109 32ff add.w r2, r9, #4294967295 800a558: d24e bcs.n 800a5f8 <__divdi3+0x2b8> 800a55a: 42b9 cmp r1, r7 800a55c: d94c bls.n 800a5f8 <__divdi3+0x2b8> 800a55e: f1a9 0902 sub.w r9, r9, #2 800a562: 4467 add r7, ip 800a564: 1a7f subs r7, r7, r1 800a566: fbb7 f2f8 udiv r2, r7, r8 800a56a: fb08 7112 mls r1, r8, r2, r7 800a56e: b2ad uxth r5, r5 800a570: fb0a fa02 mul.w sl, sl, r2 800a574: ea45 4101 orr.w r1, r5, r1, lsl #16 800a578: 458a cmp sl, r1 800a57a: d907 bls.n 800a58c <__divdi3+0x24c> 800a57c: 1e55 subs r5, r2, #1 800a57e: eb11 010c adds.w r1, r1, ip 800a582: d237 bcs.n 800a5f4 <__divdi3+0x2b4> 800a584: 458a cmp sl, r1 800a586: d935 bls.n 800a5f4 <__divdi3+0x2b4> 800a588: 3a02 subs r2, #2 800a58a: 4461 add r1, ip 800a58c: ea42 4209 orr.w r2, r2, r9, lsl #16 800a590: fa1f f886 uxth.w r8, r6 800a594: ea4f 4c12 mov.w ip, r2, lsr #16 800a598: 0c36 lsrs r6, r6, #16 800a59a: fb08 f70c mul.w r7, r8, ip 800a59e: b295 uxth r5, r2 800a5a0: fb08 f805 mul.w r8, r8, r5 800a5a4: fb06 7505 mla r5, r6, r5, r7 800a5a8: eb05 4518 add.w r5, r5, r8, lsr #16 800a5ac: fb06 fc0c mul.w ip, r6, ip 800a5b0: 42af cmp r7, r5 800a5b2: bf88 it hi 800a5b4: f50c 3c80 addhi.w ip, ip, #65536 ; 0x10000 800a5b8: ebca 0101 rsb r1, sl, r1 800a5bc: eb0c 4615 add.w r6, ip, r5, lsr #16 800a5c0: 42b1 cmp r1, r6 800a5c2: d312 bcc.n 800a5ea <__divdi3+0x2aa> 800a5c4: d009 beq.n 800a5da <__divdi3+0x29a> 800a5c6: 2300 movs r3, #0 800a5c8: e70c b.n 800a3e4 <__divdi3+0xa4> 800a5ca: 4666 mov r6, ip 800a5cc: e6ee b.n 800a3ac <__divdi3+0x6c> 800a5ce: 460e mov r6, r1 800a5d0: ea46 4207 orr.w r2, r6, r7, lsl #16 800a5d4: e706 b.n 800a3e4 <__divdi3+0xa4> 800a5d6: 460d mov r5, r1 800a5d8: e6fc b.n 800a3d4 <__divdi3+0x94> 800a5da: fa1f f888 uxth.w r8, r8 800a5de: fa00 f303 lsl.w r3, r0, r3 800a5e2: eb08 4505 add.w r5, r8, r5, lsl #16 800a5e6: 42ab cmp r3, r5 800a5e8: d2ed bcs.n 800a5c6 <__divdi3+0x286> 800a5ea: 3a01 subs r2, #1 800a5ec: 2300 movs r3, #0 800a5ee: e6f9 b.n 800a3e4 <__divdi3+0xa4> 800a5f0: 463b mov r3, r7 800a5f2: e788 b.n 800a506 <__divdi3+0x1c6> 800a5f4: 462a mov r2, r5 800a5f6: e7c9 b.n 800a58c <__divdi3+0x24c> 800a5f8: 4691 mov r9, r2 800a5fa: e7b3 b.n 800a564 <__divdi3+0x224> 800a5fc: 4688 mov r8, r1 800a5fe: e76e b.n 800a4de <__divdi3+0x19e> 800a600: 3f02 subs r7, #2 800a602: 1889 adds r1, r1, r2 800a604: e723 b.n 800a44e <__divdi3+0x10e> 800a606: bf00 nop 0800a608 <__udivdi3>: 800a608: e92d 0ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp} 800a60c: 4614 mov r4, r2 800a60e: 4605 mov r5, r0 800a610: 460e mov r6, r1 800a612: 2b00 cmp r3, #0 800a614: d13f bne.n 800a696 <__udivdi3+0x8e> 800a616: 428a cmp r2, r1 800a618: d94a bls.n 800a6b0 <__udivdi3+0xa8> 800a61a: fab2 f382 clz r3, r2 800a61e: b143 cbz r3, 800a632 <__udivdi3+0x2a> 800a620: f1c3 0020 rsb r0, r3, #32 800a624: fa25 f200 lsr.w r2, r5, r0 800a628: fa01 f603 lsl.w r6, r1, r3 800a62c: 409c lsls r4, r3 800a62e: 4316 orrs r6, r2 800a630: 409d lsls r5, r3 800a632: 0c23 lsrs r3, r4, #16 800a634: fbb6 f1f3 udiv r1, r6, r3 800a638: 0c2f lsrs r7, r5, #16 800a63a: b2a0 uxth r0, r4 800a63c: fb03 6c11 mls ip, r3, r1, r6 800a640: fb00 f201 mul.w r2, r0, r1 800a644: ea47 460c orr.w r6, r7, ip, lsl #16 800a648: 42b2 cmp r2, r6 800a64a: d908 bls.n 800a65e <__udivdi3+0x56> 800a64c: 1e4f subs r7, r1, #1 800a64e: 1936 adds r6, r6, r4 800a650: f080 80ff bcs.w 800a852 <__udivdi3+0x24a> 800a654: 42b2 cmp r2, r6 800a656: f240 80fc bls.w 800a852 <__udivdi3+0x24a> 800a65a: 3902 subs r1, #2 800a65c: 1936 adds r6, r6, r4 800a65e: 1ab6 subs r6, r6, r2 800a660: fbb6 f2f3 udiv r2, r6, r3 800a664: fb03 6312 mls r3, r3, r2, r6 800a668: b2ad uxth r5, r5 800a66a: fb00 f002 mul.w r0, r0, r2 800a66e: ea45 4303 orr.w r3, r5, r3, lsl #16 800a672: 4298 cmp r0, r3 800a674: d907 bls.n 800a686 <__udivdi3+0x7e> 800a676: 1e56 subs r6, r2, #1 800a678: 191b adds r3, r3, r4 800a67a: f080 80ec bcs.w 800a856 <__udivdi3+0x24e> 800a67e: 4298 cmp r0, r3 800a680: f240 80e9 bls.w 800a856 <__udivdi3+0x24e> 800a684: 3a02 subs r2, #2 800a686: ea42 4201 orr.w r2, r2, r1, lsl #16 800a68a: 2300 movs r3, #0 800a68c: 4610 mov r0, r2 800a68e: 4619 mov r1, r3 800a690: e8bd 0ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp} 800a694: 4770 bx lr 800a696: 428b cmp r3, r1 800a698: d843 bhi.n 800a722 <__udivdi3+0x11a> 800a69a: fab3 f483 clz r4, r3 800a69e: 2c00 cmp r4, #0 800a6a0: d142 bne.n 800a728 <__udivdi3+0x120> 800a6a2: 428b cmp r3, r1 800a6a4: 4623 mov r3, r4 800a6a6: d301 bcc.n 800a6ac <__udivdi3+0xa4> 800a6a8: 4282 cmp r2, r0 800a6aa: d83b bhi.n 800a724 <__udivdi3+0x11c> 800a6ac: 2201 movs r2, #1 800a6ae: e7ed b.n 800a68c <__udivdi3+0x84> 800a6b0: b912 cbnz r2, 800a6b8 <__udivdi3+0xb0> 800a6b2: 2701 movs r7, #1 800a6b4: fbb7 f4f2 udiv r4, r7, r2 800a6b8: fab4 f284 clz r2, r4 800a6bc: 2a00 cmp r2, #0 800a6be: f040 808a bne.w 800a7d6 <__udivdi3+0x1ce> 800a6c2: 1b09 subs r1, r1, r4 800a6c4: 0c26 lsrs r6, r4, #16 800a6c6: b2a7 uxth r7, r4 800a6c8: 2301 movs r3, #1 800a6ca: fbb1 f0f6 udiv r0, r1, r6 800a6ce: fb06 1110 mls r1, r6, r0, r1 800a6d2: ea4f 4c15 mov.w ip, r5, lsr #16 800a6d6: fb07 f200 mul.w r2, r7, r0 800a6da: ea4c 4101 orr.w r1, ip, r1, lsl #16 800a6de: 428a cmp r2, r1 800a6e0: d907 bls.n 800a6f2 <__udivdi3+0xea> 800a6e2: 1909 adds r1, r1, r4 800a6e4: f100 3cff add.w ip, r0, #4294967295 800a6e8: d202 bcs.n 800a6f0 <__udivdi3+0xe8> 800a6ea: 428a cmp r2, r1 800a6ec: f200 80d4 bhi.w 800a898 <__udivdi3+0x290> 800a6f0: 4660 mov r0, ip 800a6f2: ebc2 0c01 rsb ip, r2, r1 800a6f6: fbbc f2f6 udiv r2, ip, r6 800a6fa: fb06 c112 mls r1, r6, r2, ip 800a6fe: b2ad uxth r5, r5 800a700: fb07 f702 mul.w r7, r7, r2 800a704: ea45 4501 orr.w r5, r5, r1, lsl #16 800a708: 42af cmp r7, r5 800a70a: d907 bls.n 800a71c <__udivdi3+0x114> 800a70c: 1e51 subs r1, r2, #1 800a70e: 192c adds r4, r5, r4 800a710: f080 80a3 bcs.w 800a85a <__udivdi3+0x252> 800a714: 42a7 cmp r7, r4 800a716: f240 80a0 bls.w 800a85a <__udivdi3+0x252> 800a71a: 3a02 subs r2, #2 800a71c: ea42 4200 orr.w r2, r2, r0, lsl #16 800a720: e7b4 b.n 800a68c <__udivdi3+0x84> 800a722: 2300 movs r3, #0 800a724: 461a mov r2, r3 800a726: e7b1 b.n 800a68c <__udivdi3+0x84> 800a728: f1c4 0b20 rsb fp, r4, #32 800a72c: fa03 f604 lsl.w r6, r3, r4 800a730: fa22 f30b lsr.w r3, r2, fp 800a734: 4333 orrs r3, r6 800a736: fa21 f90b lsr.w r9, r1, fp 800a73a: 0c1e lsrs r6, r3, #16 800a73c: fa01 fa04 lsl.w sl, r1, r4 800a740: fa20 f10b lsr.w r1, r0, fp 800a744: fbb9 fcf6 udiv ip, r9, r6 800a748: ea41 0b0a orr.w fp, r1, sl 800a74c: fb06 971c mls r7, r6, ip, r9 800a750: fa1f f883 uxth.w r8, r3 800a754: ea4f 451b mov.w r5, fp, lsr #16 800a758: fb08 f90c mul.w r9, r8, ip 800a75c: ea45 4507 orr.w r5, r5, r7, lsl #16 800a760: 45a9 cmp r9, r5 800a762: fa02 fa04 lsl.w sl, r2, r4 800a766: d905 bls.n 800a774 <__udivdi3+0x16c> 800a768: 18ed adds r5, r5, r3 800a76a: f10c 32ff add.w r2, ip, #4294967295 800a76e: f0c0 8088 bcc.w 800a882 <__udivdi3+0x27a> 800a772: 4694 mov ip, r2 800a774: ebc9 0505 rsb r5, r9, r5 800a778: fbb5 f7f6 udiv r7, r5, r6 800a77c: fb06 5217 mls r2, r6, r7, r5 800a780: fa1f fb8b uxth.w fp, fp 800a784: fb08 f807 mul.w r8, r8, r7 800a788: ea4b 4102 orr.w r1, fp, r2, lsl #16 800a78c: 4588 cmp r8, r1 800a78e: d903 bls.n 800a798 <__udivdi3+0x190> 800a790: 1e7a subs r2, r7, #1 800a792: 18c9 adds r1, r1, r3 800a794: d370 bcc.n 800a878 <__udivdi3+0x270> 800a796: 4617 mov r7, r2 800a798: ea47 420c orr.w r2, r7, ip, lsl #16 800a79c: 0c17 lsrs r7, r2, #16 800a79e: fa1f fc8a uxth.w ip, sl 800a7a2: fb0c f607 mul.w r6, ip, r7 800a7a6: b295 uxth r5, r2 800a7a8: ea4f 431a mov.w r3, sl, lsr #16 800a7ac: fb0c fc05 mul.w ip, ip, r5 800a7b0: fb03 6505 mla r5, r3, r5, r6 800a7b4: eb05 451c add.w r5, r5, ip, lsr #16 800a7b8: fb03 f307 mul.w r3, r3, r7 800a7bc: 42ae cmp r6, r5 800a7be: bf88 it hi 800a7c0: f503 3380 addhi.w r3, r3, #65536 ; 0x10000 800a7c4: ebc8 0101 rsb r1, r8, r1 800a7c8: eb03 4315 add.w r3, r3, r5, lsr #16 800a7cc: 4299 cmp r1, r3 800a7ce: d350 bcc.n 800a872 <__udivdi3+0x26a> 800a7d0: d047 beq.n 800a862 <__udivdi3+0x25a> 800a7d2: 2300 movs r3, #0 800a7d4: e75a b.n 800a68c <__udivdi3+0x84> 800a7d6: 4094 lsls r4, r2 800a7d8: f1c2 0820 rsb r8, r2, #32 800a7dc: fa21 f508 lsr.w r5, r1, r8 800a7e0: 0c26 lsrs r6, r4, #16 800a7e2: fa01 f702 lsl.w r7, r1, r2 800a7e6: fa20 f308 lsr.w r3, r0, r8 800a7ea: ea43 0907 orr.w r9, r3, r7 800a7ee: fbb5 f8f6 udiv r8, r5, r6 800a7f2: fb06 5518 mls r5, r6, r8, r5 800a7f6: b2a7 uxth r7, r4 800a7f8: ea4f 4119 mov.w r1, r9, lsr #16 800a7fc: ea41 4c05 orr.w ip, r1, r5, lsl #16 800a800: fb07 f308 mul.w r3, r7, r8 800a804: 4563 cmp r3, ip 800a806: fa00 f502 lsl.w r5, r0, r2 800a80a: d909 bls.n 800a820 <__udivdi3+0x218> 800a80c: eb1c 0c04 adds.w ip, ip, r4 800a810: f108 32ff add.w r2, r8, #4294967295 800a814: d23e bcs.n 800a894 <__udivdi3+0x28c> 800a816: 4563 cmp r3, ip 800a818: d93c bls.n 800a894 <__udivdi3+0x28c> 800a81a: f1a8 0802 sub.w r8, r8, #2 800a81e: 44a4 add ip, r4 800a820: ebc3 020c rsb r2, r3, ip 800a824: fbb2 f3f6 udiv r3, r2, r6 800a828: fb06 2013 mls r0, r6, r3, r2 800a82c: fa1f f989 uxth.w r9, r9 800a830: fb07 f203 mul.w r2, r7, r3 800a834: ea49 4100 orr.w r1, r9, r0, lsl #16 800a838: 428a cmp r2, r1 800a83a: d906 bls.n 800a84a <__udivdi3+0x242> 800a83c: 1e58 subs r0, r3, #1 800a83e: 1909 adds r1, r1, r4 800a840: d226 bcs.n 800a890 <__udivdi3+0x288> 800a842: 428a cmp r2, r1 800a844: d924 bls.n 800a890 <__udivdi3+0x288> 800a846: 3b02 subs r3, #2 800a848: 1909 adds r1, r1, r4 800a84a: 1a89 subs r1, r1, r2 800a84c: ea43 4308 orr.w r3, r3, r8, lsl #16 800a850: e73b b.n 800a6ca <__udivdi3+0xc2> 800a852: 4639 mov r1, r7 800a854: e703 b.n 800a65e <__udivdi3+0x56> 800a856: 4632 mov r2, r6 800a858: e715 b.n 800a686 <__udivdi3+0x7e> 800a85a: 460a mov r2, r1 800a85c: ea42 4200 orr.w r2, r2, r0, lsl #16 800a860: e714 b.n 800a68c <__udivdi3+0x84> 800a862: fa1f f18c uxth.w r1, ip 800a866: fa00 f004 lsl.w r0, r0, r4 800a86a: eb01 4505 add.w r5, r1, r5, lsl #16 800a86e: 42a8 cmp r0, r5 800a870: d2af bcs.n 800a7d2 <__udivdi3+0x1ca> 800a872: 3a01 subs r2, #1 800a874: 2300 movs r3, #0 800a876: e709 b.n 800a68c <__udivdi3+0x84> 800a878: 4588 cmp r8, r1 800a87a: d98c bls.n 800a796 <__udivdi3+0x18e> 800a87c: 3f02 subs r7, #2 800a87e: 18c9 adds r1, r1, r3 800a880: e78a b.n 800a798 <__udivdi3+0x190> 800a882: 45a9 cmp r9, r5 800a884: f67f af75 bls.w 800a772 <__udivdi3+0x16a> 800a888: f1ac 0c02 sub.w ip, ip, #2 800a88c: 18ed adds r5, r5, r3 800a88e: e771 b.n 800a774 <__udivdi3+0x16c> 800a890: 4603 mov r3, r0 800a892: e7da b.n 800a84a <__udivdi3+0x242> 800a894: 4690 mov r8, r2 800a896: e7c3 b.n 800a820 <__udivdi3+0x218> 800a898: 3802 subs r0, #2 800a89a: 1909 adds r1, r1, r4 800a89c: e729 b.n 800a6f2 <__udivdi3+0xea> 800a89e: bf00 nop 0800a8a0 : 800a8a0: e92d4008 push {r3, lr} 800a8a4: e3a00006 mov r0, #6 800a8a8: eb00005c bl 800aa20 800a8ac: e3a00001 mov r0, #1 800a8b0: faffde3a blx 80021a0 <_exit> 0800a8b4 : 800a8b4: e352000f cmp r2, #15 800a8b8: e92d0070 push {r4, r5, r6} 800a8bc: 91a03000 movls r3, r0 800a8c0: 9a000029 bls 800a96c 800a8c4: e1813000 orr r3, r1, r0 800a8c8: e3130003 tst r3, #3 800a8cc: 11a03000 movne r3, r0 800a8d0: 1a000027 bne 800a974 800a8d4: e1a0c001 mov ip, r1 800a8d8: e1a03000 mov r3, r0 800a8dc: e1a04002 mov r4, r2 800a8e0: e59c5000 ldr r5, [ip] 800a8e4: e5835000 str r5, [r3] 800a8e8: e59c5004 ldr r5, [ip, #4] 800a8ec: e5835004 str r5, [r3, #4] 800a8f0: e59c5008 ldr r5, [ip, #8] 800a8f4: e5835008 str r5, [r3, #8] 800a8f8: e2444010 sub r4, r4, #16 800a8fc: e59c500c ldr r5, [ip, #12] 800a900: e354000f cmp r4, #15 800a904: e583500c str r5, [r3, #12] 800a908: e28cc010 add ip, ip, #16 800a90c: e2833010 add r3, r3, #16 800a910: 8afffff2 bhi 800a8e0 800a914: e242c010 sub ip, r2, #16 800a918: e3ccc00f bic ip, ip, #15 800a91c: e202200f and r2, r2, #15 800a920: e28cc010 add ip, ip, #16 800a924: e3520003 cmp r2, #3 800a928: e080300c add r3, r0, ip 800a92c: e081100c add r1, r1, ip 800a930: 9a00000d bls 800a96c 800a934: e1a05001 mov r5, r1 800a938: e1a04003 mov r4, r3 800a93c: e1a0c002 mov ip, r2 800a940: e4956004 ldr r6, [r5], #4 800a944: e24cc004 sub ip, ip, #4 800a948: e35c0003 cmp ip, #3 800a94c: e4846004 str r6, [r4], #4 800a950: 8afffffa bhi 800a940 800a954: e242c004 sub ip, r2, #4 800a958: e3ccc003 bic ip, ip, #3 800a95c: e28cc004 add ip, ip, #4 800a960: e2022003 and r2, r2, #3 800a964: e081100c add r1, r1, ip 800a968: e083300c add r3, r3, ip 800a96c: e3520000 cmp r2, #0 800a970: 0a000003 beq 800a984 800a974: e4d1c001 ldrb ip, [r1], #1 800a978: e2522001 subs r2, r2, #1 800a97c: e4c3c001 strb ip, [r3], #1 800a980: 1afffffb bne 800a974 800a984: e8bd0070 pop {r4, r5, r6} 800a988: e12fff1e bx lr 0800a98c <_raise_r>: 800a98c: e351001f cmp r1, #31 800a990: e92d4038 push {r3, r4, r5, lr} 800a994: 83a03016 movhi r3, #22 800a998: e1a05000 mov r5, r0 800a99c: 85803000 strhi r3, [r0] 800a9a0: e1a04001 mov r4, r1 800a9a4: 83e00000 mvnhi r0, #0 800a9a8: 8a000013 bhi 800a9fc <_raise_r+0x70> 800a9ac: e59522dc ldr r2, [r5, #732] ; 0x2dc 800a9b0: e3520000 cmp r2, #0 800a9b4: 0a000012 beq 800aa04 <_raise_r+0x78> 800a9b8: e7923101 ldr r3, [r2, r1, lsl #2] 800a9bc: e3530000 cmp r3, #0 800a9c0: 0a00000f beq 800aa04 <_raise_r+0x78> 800a9c4: e3530001 cmp r3, #1 800a9c8: 03a00000 moveq r0, #0 800a9cc: 0a00000a beq 800a9fc <_raise_r+0x70> 800a9d0: e3730001 cmn r3, #1 800a9d4: 03a03016 moveq r3, #22 800a9d8: 05853000 streq r3, [r5] 800a9dc: 03a00001 moveq r0, #1 800a9e0: 0a000005 beq 800a9fc <_raise_r+0x70> 800a9e4: e3a05000 mov r5, #0 800a9e8: e1a00001 mov r0, r1 800a9ec: e7825101 str r5, [r2, r1, lsl #2] 800a9f0: e1a0e00f mov lr, pc 800a9f4: e12fff13 bx r3 800a9f8: e1a00005 mov r0, r5 800a9fc: e8bd4038 pop {r3, r4, r5, lr} 800aa00: e12fff1e bx lr 800aa04: e1a00005 mov r0, r5 800aa08: eb000019 bl 800aa74 <_getpid_r> 800aa0c: e1a02004 mov r2, r4 800aa10: e1a01000 mov r1, r0 800aa14: e1a00005 mov r0, r5 800aa18: eb000005 bl 800aa34 <_kill_r> 800aa1c: eafffff6 b 800a9fc <_raise_r+0x70> 0800aa20 : 800aa20: e59f3008 ldr r3, [pc, #8] ; 800aa30 800aa24: e1a01000 mov r1, r0 800aa28: e5930000 ldr r0, [r3] 800aa2c: eaffffd6 b 800a98c <_raise_r> 800aa30: 20000438 .word 0x20000438 0800aa34 <_kill_r>: 800aa34: e92d4038 push {r3, r4, r5, lr} 800aa38: e59f4030 ldr r4, [pc, #48] ; 800aa70 <_kill_r+0x3c> 800aa3c: e3a03000 mov r3, #0 800aa40: e1a05000 mov r5, r0 800aa44: e1a00001 mov r0, r1 800aa48: e1a01002 mov r1, r2 800aa4c: e5843000 str r3, [r4] 800aa50: faffddde blx 80021d0 <_kill> 800aa54: e3700001 cmn r0, #1 800aa58: 1a000002 bne 800aa68 <_kill_r+0x34> 800aa5c: e5943000 ldr r3, [r4] 800aa60: e3530000 cmp r3, #0 800aa64: 15853000 strne r3, [r5] 800aa68: e8bd4038 pop {r3, r4, r5, lr} 800aa6c: e12fff1e bx lr 800aa70: 20000778 .word 0x20000778 0800aa74 <_getpid_r>: 800aa74: e92d4008 push {r3, lr} 800aa78: faffddd0 blx 80021c0 <_getpid> 800aa7c: e8bd4008 pop {r3, lr} 800aa80: e12fff1e bx lr 800aa84: 00000000 andeq r0, r0, r0 0800aa88 <____aeabi_i2d_from_arm>: 800aa88: e51ff004 ldr pc, [pc, #-4] ; 800aa8c <____aeabi_i2d_from_arm+0x4> 800aa8c: 08008b15 .word 0x08008b15 800aa90: 0a0d6b6f .word 0x0a0d6b6f 800aa94: 00000000 .word 0x00000000 800aa98: 6f727265 .word 0x6f727265 800aa9c: 00203a72 .word 0x00203a72 800aaa0: 20646142 .word 0x20646142 800aaa4: 626d756e .word 0x626d756e 800aaa8: 66207265 .word 0x66207265 800aaac: 616d726f .word 0x616d726f 800aab0: 000a0d74 .word 0x000a0d74 800aab4: 65707845 .word 0x65707845 800aab8: 64657463 .word 0x64657463 800aabc: 6d6f6320 .word 0x6d6f6320 800aac0: 646e616d .word 0x646e616d 800aac4: 74656c20 .word 0x74656c20 800aac8: 0d726574 .word 0x0d726574 800aacc: 0000000a .word 0x0000000a 800aad0: 75736e55 .word 0x75736e55 800aad4: 726f7070 .word 0x726f7070 800aad8: 20646574 .word 0x20646574 800aadc: 74617473 .word 0x74617473 800aae0: 6e656d65 .word 0x6e656d65 800aae4: 000a0d74 .word 0x000a0d74 800aae8: 616f6c46 .word 0x616f6c46 800aaec: 676e6974 .word 0x676e6974 800aaf0: 696f7020 .word 0x696f7020 800aaf4: 6520746e .word 0x6520746e 800aaf8: 726f7272 .word 0x726f7272 800aafc: 00000a0d .word 0x00000a0d 800ab00: 00000a0d .word 0x00000a0d 800ab04: 72470a0d .word 0x72470a0d 800ab08: 30206c62 .word 0x30206c62 800ab0c: 0064372e .word 0x0064372e 800ab10: 20313047 .word 0x20313047 800ab14: 30312d58 .word 0x30312d58 800ab18: 00000000 .word 0x00000000 800ab1c: 74697865 .word 0x74697865 800ab20: 00000000 .word 0x00000000 800ab24: 70616548 .word 0x70616548 800ab28: 646e6120 .word 0x646e6120 800ab2c: 61747320 .word 0x61747320 800ab30: 63206b63 .word 0x63206b63 800ab34: 696c6c6f .word 0x696c6c6f 800ab38: 6e6f6973 .word 0x6e6f6973 800ab3c: 0000000a .word 0x0000000a 800ab40: 3d203024 .word 0x3d203024 800ab44: 00000020 .word 0x00000020 800ab48: 74732820 .word 0x74732820 800ab4c: 2f737065 .word 0x2f737065 800ab50: 78206d6d .word 0x78206d6d 800ab54: 240a0d29 .word 0x240a0d29 800ab58: 203d2031 .word 0x203d2031 800ab5c: 00000000 .word 0x00000000 800ab60: 74732820 .word 0x74732820 800ab64: 2f737065 .word 0x2f737065 800ab68: 79206d6d .word 0x79206d6d 800ab6c: 240a0d29 .word 0x240a0d29 800ab70: 203d2032 .word 0x203d2032 800ab74: 00000000 .word 0x00000000 800ab78: 74732820 .word 0x74732820 800ab7c: 2f737065 .word 0x2f737065 800ab80: 7a206d6d .word 0x7a206d6d 800ab84: 240a0d29 .word 0x240a0d29 800ab88: 203d2033 .word 0x203d2033 800ab8c: 00000000 .word 0x00000000 800ab90: 696d2820 .word 0x696d2820 800ab94: 736f7263 .word 0x736f7263 800ab98: 6e6f6365 .word 0x6e6f6365 800ab9c: 73207364 .word 0x73207364 800aba0: 20706574 .word 0x20706574 800aba4: 736c7570 .word 0x736c7570 800aba8: 0a0d2965 .word 0x0a0d2965 800abac: 3d203424 .word 0x3d203424 800abb0: 00000020 .word 0x00000020 800abb4: 6d6d2820 .word 0x6d6d2820 800abb8: 6e696d2f .word 0x6e696d2f 800abbc: 66656420 .word 0x66656420 800abc0: 746c7561 .word 0x746c7561 800abc4: 65656620 .word 0x65656620 800abc8: 61722064 .word 0x61722064 800abcc: 0d296574 .word 0x0d296574 800abd0: 2035240a .word 0x2035240a 800abd4: 0000203d .word 0x0000203d 800abd8: 6d6d2820 .word 0x6d6d2820 800abdc: 6e696d2f .word 0x6e696d2f 800abe0: 66656420 .word 0x66656420 800abe4: 746c7561 .word 0x746c7561 800abe8: 65657320 .word 0x65657320 800abec: 6172206b .word 0x6172206b 800abf0: 0d296574 .word 0x0d296574 800abf4: 2036240a .word 0x2036240a 800abf8: 0000203d .word 0x0000203d 800abfc: 6d6d2820 .word 0x6d6d2820 800ac00: 6372612f .word 0x6372612f 800ac04: 67657320 .word 0x67657320 800ac08: 746e656d .word 0x746e656d 800ac0c: 240a0d29 .word 0x240a0d29 800ac10: 203d2037 .word 0x203d2037 800ac14: 00000000 .word 0x00000000 800ac18: 74732820 .word 0x74732820 800ac1c: 70207065 .word 0x70207065 800ac20: 2074726f .word 0x2074726f 800ac24: 65766e69 .word 0x65766e69 800ac28: 6d207472 .word 0x6d207472 800ac2c: 2e6b7361 .word 0x2e6b7361 800ac30: 6e696220 .word 0x6e696220 800ac34: 20797261 .word 0x20797261 800ac38: 0000203d .word 0x0000203d 800ac3c: 240a0d29 .word 0x240a0d29 800ac40: 203d2038 .word 0x203d2038 800ac44: 00000000 .word 0x00000000 800ac48: 63612820 .word 0x63612820 800ac4c: 656c6563 .word 0x656c6563 800ac50: 69746172 .word 0x69746172 800ac54: 69206e6f .word 0x69206e6f 800ac58: 6d6d206e .word 0x6d6d206e 800ac5c: 6365732f .word 0x6365732f 800ac60: 0d29325e .word 0x0d29325e 800ac64: 2039240a .word 0x2039240a 800ac68: 0000203d .word 0x0000203d 800ac6c: 6f632820 .word 0x6f632820 800ac70: 72656e72 .word 0x72656e72 800ac74: 20676e69 .word 0x20676e69 800ac78: 636e756a .word 0x636e756a 800ac7c: 6e6f6974 .word 0x6e6f6974 800ac80: 76656420 .word 0x76656420 800ac84: 69746169 .word 0x69746169 800ac88: 69206e6f .word 0x69206e6f 800ac8c: 6d6d206e .word 0x6d6d206e 800ac90: 00000029 .word 0x00000029 800ac94: 24270a0d .word 0x24270a0d 800ac98: 61763d78 .word 0x61763d78 800ac9c: 2765756c .word 0x2765756c 800aca0: 206f7420 .word 0x206f7420 800aca4: 20746573 .word 0x20746573 800aca8: 61726170 .word 0x61726170 800acac: 6574656d .word 0x6574656d 800acb0: 726f2072 .word 0x726f2072 800acb4: 73756a20 .word 0x73756a20 800acb8: 24272074 .word 0x24272074 800acbc: 6f742027 .word 0x6f742027 800acc0: 6d756420 .word 0x6d756420 800acc4: 75632070 .word 0x75632070 800acc8: 6e657272 .word 0x6e657272 800accc: 65732074 .word 0x65732074 800acd0: 6e697474 .word 0x6e697474 800acd4: 0a0d7367 .word 0x0a0d7367 800acd8: 00000000 .word 0x00000000 800acdc: 70657453 .word 0x70657453 800ace0: 6d6d2f73 .word 0x6d6d2f73 800ace4: 73756d20 .word 0x73756d20 800ace8: 65622074 .word 0x65622074 800acec: 30203e20 .word 0x30203e20 800acf0: 0a0d302e .word 0x0a0d302e 800acf4: 00000000 .word 0x00000000 800acf8: 70657453 .word 0x70657453 800acfc: 6c757020 .word 0x6c757020 800ad00: 6d206573 .word 0x6d206573 800ad04: 20747375 .word 0x20747375 800ad08: 3e206562 .word 0x3e206562 800ad0c: 2033203d .word 0x2033203d 800ad10: 7263696d .word 0x7263696d 800ad14: 6365736f .word 0x6365736f 800ad18: 73646e6f .word 0x73646e6f 800ad1c: 00000a0d .word 0x00000a0d 800ad20: 6e6b6e55 .word 0x6e6b6e55 800ad24: 206e776f .word 0x206e776f 800ad28: 61726170 .word 0x61726170 800ad2c: 6574656d .word 0x6574656d 800ad30: 000a0d72 .word 0x000a0d72 800ad34: 726f7453 .word 0x726f7453 800ad38: 6e206465 .word 0x6e206465 800ad3c: 73207765 .word 0x73207765 800ad40: 69747465 .word 0x69747465 800ad44: 0a0d676e .word 0x0a0d676e 800ad48: 00000000 .word 0x00000000 800ad4c: 20272427 .word 0x20272427 800ad50: 64206f74 .word 0x64206f74 800ad54: 20706d75 .word 0x20706d75 800ad58: 72727563 .word 0x72727563 800ad5c: 20746e65 .word 0x20746e65 800ad60: 74746573 .word 0x74746573 800ad64: 73676e69 .word 0x73676e69 800ad68: 00000a0d .word 0x00000a0d 800ad6c: 6e726157 .word 0x6e726157 800ad70: 3a676e69 .word 0x3a676e69 800ad74: 69614620 .word 0x69614620 800ad78: 2064656c .word 0x2064656c 800ad7c: 72206f74 .word 0x72206f74 800ad80: 20646165 .word 0x20646165 800ad84: 52504545 .word 0x52504545 800ad88: 73204d4f .word 0x73204d4f 800ad8c: 69747465 .word 0x69747465 800ad90: 2e73676e .word 0x2e73676e 800ad94: 69735520 .word 0x69735520 800ad98: 6420676e .word 0x6420676e 800ad9c: 75616665 .word 0x75616665 800ada0: 2e73746c .word 0x2e73746c 800ada4: 00000a0d .word 0x00000a0d 800ada8: 00000043 .word 0x00000043 800adac: 6f707968 .word 0x6f707968 800adb0: 00000074 .word 0x00000074 800adb4: 74727173 .word 0x74727173 800adb8: 00000000 .word 0x00000000 0800adbc : 800adbc: 3ff921fb 400921fb 4012d97c 401921fb .!.?.!.@|..@.!.@ 800adcc: 401f6a7a 4022d97c 4025fdbb 402921fb zj.@|."@..%@.!)@ 800addc: 402c463a 402f6a7a 4031475c 4032d97c :F,@zj/@\G1@|.2@ 800adec: 40346b9c 4035fdbb 40378fdb 403921fb .k4@..5@..7@.!9@ 800adfc: 403ab41b 403c463a 403dd85a 403f6a7a ..:@:F<@Z.=@zj?@ 800ae0c: 40407e4c 4041475c 4042106c 4042d97c L~@@\GA@l.B@|.B@ 800ae1c: 4043a28c 40446b9c 404534ac 4045fdbb ..C@.kD@.4E@..E@ 800ae2c: 4046c6cb 40478fdb 404858eb 404921fb ..F@..G@.XH@.!I@ 0800ae3c : 800ae3c: 00a2f983 006e4e44 001529fc 002757d1 ....DNn..)...W'. 800ae4c: 00f534dd 00c0db62 0095993c 00439041 .4..b...<...A.C. 800ae5c: 00fe5163 00abdebb 00c561b7 00246e3a cQ.......a..:n$. 800ae6c: 00424dd2 00e00649 002eea09 00d1921c .MB.I........... 800ae7c: 00fe1deb 001cb129 00a73ee8 008235f5 ....)....>...5.. 800ae8c: 002ebb44 0084e99c 007026b4 005f7e41 D........&p.A~_. 800ae9c: 003991d6 00398353 0039f49c 00845f8b ..9.S.9...9.._.. 800aeac: 00bdf928 003b1ff8 0097ffde 0005980f (.....;......... 800aebc: 00ef2f11 008b5a0a 006d1f6d 00367ecf ./...Z..m.m..~6. 800aecc: 0027cb09 00b74f46 003f669e 005fea2d ..'.FO...f?.-._. 800aedc: 007527ba 00c7ebe5 00f17b3d 000739f7 .'u.....={...9.. 800aeec: 008a5292 00ea6bfb 005fb11f 008d5d08 .R...k...._..].. 800aefc: 00560330 0046fc7b 006babf0 00cfbc20 0.V.{.F...k. ... 800af0c: 009af436 001da9e3 0091615e 00e61b08 6.......^a...... 800af1c: 00659985 005f14a0 0068408d 00ffd880 ..e..._..@h..... 800af2c: 004d7327 00310606 001556ca 0073a8c9 'sM...1..V....s. 800af3c: 0060e27b 00c08c6b {.`.k... 0800af44 : 800af44: 00000002 00000003 00000004 00000006 ................ 800af54: 00000000 .... 0800af58 : 800af58: 40000000 3ff921fb 00000000 3e74442d ...@.!.?....-Dt> 800af68: 80000000 3cf84698 60000000 3b78cc51 .....F.<...`Q.x; 800af78: 80000000 39f01b83 40000000 387a2520 .......9...@ %z8 800af88: 80000000 36e38222 00000000 3569f31d ...."..6......i5 0800af98 : 800af98: 222f65e2 3c7a2b7f 33145c07 3c81a626 .e/".+z<.\.3&..< 800afa8: 7af0cbbd 3c700788 33145c07 3c91a626 ...z..p<.\.3&..< 0800afb8 : 800afb8: 0561bb4f 3fddac67 54442d18 3fe921fb O.a.g..?.-DT.!.? 800afc8: d281f69b 3fef730b 54442d18 3ff921fb .....s.?.-DT.!.?