Register usage:
;
; R3: Holds value used to toggle D4 in PORT D
; R16: Temporary use
; R17: Port B contents to turn on Antenna 1
; R18: Port B contents to turn on Antenna 2
; R19: Port B contents to turn on Antenna 3
; R20: Port B contents to turn on Antenna 4
; R21: Bit image for PORT D
; R24-R28: General counters
;


.equ	portd=$12
.equ	ddrd=$11
.equ	pind=$10
.equ	portb=$18
.equ	ddrb=$17
.equ	pinb=$16

.equ	divcount=50		;number of clock pulse transitions for each antenna switch time


	.org	0		;code always begins at address 0
	rjmp	start
	.org	4		;jump over IVT


;*************** main ***************

start:	rcall	initports	;initialize ports
	rcall	delay		;wait about 200 mS for things to settle
	
;
; Revision 1.1 -- Check PD0, which is now pulled up by the internal resistor.
; If (PD0==1) use the normal clock speed. Otherwise, drop the clock by 12%.
;

	in	r16,pind
	bst	r16,0		;Check on PD0
	brtc	slow_code	;If (PD0==0) then run the slow code
	rjmp	normal_code	;Otherwise run the normal code


;**********************************************************************
;
; SLOW_CODE
;
; This is the entry point for the slower (by 12%) code.
;
;**********************************************************************


	
;
; Static register setups
;

slow_code:

	ldi	r16,0b00010000	; value to toggle D4 in port D
	mov	r3,r16
	
	ldi	r17,0b10101001	; turn on Antenna 1 value
	ldi	r18,0b10100110	; turn on Antenna 2 value
	ldi	r19,0b10011010	; turn on Antenna 3 value
	ldi	r20,0b01101010	; turn on Antenna 4 value
	ldi	r21,0		; all pins on port D initially LOW
	ldi	r24,divcount	; prime for 1st execution of ANT1 logic

;
; ANTENNA1 portion of cycle
;

mainloop:	out	portb,r17	;turn on antenna1	

	
loop1:	eor	r21,r3		;toggle 100 kHz clock signal
	nop
	out	portd,r21	;update I/O port pins
	ldi	r25,divcount	;setup for LOOP2
	dec	r24
	breq	ant2
	rjmp	loop1



;
; ANTENNA2 portion of cycle
;

ant2:	out	portb,r18	;turn on antenna2	
	
loop2:	eor	r21,r3		;toggle 100 kHz clock signal
	nop
	out	portd,r21	;update I/O port pins
	ldi	r26,divcount	;setup for LOOP3
	dec	r25
	breq	ant3
	rjmp	loop2


;
; ANTENNA3 portion of cycle
;

ant3:	out	portb,r19	;turn on antenna3	
	
loop3:	eor	r21,r3		;toggle 100 kHz clock signal
	nop
	out	portd,r21	;update I/O port pins
	ldi	r27,divcount	;setup for LOOP4
	dec	r26
	breq	ant4
	rjmp	loop3



;
; ANTENNA4 portion of cycle
;

ant4:	out	portb,r20	;turn on antenna4	

;
; R28 setup in LOOP3
;
	
loop4:	eor	r21,r3		;toggle 100 kHz clock signal
	nop
	out	portd,r21	;update I/O port pins
	ldi	r24,divcount	;setup for LOOP1
	dec	r27
	breq	mainloop
	rjmp	loop4

	
	

;**********************************************************************
;
; NORMAL_CODE
;
; This is the entry point for the normal speed code. It is identical to
; the code from the original version.
;
;**********************************************************************

normal_code:

;
; Static register setups
;

	ldi	r16,0b00010000	; value to toggle D4 in port D
	mov	r3,r16
	
	ldi	r17,0b10101001	; turn on Antenna 1 value
	ldi	r18,0b10100110	; turn on Antenna 2 value
	ldi	r19,0b10011010	; turn on Antenna 3 value
	ldi	r20,0b01101010	; turn on Antenna 4 value
	ldi	r21,0		; all pins on port D initially LOW
	ldi	r24,divcount	; prime for 1st execution of ANT1 logic

;
; ANTENNA1 portion of cycle
;

nmainloop:	out	portb,r17	;turn on antenna1	

	
nloop1:	eor	r21,r3		;toggle 100 kHz clock signal
	out	portd,r21	;update I/O port pins
	ldi	r25,divcount	;setup for LOOP2
	dec	r24
	breq	nant2
	rjmp	nloop1



;
; ANTENNA2 portion of cycle
;

nant2:	out	portb,r18	;turn on antenna2	
	
nloop2:	eor	r21,r3		;toggle 100 kHz clock signal
	out	portd,r21	;update I/O port pins
	ldi	r26,divcount	;setup for LOOP3
	dec	r25
	breq	nant3
	rjmp	nloop2


;
; ANTENNA3 portion of cycle
;

nant3:	out	portb,r19	;turn on antenna3	
	
nloop3:	eor	r21,r3		;toggle 100 kHz clock signal
	out	portd,r21	;update I/O port pins
	ldi	r27,divcount	;setup for LOOP4
	dec	r26
	breq	nant4
	rjmp	nloop3



;
; ANTENNA4 portion of cycle
;

nant4:	out	portb,r20	;turn on antenna4	

;
; R28 setup in LOOP3
;
	
nloop4:	eor	r21,r3		;toggle 100 kHz clock signal
	out	portd,r21	;update I/O port pins
	ldi	r24,divcount	;setup for LOOP1
	dec	r27
	breq	nmainloop
	rjmp	nloop4





;*******************************************************
;
;Delay: Wait for approximately 200 mS (depends on 1 MHz CPU2 clock)
;
;Destroys R17, R18
;
;*******************************************************

delay:	clr	r17
	clr	r18
dl1:	dec	r17
	brne	dl1
	dec	r18
	brne	dl1
	ret
	

;*******************************************************
;
;Delay50: Wait for approximately 50 mS (depends on 1 MHz CPU2 clock)
;
;Destroys R17, R18
;
;*******************************************************

delay50:	clr	r17
		ldi	r18,$40
		rjmp	dl1
		
		
;*******************************************************
;
;Delay25: Wait for approximately 12 mS (depends on 1 MHz CPU2 clock)
;
;Destroys R17, R18
;
;*******************************************************

delay25:	clr	r17
		ldi	r18,$10
		rjmp	dl1




	
;
;******************** initports ******************
;
;Set port D as all outputs, except for PD0 -- an input with
;	a pull-up resistor.
;
;Set port B as all outputs.
;;
;R16 is destroyed.
;
;*************************************************
;

initports:
	ser	r16		;ff->R16
	out	ddrb,r16	;make port B all outputs

	ldi	r16,$fe
	out	ddrd,r16	;make port D all outputs
				;except for PD0
	
	ldi	r16,$01
	out	portd,r16	;turn on the pull-up resistor on PD0
	
	ret