library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_unsigned.all;



entity SPI_ausgabe is	
    Port 
	( 
		pi1r_RST 	: in std_logic;
		pi1c_CLK	: in std_logic;			
		pi8_Data 	: in std_logic_vector (7 downto 0) ;                                   
		pi1_SCLK 	: in std_logic ;			-- CLK heruntergeteilt
		pi1_Enable	: in std_logic ;			-- neues Byte vorliegend?
		pi1_Enable2	: in std_logic ; 
		po1_Ready 	: out std_logic ;			-- Byte übertragen?
		po1_nSS 	: out std_logic ;    		-- not slave select, ausgewählt bei 0                             
		po1_SCLK 	: out std_logic  ;			-- Clock
		po1_MOSI 	: out std_logic      		-- Datenleitung       
        ) ;
		
end SPI_ausgabe;


architecture Behavioral of SPI_ausgabe is
	signal s1_SCLK_Fall		: std_logic ;
	signal s1_SCLK_next		: std_logic ;
	signal s8_Data			: std_logic_vector (7 downto 0);
	signal si_Count			: integer range 0 to 7;
	signal s1_Blocked		: std_logic;			-- auf 1: Daten werden gerade ausgegeben
	signal s1_Data_now		: std_logic;
begin

	process(pi1c_CLK,pi1r_RST)
		begin	
			
			if pi1r_RST='0' then
				s1_SCLK_next	<= '0';
				po1_nSS		<='1';
			elsif rising_edge (pi1c_CLK) then
				s1_SCLK_next	<= pi1_SCLK;
				po1_nSS		<='0';
			end if;
		end process;
		
		s1_SCLK_Fall	<= not pi1_SCLK and s1_SCLK_next ; 

	process (pi1c_CLK,pi1r_RST)
		  begin
			if pi1r_RST='0' then
				s8_Data		<= (others=>'0');
				si_Count 	<= 0;
				po1_Ready	<= '0';
				s1_Blocked	<= '0';
				po1_nSS		<= '1';
			elsif rising_edge (pi1c_CLK) then
				po1_nSS			<= '0';
				if (pi1_Enable = '1' or pi1_Enable2 = '1') and s1_Blocked = '0' then
					si_Count	<= 7;
					s8_Data		<=	pi8_Data;
					po1_Ready	<= '0';
					s1_Blocked	<= '1';
				end if;
				
				if (s1_SCLK_Fall = '1') then
					if si_Count /= 0 then
						s8_Data(7 downto 0) <= s8_Data(6 downto 0) & '0';
						si_Count <= si_Count - 1 ;
					else
						po1_Ready	<= '1';
						s1_Blocked	<= '0';
						s8_Data		<= (others=>'0');  -- eingefügt
				end if;
			end if;
				
				if s1_Blocked='1' then
					po1_SCLK <= pi1_SCLK; 					-- CLK nur an Display durchgeben, wenn Daten übertragen werden
				else po1_SCLK <= '1' ;
				end if;
			end if;
		  end process;
  
	  s1_Data_now <= s8_Data(7);
	  po1_MOSI <= s1_Data_now;
  
 end Behavioral;