library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity entprellen is
    Port ( clk    : in  STD_LOGIC;
           keyin  : in  STD_LOGIC;
           keyout : out  STD_LOGIC);
end entprellen;

architecture Behavioral of entprellen is
signal keydeb : std_logic := '0';
signal debcnt : integer range 0 to 63 := 0;
begin
   process(clk,keyin) 
   begin
      if rising_edge(clk) then
      -- XOR
			if (keyin=keydeb) then 
				debcnt <= 0;
			else 
				debcnt <= debcnt+1;
			end if;
      -- Latch
			if (debcnt=63) then 
				keydeb <= keyin; 
			end if;
		end if;
   end process;
   keyout <= keydeb;

end Behavioral;