mux Project Status (10/29/2012 - 17:36:51)
Project File: a2.xise Parser Errors: No Errors
Module Name: mux Implementation State: Synthesized (Failed)
Target Device: xc3s100e-4vq100
  • Errors:
 
Product Version:ISE 12.2
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slices 4 960 0%
Number of 4 input LUTs 8 1920 0%
Number of bonded IOBs 25 66 37%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMo 29. Okt 16:45:59 2012   
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 10/29/2012 - 17:40:05