DDR2_Test_Top Project Status
Project File: FIFO.xise Parser Errors: No Errors
Module Name: DDR2_Test_Top Implementation State: Programming File Generated
Target Device: xc6slx16-2csg324
  • Errors:
No Errors
Product Version:ISE 14.1
  • Warnings:
467 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 382 18,224 2%  
    Number used as Flip Flops 382      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 556 9,112 6%  
    Number used as logic 536 9,112 5%  
        Number using O6 output only 380      
        Number using O5 output only 49      
        Number using O5 and O6 107      
        Number used as ROM 0      
    Number used as Memory 0 2,176 0%  
    Number used exclusively as route-thrus 20      
        Number with same-slice register load 15      
        Number with same-slice carry load 5      
        Number with other load 0      
Number of occupied Slices 192 2,278 8%  
Nummber of MUXCYs used 148 4,556 3%  
Number of LUT Flip Flop pairs used 590      
    Number with an unused Flip Flop 238 590 40%  
    Number with an unused LUT 34 590 5%  
    Number of fully used LUT-FF pairs 318 590 53%  
    Number of unique control sets 37      
    Number of slice register sites lost
        to control set restrictions
130 18,224 1%  
Number of bonded IOBs 30 232 12%  
    Number of LOCed IOBs 10 30 33%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 2 16 12%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 1      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 248 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 24 248 9%  
    Number used as IODELAY2s 0      
    Number used as IODRP2s 2      
    Number used as IODRP2_MCBs 22      
Number of OLOGIC2/OSERDES2s 22 248 8%  
    Number used as OLOGIC2s 0      
    Number used as OSERDES2s 22      
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 1 4 25%  
Number of DSP48A1s 0 32 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 1 2 50%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 2 50%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.90      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentDi 30. Okt 16:29:35 20120444 Warnings (0 new)104 Infos (0 new)
Translation ReportCurrentDi 30. Okt 16:31:39 2012023 Warnings (0 new)20 Infos (0 new)
Map ReportCurrentDi 30. Okt 16:32:01 2012007 Infos (0 new)
Place and Route ReportCurrentDi 30. Okt 16:32:18 2012003 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentDi 30. Okt 16:32:25 2012004 Infos (0 new)
Bitgen ReportCurrentDi 30. Okt 16:33:26 2012000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentDi 30. Okt 16:31:46 2012
WebTalk ReportCurrentDi 30. Okt 16:35:11 2012
WebTalk Log FileCurrentDi 30. Okt 16:35:17 2012

Date Generated: 11/01/2012 - 08:04:31