//HIGH
	LDI temp_1, (1<<ENC28J60_BIT_ECON1_BSEL_1)|(0<<ENC28J60_BIT_ECON1_BSEL_0)	//Bank 0x02
	STS (SRAM_BANK_NUMBER_NEW), temp_1		
	
	RCALL CHANGE_BANK
	
	LDI temp_1, (ENC28J60_OP_BF_CLEAR | MAMXFLH)
	STS (SRAM_OP_CODE_CLEAR), temp_1
	
	RCALL CLEAR_REGISTER_VALUE
	
	LDI temp_1, (ENC28J60_OP_BF_SET | MAMXFLH)		//0x80 | 0x0B	
	STS (SRAM_OP_CODE), temp_1	
	LDI temp_1, HIGH(1518)							//0x05EE	=	5 238				
	STS (SRAM_DATA_CODE), temp_1					//HIER IST EIN FEHLER ERGEBNIS = 7 statt 5
	
	RCALL WRITE_REGISTER_VALUE						//Value Of Reset = 6 S.14
													

//Kontrolle
LDI temp_1, (1<<ENC28J60_BIT_ECON1_BSEL_1)|(1<<ENC28J60_BIT_ECON1_BSEL_0)	//Bank 0x02
STS (SRAM_BANK_NUMBER_NEW), temp_1
RCALL CHANGE_BANK
LDI temp_1, (ENC_RD_CTL_REG | MAADR5)
STS (SRAM_OP_CODE), temp_1
rcall ENC_READ_BANK_VALUE
sbi portb, TEST_LED
rcall UART_SEND
		

	SBR STATUS_FLAG, (1<<START_INIT)

	RET
//*************************************************************************************************
CHANGE_BANK:
	LDS temp_1, (SRAM_BANK_NUMBER_NEW)
	LDS temp_2, (SRAM_BANK_NUMBER_OLD)

	CP temp_1, temp_2
	BREQ CHANGE_BANK_END
	TST temp_1
	BREQ BANK_00
	CPI temp_1, 1
	BREQ BANK_01
	CPI temp_1, 2
	BREQ BANK_02
	CPI temp_1, 3
	BREQ BANK_03

BANK_00:
	RCALL CLEAR_BANK_REGISTER
//Set Bank 0
	LDI temp_1, (ENC28J60_OP_BF_SET | ECON1)		//0x80 | 0x1F
	STS (SRAM_OP_CODE), temp_1
	LDI temp_1, (0<<ENC28J60_BIT_ECON1_BSEL_1)|(0<<ENC28J60_BIT_ECON1_BSEL_0)
	STS (SRAM_DATA_CODE), temp_1
	STS (SRAM_BANK_NUMBER_OLD), temp_1
	RCALL WRITE_REGISTER_VALUE
	RJMP CHANGE_BANK_END
BANK_01:
	RCALL CLEAR_BANK_REGISTER
//Set Bank 1
	LDI temp_1, (ENC28J60_OP_BF_SET | ECON1)		//0x80 | 0x1F
	STS (SRAM_OP_CODE), temp_1
	LDI temp_1, (0<<ENC28J60_BIT_ECON1_BSEL_1)|(1<<ENC28J60_BIT_ECON1_BSEL_0)
	STS (SRAM_DATA_CODE), temp_1
	STS (SRAM_BANK_NUMBER_OLD), temp_1
	RCALL WRITE_REGISTER_VALUE
	RJMP CHANGE_BANK_END
BANK_02:
	RCALL CLEAR_BANK_REGISTER
//Set Bank 2
	LDI temp_1, (ENC28J60_OP_BF_SET | ECON1)		//0x80 | 0x1F
	STS (SRAM_OP_CODE), temp_1
	LDI temp_1, (1<<ENC28J60_BIT_ECON1_BSEL_1)|(0<<ENC28J60_BIT_ECON1_BSEL_0)
	STS (SRAM_DATA_CODE), temp_1
	STS (SRAM_BANK_NUMBER_OLD), temp_1
	RCALL WRITE_REGISTER_VALUE
	RJMP CHANGE_BANK_END
BANK_03:
	RCALL CLEAR_BANK_REGISTER
//Set Bank 3
	LDI temp_1, (ENC28J60_OP_BF_SET | ECON1)		//0x80 | 0x1F
	STS (SRAM_OP_CODE), temp_1
	LDI temp_1, (1<<ENC28J60_BIT_ECON1_BSEL_1)|(1<<ENC28J60_BIT_ECON1_BSEL_0)
	STS (SRAM_DATA_CODE), temp_1
	STS (SRAM_BANK_NUMBER_OLD), temp_1
	RCALL WRITE_REGISTER_VALUE	

CHANGE_BANK_END:
	RET
//*************************************************************************************************
CLEAR_BANK_REGISTER:
	LDI temp_1, (ENC28J60_OP_BF_CLEAR | ECON1)	//0xA0 | 0x1F
	STS (SRAM_OP_CODE), temp_1
	LDI temp_1, (1<<ENC28J60_BIT_ECON1_BSEL_1)|(1<<ENC28J60_BIT_ECON1_BSEL_0)
	STS (SRAM_DATA_CODE), temp_1

	RCALL WRITE_REGISTER_VALUE

	RET
//*************************************************************************************************
CLEAR_REGISTER_VALUE:
//CS = 0
	CBI ENC28J60_PORT_B, ETH_CS					//PB0 = 0
//Write op-code
	LDS temp_1, (SRAM_OP_CODE_CLEAR)					
	OUT SPDR, temp_1
SPI_LOOP_DATA_SHIFT_6:
	IN temp_1, SPSR
	SBRS temp_1, SPIF
	RJMP SPI_LOOP_DATA_SHIFT_6
//Write data
	LDS temp_1, 0xFF//(SRAM_DATA_CODE)
	OUT SPDR, temp_1 	
SPI_LOOP_DATA_SHIFT_7:
	IN temp_1, SPSR
	SBRS temp_1, SPIF
	RJMP SPI_LOOP_DATA_SHIFT_7
//	IN temp_1, SPDR								//Daten aus ENC
//CS = 1
	SBI ENC28J60_PORT_B, ETH_CS					//PB0 = 1

	RET
//*************************************************************************************************
WRITE_REGISTER_VALUE:
//CS = 0
	CBI ENC28J60_PORT_B, ETH_CS					//PB0 = 0
//Write op-code
	LDS temp_1, (SRAM_OP_CODE)					
	OUT SPDR, temp_1
SPI_LOOP_DATA_SHIFT_1:
	IN temp_1, SPSR
	SBRS temp_1, SPIF
	RJMP SPI_LOOP_DATA_SHIFT_1
//Write data
	LDS temp_1, (SRAM_DATA_CODE)
	OUT SPDR, temp_1 	
SPI_LOOP_DATA_SHIFT_2:
	IN temp_1, SPSR
	SBRS temp_1, SPIF
	RJMP SPI_LOOP_DATA_SHIFT_2
	IN temp_1, SPSR							//Daten aus ENC
//CS = 1
	SBI ENC28J60_PORT_B, ETH_CS					//PB0 = 1
	
	RET
//*************************************************************************************************
ENC_READ_BANK_REGISTER:
/*
Achtung, man muss bei allen Regs die mit MA oder MI anfangen ein dummy
byte lesen.
*/
	CBI ENC28J60_PORT_B, ETH_CS					//PB0 = 0
	
	LDS temp_1, (SRAM_OP_CODE)					
	OUT SPDR, temp_1
SPI_LOOP_DATA_SHIFT_3:
	IN temp_1, SPSR
	SBRS temp_1, SPIF
	RJMP SPI_LOOP_DATA_SHIFT_3
//Read dummy
	LDS temp_1, ENC_READ_DUMMY
	OUT SPDR, temp_1 	
SPI_LOOP_DATA_SHIFT_4:
	IN temp_1, SPSR
	SBRS temp_1, SPIF
	RJMP SPI_LOOP_DATA_SHIFT_4
	
	LDS temp_1, ENC_READ_DUMMY
	OUT SPDR, temp_1 	
SPI_LOOP_DATA_SHIFT_5:
	IN temp_1, SPSR
	SBRS temp_1, SPIF
	RJMP SPI_LOOP_DATA_SHIFT_5	
	IN temp_1, SPDR								//Daten aus ENC
	STS (SRAM_BANK_REG_VALUE), temp_1
//CS = 1
	SBI ENC28J60_PORT_B, ETH_CS					//PB0 = 1

	RET
//*************************************************************************************************
ENC_READ_BANK_VALUE:
	RCALL CHANGE_BANK

	RCALL ENC_READ_BANK_REGISTER

	RET
//*************************************************************************************************