hardware/enc28j60.h

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00001 
00002 //*****************************************************************************
00003 //
00004 // File Name    : 'enc28j60.h'
00005 // Title                : Microchip ENC28J60 Ethernet Interface Driver
00006 // Author               : Pascal Stang (c)2005
00007 // Created              : 9/22/2005
00008 // Revised              : 9/22/2005
00009 // Version              : 0.1
00010 // Target MCU   : Atmel AVR series
00011 // Editor Tabs  : 4
00012 //
00022 //
00023 //*****************************************************************************
00025 
00026 
00027 #ifndef ENC28J60_H
00028 #define ENC28J60_H
00029 
00030 // ENC28J60 Control Registers
00031 // Control register definitions are a combination of address,
00032 // bank number, and Ethernet/MAC/PHY indicator bits.
00033 // - Register address   (bits 0-4)
00034 // - Bank number                (bits 5-6)
00035 // - MAC/PHY indicator  (bit 7)
00036 #define ADDR_MASK       0x1F
00037 #define BANK_MASK       0x60
00038 #define SPRD_MASK       0x80
00039 // All-bank registers
00040 #define EIE             0x1B
00041 #define EIR             0x1C
00042 #define ESTAT           0x1D
00043 #define ECON2           0x1E
00044 #define ECON1           0x1F
00045 // Bank 0 registers
00046 #define ERDPTL          (0x00|0x00)
00047 #define ERDPTH          (0x01|0x00)
00048 #define EWRPTL          (0x02|0x00)
00049 #define EWRPTH          (0x03|0x00)
00050 #define ETXSTL          (0x04|0x00)
00051 #define ETXSTH          (0x05|0x00)
00052 #define ETXNDL          (0x06|0x00)
00053 #define ETXNDH          (0x07|0x00)
00054 #define ERXSTL          (0x08|0x00)
00055 #define ERXSTH          (0x09|0x00)
00056 #define ERXNDL          (0x0A|0x00)
00057 #define ERXNDH          (0x0B|0x00)
00058 #define ERXRDPTL        (0x0C|0x00)
00059 #define ERXRDPTH        (0x0D|0x00)
00060 #define ERXWRPTL        (0x0E|0x00)
00061 #define ERXWRPTH        (0x0F|0x00)
00062 #define EDMASTL         (0x10|0x00)
00063 #define EDMASTH         (0x11|0x00)
00064 #define EDMANDL         (0x12|0x00)
00065 #define EDMANDH         (0x13|0x00)
00066 #define EDMADSTL        (0x14|0x00)
00067 #define EDMADSTH        (0x15|0x00)
00068 #define EDMACSL         (0x16|0x00)
00069 #define EDMACSH         (0x17|0x00)
00070 // Bank 1 registers
00071 #define EHT0            (0x00|0x20)
00072 #define EHT1            (0x01|0x20)
00073 #define EHT2            (0x02|0x20)
00074 #define EHT3            (0x03|0x20)
00075 #define EHT4            (0x04|0x20)
00076 #define EHT5            (0x05|0x20)
00077 #define EHT6            (0x06|0x20)
00078 #define EHT7            (0x07|0x20)
00079 #define EPMM0           (0x08|0x20)
00080 #define EPMM1           (0x09|0x20)
00081 #define EPMM2           (0x0A|0x20)
00082 #define EPMM3           (0x0B|0x20)
00083 #define EPMM4           (0x0C|0x20)
00084 #define EPMM5           (0x0D|0x20)
00085 #define EPMM6           (0x0E|0x20)
00086 #define EPMM7           (0x0F|0x20)
00087 #define EPMCSL          (0x10|0x20)
00088 #define EPMCSH          (0x11|0x20)
00089 #define EPMOL           (0x14|0x20)
00090 #define EPMOH           (0x15|0x20)
00091 #define EWOLIE          (0x16|0x20)
00092 #define EWOLIR          (0x17|0x20)
00093 #define ERXFCON         (0x18|0x20)
00094 #define EPKTCNT         (0x19|0x20)
00095 // Bank 2 registers
00096 #define MACON1          (0x00|0x40|0x80)
00097 #define MACON2          (0x01|0x40|0x80)
00098 #define MACON3          (0x02|0x40|0x80)
00099 #define MACON4          (0x03|0x40|0x80)
00100 #define MABBIPG         (0x04|0x40|0x80)
00101 #define MAIPGL          (0x06|0x40|0x80)
00102 #define MAIPGH          (0x07|0x40|0x80)
00103 #define MACLCON1        (0x08|0x40|0x80)
00104 #define MACLCON2        (0x09|0x40|0x80)
00105 #define MAMXFLL         (0x0A|0x40|0x80)
00106 #define MAMXFLH         (0x0B|0x40|0x80)
00107 #define MAPHSUP         (0x0D|0x40|0x80)
00108 #define MICON           (0x11|0x40|0x80)
00109 #define MICMD           (0x12|0x40|0x80)
00110 #define MIREGADR        (0x14|0x40|0x80)
00111 #define MIWRL           (0x16|0x40|0x80)
00112 #define MIWRH           (0x17|0x40|0x80)
00113 #define MIRDL           (0x18|0x40|0x80)
00114 #define MIRDH           (0x19|0x40|0x80)
00115 // Bank 3 registers
00116 #define MAADR1          (0x00|0x60|0x80)
00117 #define MAADR0          (0x01|0x60|0x80)
00118 #define MAADR3          (0x02|0x60|0x80)
00119 #define MAADR2          (0x03|0x60|0x80)
00120 #define MAADR5          (0x04|0x60|0x80)
00121 #define MAADR4          (0x05|0x60|0x80)
00122 #define EBSTSD          (0x06|0x60)
00123 #define EBSTCON         (0x07|0x60)
00124 #define EBSTCSL         (0x08|0x60)
00125 #define EBSTCSH         (0x09|0x60)
00126 #define MISTAT          (0x0A|0x60|0x80)
00127 #define EREVID          (0x12|0x60)
00128 #define ECOCON          (0x15|0x60)
00129 #define EFLOCON         (0x17|0x60)
00130 #define EPAUSL          (0x18|0x60)
00131 #define EPAUSH          (0x19|0x60)
00132 // PHY registers
00133 #define PHCON1          0x00
00134 #define PHSTAT1         0x01
00135 #define PHHID1          0x02
00136 #define PHHID2          0x03
00137 #define PHCON2          0x10
00138 #define PHSTAT2         0x11
00139 #define PHIE            0x12
00140 #define PHIR            0x13
00141 #define PHLCON          0x14
00142 
00143 // ENC28J60 EIE Register Bit Definitions
00144 #define EIE_INTIE               0x80
00145 #define EIE_PKTIE               0x40
00146 #define EIE_DMAIE               0x20
00147 #define EIE_LINKIE              0x10
00148 #define EIE_TXIE                0x08
00149 #define EIE_WOLIE               0x04
00150 #define EIE_TXERIE              0x02
00151 #define EIE_RXERIE              0x01
00152 // ENC28J60 EIR Register Bit Definitions
00153 #define EIR_PKTIF               0x40
00154 #define EIR_DMAIF               0x20
00155 #define EIR_LINKIF              0x10
00156 #define EIR_TXIF                0x08
00157 #define EIR_WOLIF               0x04
00158 #define EIR_TXERIF              0x02
00159 #define EIR_RXERIF              0x01
00160 // ENC28J60 ESTAT Register Bit Definitions
00161 #define ESTAT_INT               0x80
00162 #define ESTAT_LATECOL           0x10
00163 #define ESTAT_RXBUSY            0x04
00164 #define ESTAT_TXABRT            0x02
00165 #define ESTAT_CLKRDY            0x01
00166 // ENC28J60 ECON2 Register Bit Definitions
00167 #define ECON2_AUTOINC           0x80
00168 #define ECON2_PKTDEC            0x40
00169 #define ECON2_PWRSV             0x20
00170 #define ECON2_VRPS              0x08
00171 // ENC28J60 ECON1 Register Bit Definitions
00172 #define ECON1_TXRST             0x80
00173 #define ECON1_RXRST             0x40
00174 #define ECON1_DMAST             0x20
00175 #define ECON1_CSUMEN            0x10
00176 #define ECON1_TXRTS             0x08
00177 #define ECON1_RXEN              0x04
00178 #define ECON1_BSEL1             0x02
00179 #define ECON1_BSEL0             0x01
00180 // ENC28J60 MACON1 Register Bit Definitions
00181 #define MACON1_LOOPBK           0x10
00182 #define MACON1_TXPAUS           0x08
00183 #define MACON1_RXPAUS           0x04
00184 #define MACON1_PASSALL          0x02
00185 #define MACON1_MARXEN           0x01
00186 // ENC28J60 MACON2 Register Bit Definitions
00187 #define MACON2_MARST            0x80
00188 #define MACON2_RNDRST           0x40
00189 #define MACON2_MARXRST          0x08
00190 #define MACON2_RFUNRST          0x04
00191 #define MACON2_MATXRST          0x02
00192 #define MACON2_TFUNRST          0x01
00193 // ENC28J60 MACON3 Register Bit Definitions
00194 #define MACON3_PADCFG2          0x80
00195 #define MACON3_PADCFG1          0x40
00196 #define MACON3_PADCFG0          0x20
00197 #define MACON3_TXCRCEN          0x10
00198 #define MACON3_PHDRLEN          0x08
00199 #define MACON3_HFRMLEN          0x04
00200 #define MACON3_FRMLNEN          0x02
00201 #define MACON3_FULDPX           0x01
00202 // ENC28J60 MICMD Register Bit Definitions
00203 #define MICMD_MIISCAN           0x02
00204 #define MICMD_MIIRD             0x01
00205 // ENC28J60 MISTAT Register Bit Definitions
00206 #define MISTAT_NVALID           0x04
00207 #define MISTAT_SCAN             0x02
00208 #define MISTAT_BUSY             0x01
00209 // ENC28J60 PHY PHCON1 Register Bit Definitions
00210 #define PHCON1_PRST             0x8000
00211 #define PHCON1_PLOOPBK          0x4000
00212 #define PHCON1_PPWRSV           0x0800
00213 #define PHCON1_PDPXMD           0x0100
00214 // ENC28J60 PHY PHSTAT1 Register Bit Definitions
00215 #define PHSTAT1_PFDPX           0x1000
00216 #define PHSTAT1_PHDPX           0x0800
00217 #define PHSTAT1_LLSTAT          0x0004
00218 #define PHSTAT1_JBSTAT          0x0002
00219 // ENC28J60 PHY PHCON2 Register Bit Definitions
00220 #define PHCON2_FRCLINK          0x4000
00221 #define PHCON2_TXDIS            0x2000
00222 #define PHCON2_JABBER           0x0400
00223 #define PHCON2_HDLDIS           0x0100
00224 
00225 // ENC28J60 Packet Control Byte Bit Definitions
00226 #define PKTCTRL_PHUGEEN         0x08
00227 #define PKTCTRL_PPADEN          0x04
00228 #define PKTCTRL_PCRCEN          0x02
00229 #define PKTCTRL_POVERRIDE       0x01
00230 
00231 // SPI operation codes
00232 #define ENC28J60_READ_CTRL_REG  0x00
00233 #define ENC28J60_READ_BUF_MEM   0x3A
00234 #define ENC28J60_WRITE_CTRL_REG 0x40
00235 #define ENC28J60_WRITE_BUF_MEM  0x7A
00236 #define ENC28J60_BIT_FIELD_SET  0x80
00237 #define ENC28J60_BIT_FIELD_CLR  0xA0
00238 #define ENC28J60_SOFT_RESET     0xFF
00239 
00240 // buffer boundaries applied to internal 8K ram
00241 // entire available packet buffer space is allocated
00242 #define TXSTART_INIT    0x1000  // start TX buffer at 0
00243 #define RXSTART_INIT    0x0000  // give TX buffer space for one full ethernet frame (~1500 bytes)
00244 #define RXSTOP_INIT     0x0FFF  // receive buffer gets the rest
00245 
00246 //#define TXSTART_INIT          MAX_FRAMELEN    // start TX buffer at 0
00247 //#define RXSTART_INIT          MAX_FRAMELEN+1  // give TX buffer space for one full ethernet frame (~1500 bytes)
00248 
00249 #define MAX_FRAMELEN    512     // maximum ethernet frame length
00250 
00251 // unsigned char buffer[MAX_FRAMELEN];
00252 
00253 // Ethernet constants
00254 // #define ETHERNET_MIN_PACKET_LENGTH   0x3C
00255 // #define ETHERNET_HEADER_LENGTH       0x0E
00256 
00257 // MAC address for this interface
00258 
00259 #ifndef ENC28J60_MAC0
00260 #define ENC28J60_MAC0 0x00
00261 #define ENC28J60_MAC1 0x03
00262 #define ENC28J60_MAC2 0x6f
00263 #define ENC28J60_MAC3 0x55
00264 #define ENC28J60_MAC4 0x1c
00265 #define ENC28J60_MAC5 0xc2
00266 #endif
00267 
00268 // functions
00269 // setup ports for I/O
00270 
00272 void nicSetMacAddress( void );
00274 unsigned char enc28j60ReadOp( unsigned char op,  unsigned char address);
00276 void enc28j60WriteOp( unsigned char op,  unsigned char address,  unsigned char data);
00278 void enc28j60ReadBuffer( unsigned int len,  unsigned char* data);
00280 void enc28j60WriteBuffer( unsigned int len,  unsigned char* data);
00282 void enc28j60SetBank( unsigned char address);
00284 unsigned char enc28j60Read( unsigned char address);
00286 void enc28j60Write( unsigned char address, unsigned char data);
00288 unsigned int enc28j60PhyRead( unsigned char address);
00290 void enc28j60PhyWrite( unsigned char address,  unsigned int data);
00291 
00293 void enc28j60Init(void);
00294 
00299 void enc28j60PacketSend(unsigned int len, unsigned char* packet);
00300 
00307 unsigned int enc28j60PacketReceive(unsigned int maxlen, unsigned char* packet);
00308 
00309 unsigned int enc28j60PacketReceiveLenght( void );
00310 
00311 #endif
00312 

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