library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_logic_unsigned.all;
use IEEE.STD_logic_arith.all;

entity usb_control is
 generic(buswidth : natural := 8);
 Port (usb_clk : in STD_LOGIC;
       TXE : in STD_LOGIC;
       RXF : in STD_LOGIC;
       data_TX : in STD_LOGIC_VECTOR(buswidth-1 downto 0);
       rdempty : in std_logic;
       rdreq : out STD_LOGIC;
       WR : out STD_LOGIC;
       OE : out STD_LOGIC;
       RD : out STD_LOGIC;
       SIWU : out STD_LOGIC;
       usb_data : inout std_logic_vector(buswidth-1 downto 0));
end usb_control;


architecture Behavioral of usb_control is
signal ft2232_wait : integer range 0 to 1 := 0;
signal bus_oe_mode : integer range 0 to 3 := 0;
signal state_tx : std_logic;
signal state_rx : std_logic;
signal tx : std_logic;
signal rx : std_logic;
signal data_rx : std_logic_vector(buswidth-1 downto 0) := x"00";

begin

SIWU <= '1'; --If not used tie this pin to Vcc

tx <= '1' when TXE = '0' and ft2232_wait = 1 and rdempty = '0' else '0';
rx <= '1' when RXF = '0' else '0';
 
state_tx<= '1' when tx_ = '1' else '0';
state_rx <= '1' when bus_oe_mode > 1 and rx = '1' and tx = '0' else '0';

rdreq <= '1' when state_tx = '1' else '0';

WR <= '0' when state_tx = '1' else '1';
RD <= '0' when state_rx = '1' else '1';
OE <= '0' when bus_oe_mode > 0 else '1';

usb_data <= data_tx when state_tx = '1' else (others => 'Z');
data_rx <= usb_data when bus_oe_mode > 0 and RXF = '0';


process
 begin
 wait until rising_edge(usb_clk); 
 if (tx = '0' or rx = '1') then
  bus_oe_mode <= 0;
  if (TXE = '0') then
   ft2232_wait <= ft2232_wait + 1;
  else
   ft2232_wait <= 0;
  end if;
 elsif (rx = '1') then
  ft2232_wait <= 0;
  if (bus_oe_mode < 3) then
   bus_oe_mode <= bus_oe_mode + 1;
  end if;
 end if;
end process;


end Behavioral;