mig_36_1 Project Status (12/18/2012 - 11:17:18) | |||
Project File: | mig_36_1.xise | Parser Errors: | No Errors |
Module Name: | mig_36_1 | Implementation State: | Mapped (Failed) |
Target Device: | xc6slx16-2csg324 |
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X 2 Errors (2 new) |
Product Version: | ISE 14.3 |
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367 Warnings (367 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary | [-] |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Di 18. Dez 11:15:05 2012 | 0 | 366 Warnings (366 new) | 104 Infos (104 new) | |
Translation Report | Current | Di 18. Dez 11:17:05 2012 | 0 | 1 Warning (1 new) | 4 Infos (0 new) | |
Map Report | Current | Di 18. Dez 11:17:16 2012 | X 2 Errors (2 new) | 0 | 6 Infos (3 new) | |
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |