Project Report (generated at 22.12.2012 21:56:10)
Copyright 2012 SOFDIO Systems. All rights reserved
| Project Name |
uptime_wb1 |
| Location |
C:\Users\HOLGER\Documents\Code Patata\Project\VERILOG_1 |
| Total Files |
1 |
| VHDL Files |
0 |
| Verilog HDL Files |
1 |
| Total Lines |
170 |
| Lines for Active Code |
161 |
| Total Symbols |
23 |
| Modules |
2 |
| Instances |
2 |
| Ports |
9 |
| Signals |
10 |
| Deepest Level of Instances |
2 |
| File |
Size |
Total Lines |
Active Code |
| C:\Users\HOLGER\Documents\Code Patata\Project\VERILOG_1\uptime_wb_1.v |
8294 |
170 |
161 |
| Symbol |
Type |
Definition |
References |
| CLK_IN_HZ |
Statement |
1 |
0 |
| DIVISOR_62_5 |
Statement |
1 |
1 |
| clk_ii |
Port |
1 |
3 |
| dat_o_reg_single_4 |
Object |
1 |
6 |
| hours_cur_work_reg_02 |
Object |
1 |
4 |
| minutes_cur_work_reg_01 |
Object |
1 |
6 |
| rst_i |
Port |
1 |
8 |
| sec_clock_irq_trigger |
Object |
1 |
4 |
| seconds_cur_work_reg_00 |
Object |
1 |
6 |
| shaddow_00_seconds_reg |
Object |
1 |
4 |
| shaddow_01_minutes_reg |
Object |
1 |
3 |
| shaddow_02_hours_reg |
Object |
1 |
3 |
| tick_clock_count |
Object |
1 |
5 |
| wb_Read_import_via_r4 |
Statement |
1 |
2 |
| wb_Write_export_via_rNULL |
Statement |
1 |
3 |
| wb_ack_o |
Port |
1 |
1 |
| wb_adr_ii |
Port |
1 |
1 |
| wb_cyc_i |
Port |
1 |
1 |
| wb_dat_i_fabi |
Port |
1 |
0 |
| wb_dat_single_as_sampler_o |
Port |
1 |
1 |
| wb_stb_i |
Port |
1 |
2 |
| wb_tigger_flg |
Object |
1 |
5 |
| wb_we_i |
Port |
1 |
1 |
22.12.2012 21:51:01
Version:v1
Author: HOLGER
Comment:
uptime_WB
File List: