library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity analoginput is
    Port ( 	
				  RESET : in STD_LOGIC;
				
				  IN_REFRESH_DIRECT : in  STD_LOGIC;
				  IN_REFRESH_MEAN  : in  STD_LOGIC;
				  IN_ADR : in  STD_LOGIC_VECTOR (3 downto 0);
				  IN_SET_ADR : in  STD_LOGIC;
				  OUT_DATA : out  STD_LOGIC_VECTOR (13 downto 0);
			  --ADC
				  ADC1_DATA : in  STD_LOGIC_VECTOR (13 downto 0);
				  ADC1_CLK : out  STD_LOGIC;
				  ADC2_DATA : in  STD_LOGIC_VECTOR (13 downto 0);
				  ADC2_CLK : out  STD_LOGIC;
	
			  --GLOBAL
				  CLK : in  STD_LOGIC);
end analoginput;


architecture Behavioral of analoginput is
	--Signal zum Takten
		type ZUSTAENDE is (Z0, Z1, Z2, Z3, Z4, Z5); -- Aufzählungstyp
		signal ZUSTAND, FOLGEZUSTAND: ZUSTAENDE;
	--SIGNAL ZUR FLANKENERKENNUNG VON IN_SET_ADR
		signal SIG_SET_ADR : STD_LOGIC_VECTOR (1 downto 0) := "01" ;
	--SIGNAL ZUR FLANKENERKENNUNG VON IN_REFRESH_xxxxx
		signal SIG_IN_REFRESH : STD_LOGIC_VECTOR (3 downto 0) := "0000" ;
	--FF für ADRESSE
		signal SIG_ADR : STD_LOGIC_VECTOR (3 downto 0) := "0000" ;
	--FF für OUT_DATA
		signal SIG_OUT_DATA : STD_LOGIC_VECTOR (13 downto 0) := "00000000000000" ;
	--FF für ADC_DATA
		signal SIG_ADC1_DATA : STD_LOGIC_VECTOR (13 downto 0) := "00000000000000" ;
		signal SIG_ADC2_DATA : STD_LOGIC_VECTOR (13 downto 0) := "00000000000000" ;
	--SIGNALE für Mittelung


		signal SIG_ADC_MEAN_SUM 	: STD_LOGIC_VECTOR (15 downto 0) :=  "0000000000000000" ; 
		signal SIG_ADC_MEAN		: STD_LOGIC_VECTOR (13 downto 0) :=  "00000000000000" ;  
		signal SIG_ADC_MEAN_VALUE_1 	: STD_LOGIC_VECTOR (13 downto 0) :=  "00000000000000" ;
		signal SIG_ADC_MEAN_VALUE_2 	: STD_LOGIC_VECTOR (13 downto 0) :=  "00000000000000" ;
		signal SIG_ADC_MEAN_VALUE_3 	: STD_LOGIC_VECTOR (13 downto 0) :=  "00000000000000" ;
		signal SIG_ADC_MEAN_VALUE_4 	: STD_LOGIC_VECTOR (13 downto 0) :=  "00000000000000" ;

begin


PROCESS_adc_zustand: process(CLK,RESET)
begin
	if rising_edge(CLK) then
		if RESET = '1' then
			ZUSTAND <= Z0;
		else
			ZUSTAND <= FOLGEZUSTAND;
		end if;
	end if;
end process;

PROCESS_adc: process(CLK)
begin
	if rising_edge(CLK) then
		CASE ZUSTAND IS
		 WHEN  z0  =>  
						ADC1_CLK <= '1';
						ADC2_CLK <= '1';
						SIG_ADC1_DATA <= SIG_ADC1_DATA;
						SIG_ADC2_DATA <= SIG_ADC2_DATA;					

							SIG_ADC_MEAN <= SIG_ADC_MEAN_SUM(15 downto 2) ;	--zuweisung mean 
							SIG_ADC_MEAN_SUM <= SIG_ADC_MEAN_SUM ;
							SIG_ADC_MEAN_VALUE_1 <= SIG_ADC_MEAN_VALUE_1;	--begin: speicher
							SIG_ADC_MEAN_VALUE_2 <= SIG_ADC_MEAN_VALUE_2;
							SIG_ADC_MEAN_VALUE_3 <= SIG_ADC_MEAN_VALUE_3;
							SIG_ADC_MEAN_VALUE_4 <= SIG_ADC_MEAN_VALUE_4; --end: speicher

						FOLGEZUSTAND <= z1;
		 WHEN  z1  =>  
						ADC1_CLK <= '1';
						ADC2_CLK <= '1';
						SIG_ADC1_DATA <= SIG_ADC1_DATA;
						SIG_ADC2_DATA <= SIG_ADC2_DATA;
							
							SIG_ADC_MEAN <= SIG_ADC_MEAN;
							SIG_ADC_MEAN_SUM <= STD_LOGIC_VECTOR(unsigned(SIG_ADC_MEAN_SUM) - unsigned(('0' & '0' & SIG_ADC_MEAN_VALUE_4))) ;				--Subtrahiere letzten Wert
							SIG_ADC_MEAN_VALUE_1 <= SIG_ADC_MEAN_VALUE_1;	--begin: speicher
							SIG_ADC_MEAN_VALUE_2 <= SIG_ADC_MEAN_VALUE_2;
							SIG_ADC_MEAN_VALUE_3 <= SIG_ADC_MEAN_VALUE_3;
							SIG_ADC_MEAN_VALUE_4 <= SIG_ADC_MEAN_VALUE_4; --end: speicher
							
						FOLGEZUSTAND <= z2;
		 WHEN  z2  =>  
						ADC1_CLK <= '1';
						ADC2_CLK <= '1';
						SIG_ADC1_DATA <= SIG_ADC1_DATA;
						SIG_ADC2_DATA <= SIG_ADC2_DATA;
						
							SIG_ADC_MEAN <= SIG_ADC_MEAN;
							SIG_ADC_MEAN_SUM <= SIG_ADC_MEAN_SUM;
							SIG_ADC_MEAN_VALUE_1 <= SIG_ADC_MEAN_VALUE_1;	--begin: speicher
							SIG_ADC_MEAN_VALUE_2 <= SIG_ADC_MEAN_VALUE_2;
							SIG_ADC_MEAN_VALUE_3 <= SIG_ADC_MEAN_VALUE_3;
							SIG_ADC_MEAN_VALUE_4 <= SIG_ADC_MEAN_VALUE_4; --end: speicher
							
						FOLGEZUSTAND <= z3;
		 WHEN  z3  =>  
						ADC1_CLK <= '0';
						ADC2_CLK <= '0';
						SIG_ADC1_DATA <= SIG_ADC1_DATA;
						SIG_ADC2_DATA <= SIG_ADC2_DATA;
								
							SIG_ADC_MEAN <= SIG_ADC_MEAN;
							SIG_ADC_MEAN_SUM <= SIG_ADC_MEAN_SUM;
							SIG_ADC_MEAN_VALUE_1 <= SIG_ADC_MEAN_VALUE_1;	--begin: speicher
							SIG_ADC_MEAN_VALUE_2 <= SIG_ADC_MEAN_VALUE_2;
							SIG_ADC_MEAN_VALUE_3 <= SIG_ADC_MEAN_VALUE_3;
							SIG_ADC_MEAN_VALUE_4 <= SIG_ADC_MEAN_VALUE_4; --end: speicher
							
						FOLGEZUSTAND <= z4;
		 WHEN  z4  =>  --Hier ist die Zuweisung
						ADC1_CLK <= '0';
						ADC2_CLK <= '0';
						SIG_ADC1_DATA <= (not ADC1_DATA(13) & ADC1_DATA(12 downto 0));
						SIG_ADC2_DATA <= (not ADC2_DATA(13) & ADC2_DATA(12 downto 0));

							SIG_ADC_MEAN <= SIG_ADC_MEAN;
							SIG_ADC_MEAN_SUM <= SIG_ADC_MEAN_SUM;
							if SIG_ADR(3) = '1' then	--wenn > 7 dann ADC2						--begin: speicher
								SIG_ADC_MEAN_VALUE_1 <= ( not ADC2_DATA(13) & ADC2_DATA(12 downto 0));	
							else
								SIG_ADC_MEAN_VALUE_1 <= ( not ADC1_DATA(13) & ADC1_DATA(12 downto 0));	
							end if;
							SIG_ADC_MEAN_VALUE_2 <= SIG_ADC_MEAN_VALUE_1;
							SIG_ADC_MEAN_VALUE_3 <= SIG_ADC_MEAN_VALUE_2;
							SIG_ADC_MEAN_VALUE_4 <= SIG_ADC_MEAN_VALUE_3; --end: speicher

						FOLGEZUSTAND <= z5;
		 WHEN  z5  =>  
						ADC1_CLK <= '0';
						ADC2_CLK <= '0';
						SIG_ADC1_DATA <= SIG_ADC1_DATA;
						SIG_ADC2_DATA <= SIG_ADC2_DATA;
							
							SIG_ADC_MEAN <= SIG_ADC_MEAN;
							SIG_ADC_MEAN_SUM <= STD_LOGIC_VECTOR(unsigned(SIG_ADC_MEAN_SUM) + unsigned(('0' & '0' & SIG_ADC_MEAN_VALUE_1))) ;			---    addiere neuen Wert
							SIG_ADC_MEAN_VALUE_1 <= SIG_ADC_MEAN_VALUE_1;	--begin: speicher
							SIG_ADC_MEAN_VALUE_2 <= SIG_ADC_MEAN_VALUE_2;
							SIG_ADC_MEAN_VALUE_3 <= SIG_ADC_MEAN_VALUE_3;
							SIG_ADC_MEAN_VALUE_4 <= SIG_ADC_MEAN_VALUE_4; --end: speicher
							
						FOLGEZUSTAND <= z0;							
	  END CASE;
	end if;
end process;







--IN_REFRESH GIBT LETZTEN GEMESSENEN WERT VON CHANNEL IN_ADR AUS (UNGEMITTELT ODER GEMITTELT)
PROCESS_READ_in_refresh : process(CLK,RESET)
begin
	if rising_edge(CLK) then
		if RESET = '1' then
			SIG_IN_REFRESH <= "0000";
		else
			SIG_IN_REFRESH(0) <= IN_REFRESH_DIRECT;
			SIG_IN_REFRESH(1) <= SIG_IN_REFRESH(0);
			SIG_IN_REFRESH(2) <= IN_REFRESH_MEAN;
			SIG_IN_REFRESH(3) <= SIG_IN_REFRESH(2);
		end if;
	OUT_DATA <= SIG_OUT_DATA;
	end if;
end process;


PROCESS_in_refresh : process(CLK,RESET)
begin
	if rising_edge(CLK) then
		if RESET = '1' then
			SIG_OUT_DATA <= "00000000000000";
		else	
			CASE SIG_IN_REFRESH IS
					WHEN "0001" =>			--REFRESH DIRECT
								if SIG_ADR(3) = '1' then	--wenn > 7 dann ADC2 
									SIG_OUT_DATA <= SIG_ADC2_DATA;
								else								--ansonsten ADC1
									SIG_OUT_DATA <= SIG_ADC1_DATA;
								end if;
					WHEN "0100" =>			--REFRESH MEAN												--xxxx
								SIG_OUT_DATA <= SIG_ADC_MEAN;
					WHEN OTHERS =>
						SIG_OUT_DATA <= SIG_OUT_DATA;
			END CASE;
		end if;
	end if;
end process;

end Behavioral;