Version 4
SHEET 1 1832 5332
WIRE -160 -16 -368 -16
WIRE -16 -16 -160 -16
WIRE 208 -16 -16 -16
WIRE 304 -16 208 -16
WIRE -160 48 -160 -16
WIRE -368 96 -368 64
WIRE 208 160 208 -16
WIRE 176 176 112 176
WIRE 384 192 240 192
WIRE -320 208 -400 208
WIRE -160 208 -160 128
WIRE -160 208 -256 208
WIRE 176 208 -160 208
WIRE 384 208 384 192
WIRE -400 224 -400 208
WIRE 112 288 112 176
WIRE 384 288 112 288
WIRE -160 304 -160 208
WIRE 384 304 384 288
WIRE -400 416 -400 304
WIRE -160 416 -160 384
WIRE 208 416 208 224
WIRE -16 496 -16 -16
WIRE 384 528 384 384
WIRE 384 528 208 528
WIRE 304 576 304 -16
WIRE 208 592 208 528
WIRE 272 592 208 592
WIRE 384 608 384 528
WIRE 384 608 336 608
WIRE -16 624 -16 576
WIRE 272 624 -16 624
WIRE -16 672 -16 624
WIRE -16 784 -16 752
WIRE 304 800 304 640
FLAG -368 96 0
FLAG 208 416 0
FLAG -400 416 0
FLAG -160 416 0
FLAG -16 784 0
FLAG 304 800 0
SYMBOL voltage -400 208 R0
WINDOW 3 -177 103 Left 2
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR Value SINE(1 0.5 1k)
SYMATTR InstName V1
SYMBOL voltage -368 -32 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V2
SYMATTR Value 5
SYMBOL res 368 192 R0
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL res 368 288 R0
SYMATTR InstName R2
SYMATTR Value 30k
SYMBOL Opamps\\opamp2 208 128 R0
SYMATTR InstName U1
SYMATTR Value MCP6401
SYMBOL cap -256 192 R90
WINDOW 0 0 32 VBottom 2
WINDOW 3 32 32 VTop 2
SYMATTR InstName C1
SYMATTR Value 100n
SYMBOL res -176 32 R0
SYMATTR InstName R3
SYMATTR Value 50k
SYMBOL res -176 288 R0
SYMATTR InstName R4
SYMATTR Value 50k
SYMBOL Opamps\\opamp2 304 544 R0
SYMATTR InstName U2
SYMATTR Value MCP6401
SYMBOL res -32 480 R0
SYMATTR InstName R5
SYMATTR Value 50k
SYMBOL res -32 656 R0
SYMATTR InstName R6
SYMATTR Value 50k
TEXT -568 616 Left 2 !.tran 10ms
TEXT 544 248 Left 2 !.SUBCKT MCP6401 1 2 3 4 5\n*               | | | | |\n*               | | | | Output\n*               | | | Negative Supply\n*               | | Positive Supply\n*               | Inverting Input\n*               Non-inverting Input\n*\n********************************************************************************\n* Software License Agreement                                                   *\n*                                                                              *\n* The software supplied herewith by Microchip Technology Incorporated (the     *\n* 'Company') is intended and supplied to you, the Company's customer, for use  *\n* soley and exclusively on Microchip products.                                 *\n*                                                                              *\n* The software is owned by the Company and/or its supplier, and is protected   *\n* under applicable copyright laws. All rights are reserved. Any use in         *\n* violation of the foregoing restrictions may subject the user to criminal     *\n* sanctions under applicable laws, as well as to civil liability for the       *\n* breach of the terms and conditions of this license.                          *\n*                                                                              *\n* THIS SOFTWARE IS PROVIDED IN AN 'AS IS' CONDITION. NO WARRANTIES, WHETHER    *\n* EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED        *\n* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO  *\n* THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR    *\n* SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.     *\n********************************************************************************\n*\n* The following op-amps are covered by this model:\n*      MCP6401, MCP6401R, MCP6401U, MCP6402, MCP6404, MCP6406, MCP6407, MCP6409\n*\n* Date of model creation: 10/10/2010\n* Level of Model Creator: 3.0\n*\n* Revision History:\n*      REV A: 10-Oct-10\n*      REV B: 09-Jul-12, Added MCP6406, MCP6407, MCP6409\n*       \n* Recommendations:\n*      Use PSPICE (or SPICE 2G6; other simulators may require translation)\n*      For a quick, effective design, use a combination of: data sheet\n*            specs, bench testing, and simulations with this macromodel\n*      For high impedance circuits, set GMIN=100F in the .OPTIONS statement\n*\n* Supported:\n*      Typical performance for temperature range (-40 to 125) degrees Celsius\n*      DC, AC, Transient, and Noise analyses.\n*      Most specs, including: offsets, DC PSRR, DC CMRR, input impedance,\n*            open loop gain, voltage ranges, supply current, ... , etc.\n*      Temperature effects for Ibias, Iquiescent, Iout short circuit \n*            current, Vsat on both rails, Slew Rate vs. Temp and P.S.\n*\n* Not Supported:\n*      Some Variation in specs vs. Power Supply Voltage\n*      Vos distribution, Ib distribution for Monte Carlo\n*      Distortion (detailed non-linear behavior)\n*      Some Temperature analysis\n*      Process variation\n*      Behavior outside normal operating region\n*\n*\n* Input Stage\nV10  3 10 -400M\nR10 10 11 1.00MEG\nR11 10 12 1.00MEG\nG10 10 11 10 11 100U\nG11 10 12 10 12 100U\nC11 11 12 397E-15\nC12  1  0 6P\nE12 71 14 POLY(6) 20 0 21 0 22 0 23 0 26 0 27 0   4.5M 11.7 11.7 3.6 3.6 1 1\nG12 1 0 62 0 1m\nG13 1 2 63 0 1u\nM12 11 14 15 15 NMI \nM14 12 2 15 15 NMI \nG14 2 0 62 0 1m\nC14  2  0 6P\nC13 1 2 3P\nI15 15 4 20.0U\nV16 16 4 -200M\nGD16 16 1 TABLE {V(16,1)} ((-100,-1p)(0,0)(1m,1u)(2m,1m)) \nV13 3 13 -200M\nGD13 2 13 TABLE {V(2,13)} ((-100,-1p)(0,0)(1m,1u)(2m,1m)) \nR71  1  0 20.0E12\nR72  2  0 20.0E12\nR73  1  2 20.0E12\n*\n* Noise, PSRR, and CMRR\nI20 21 20 423U\nD20 20  0 DN1\nD21  0 21 DN1\nI22 22 23 1N\nR22 22 0  1k\nR23  0 23 1k\nG26  0 26 POLY(2) 3 0 4 0   0.00 -79.4U -100U\nR26 26  0 1\nG27  0 27 POLY(2) 1 0 2 0  -847U 40U 40U\nR27 27  0 1\n*\n* Open Loop Gain, Slew Rate\nG30  0 30 12 11 1\nR30 30  0 1.00K\nG31 0 31 3 4 3.9\nI31 0 31 DC 51.5\nR31 31  0 1 TC=3.03M,2.40U\nGD31 30 0 TABLE {V(30,31)} ((-100,-1n)(0,0)(1m,0.1)(2m,2))\nCD31 31 30 2p\nG32 32 0 3 4 2.2\nI32 32 0 DC 93\nR32 32  0 1 TC=2.22M,-2.72U\nGD32 0 30 TABLE {V(30,32)} ((-2m,2)(-1m,0.1)(0,0)(100,-1n))\nCD32 32 30 2p\nG33  0 33 30 0 1m\nR33  33 0 1K\nG34  0 34 33 0 0.325\nR34  34 0 1K\nC34  34 0 50.3U\nG37  0 37 34 0 1m\nR37  37 0 1K\nC37  37 0 63.6P\nG38  0 38 37 0 1m\nR38  39 0 1K\nL38  38 39 79.5U\nE38  35 0 38 0 1\nG35 33 0 TABLE {V(35,3)} ((-1,-1n)(0,0)(90,1n))(91,1))\nG36 33 0 TABLE {V(35,4)} ((-91,-1)((-90,-1n)(0,0)(1,1n))\n*\n* Output Stage\nR80 50 0 100MEG\nG50 0 50 57 96 2\nR58 57  96 0.50\nR57 57  0 1.2K\nC58  5  0 2.00P\nG57  0 57 POLY(3) 3 0 4 0 35 0 0 312U 416U 833U\nGD55 55 57 TABLE {V(55,57)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))\nCD55 55 57 2p\nCD56 57 56 2p\nGD56 57 56 TABLE {V(57,56)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n))\nE55 55  0 POLY(2) 3 0 51 0 2M 1 -54M \nE56 56  0 POLY(2) 4 0 52 0 1.2M 1 -50M \nR51 51 0 1k\nR52 52 0 1k\nGD51 50 51 TABLE {V(50,51)} ((-10,-1n)(0,0)(1m,1m)(2m,1))\nGD52 50 52 TABLE {V(50,52)}  ((-2m,-1)(-1m,-1m)(0,0)(10,1n))\nCD51 50 52 2p\nCD52 50 51 2p\nG53  3  0 POLY(1) 51 0  -20.0U 1M\nG54  0  4 POLY(1) 52 0  -20.0U -1M\n*\n* Current Limit\nG99 96 5 99 0 1\nR98 0 98 1 TC=-3.71M,8.17U\nG97 0 98 TABLE { V(96,5) } ((-12.0,-7.00M)(-1.00M,-6.93M)(0,0)(1.00M,6.93M)(12.0,7.00M))\nE97 99 0 VALUE { V(98)*((V(3)-V(4))*428M + 142M)}\nD98 4 5 DESD\nD99 5 3 DESD\n*\n* Temperature / Voltage Sensitive IQuiscent\nR61 0 61 1 TC=2.24M,3.12U\nG61 3 4 61 0 1\nG60 0 61 TABLE {V(3,4)} \n+ ((0,0)(800M,440N)(850M,3.00U)(1.3,40.0U)\n+ (1.4,42.0U)(5.00,46.0U)(7.00,50.0U))\n*\n* Temperature Sensitive offset voltage\nI73 0 70 DC 1uA\nR74 0 70 1 TC=2.00\nE75 1 71 70 0 1 \n*\n* Temp Sensistive IBias\nI62 0 62 DC 1uA\nR62 0 62 REXP  1.1m\n*\n* Temp Sensistive Offset IBias\nI63 0 63 DC 1uA\nR63 0 63 1.1 TC=30.4M,454U\n*\n* Models\n.MODEL NMI NMOS(L=2.00U W=50.0U KP=20.0U LEVEL=1 )\n.MODEL DESD  D   N=1 IS=1.00E-15\n.MODEL DN1 D   IS=1P KF=146E-18 AF=1\n.MODEL REXP  RES TCE= 6.6\n.ENDS MCP6401