Xilinx Design Summary

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	39	3,072	1%
Number of 4 input LUTs	106	3,072	3%
Logic Distribution
Number of occupied Slices	59	1,536	3%
Number of Slices containing only related logic	59	59	100%
Number of Slices containing unrelated logic	0	59	0%
Total Number 4 input LUTs	109	3,072	3%
Number used as logic	106
Number used as a route-thru	3
Number of bonded IOBs	23	172	13%
IOB Flip Flops	1
Number of GCLKs	1	16	6%
Total equivalent gate count for design	983
Additional JTAG gate count for IOBs	1,104

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met