top Project Status (05/15/2013 - 10:33:11) | |||
Project File: | MIG_STANDALONE.xise | Parser Errors: | No Errors |
Module Name: | top | Implementation State: | Translated (Failed) |
Target Device: | xc6slx45-2fgg484 |
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X 4 Errors (4 new) |
Product Version: | ISE 14.4 |
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1076 Warnings (15 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 469 | 54576 | 0% | |
Number of Slice LUTs | 770 | 27288 | 2% | |
Number of fully used LUT-FF pairs | 371 | 868 | 42% | |
Number of bonded IOBs | 214 | 316 | 67% | |
Number of BUFG/BUFGCTRLs | 3 | 16 | 18% | |
Number of PLL_ADVs | 1 | 4 | 25% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Mi 15. Mai 10:21:58 2013 | 0 | 1071 Warnings (12 new) | 184 Infos (0 new) | |
Translation Report | Current | Mi 15. Mai 10:33:09 2013 | X 4 Errors (4 new) | 5 Warnings (3 new) | 0 | |
Map Report | Out of Date | Mi 15. Mai 10:28:36 2013 | X 3 Errors (2 new) | 0 | 8 Infos (1 new) | |
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |