top Project Status (05/15/2013 - 10:33:11)
Project File: MIG_STANDALONE.xise Parser Errors: No Errors
Module Name: top Implementation State: Translated (Failed)
Target Device: xc6slx45-2fgg484
  • Errors:
X 4 Errors (4 new)
Product Version:ISE 14.4
  • Warnings:
1076 Warnings (15 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 469 54576 0%
Number of Slice LUTs 770 27288 2%
Number of fully used LUT-FF pairs 371 868 42%
Number of bonded IOBs 214 316 67%
Number of BUFG/BUFGCTRLs 3 16 18%
Number of PLL_ADVs 1 4 25%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentMi 15. Mai 10:21:58 201301071 Warnings (12 new)184 Infos (0 new)
Translation ReportCurrentMi 15. Mai 10:33:09 2013X 4 Errors (4 new)5 Warnings (3 new)0
Map ReportOut of DateMi 15. Mai 10:28:36 2013X 3 Errors (2 new)08 Infos (1 new)
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 05/15/2013 - 10:47:25