top Project Status (05/14/2013 - 15:46:04)
Project File: MIG_VFIFO.xise Parser Errors: No Errors
Module Name: top Implementation State: Mapped (Failed)
Target Device: xc6slx45-2fgg484
  • Errors:
X 4 Errors (3 new)
Product Version:ISE 14.4
  • Warnings:
3059 Warnings (12 new, 0 filtered)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary [-]
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentDi 14. Mai 15:03:59 201303057 Warnings (12 new, 0 filtered)346 Infos (0 new, 0 filtered)
Translation ReportCurrentDi 14. Mai 15:45:03 201302 Warnings (0 new, 0 filtered)1 Info (0 new, 0 filtered)
Map ReportCurrentDi 14. Mai 15:46:02 2013X 4 Errors (3 new)08 Infos (1 new, 0 filtered)
Place and Route ReportOut of DateMo 13. Mai 13:56:31 2013016 Warnings (16 new, 0 filtered)3 Infos (0 new, 0 filtered)
Power Report     
Post-PAR Static Timing ReportOut of DateMo 13. Mai 13:56:44 2013004 Infos (0 new, 0 filtered)
Bitgen ReportOut of DateMo 13. Mai 13:57:12 2013016 Warnings (16 new, 0 filtered)1 Info (1 new, 0 filtered)
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateDi 14. Mai 14:31:24 2013
WebTalk ReportOut of DateMo 13. Mai 13:57:14 2013
WebTalk Log FileOut of DateMo 13. Mai 13:57:16 2013

Date Generated: 05/15/2013 - 11:02:11