TOP_DESIGN_01 Project Status
Project File:	TEST_MEM_CONTR_VH-Modell.xise	Parser Errors:
Module Name:	TOP_DESIGN_01	Implementation State:	New
Target Device:	xc5vlx155t-1ff1136	Errors:
Product Version:	ISE 14.5	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:		Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 07/05/2013 - 12:00:21