### FPGA ###
Export Time: 2013-08-27 10:52:09								
Port 0								
Aardvark HW_Version: 3.00 FW_Version: 3.50								
								
Time						Module	Read/Write	Master/Slave	Features	Bitrate	Address	Length	Data
2013-08-27 10:44:15.642"	SPI						S				RSM						SPI 	Slave Enabled
27.08.2013 10:51			SPI			R			S				RSML					38		50 80 11 07 E8 00 81 21 02 40 00 82 20 13 88 00 83 58 40 C2 00 84 00 00 0A 00 85 40 00 00 00 86 C0 C0 60 00 70 03
27.08.2013 10:51			SPI			W			S				RSML					38		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00



### uC ###
Export Time: 2013-08-22 11:06:50								
Port 0								
Aardvark HW_Version: 3.00 FW_Version: 3.50								
								
Time						Module	Read/Write	Master/Slave	Features	Bitrate	Address	Length	Data
2013-08-22 11:05:36.309"	SPI						S				RSM						SPI 	Slave Enabled
22.08.2013 11:05			SPI			R			S				RSML					38		50 80 11 07 E8 00 81 21 02 40 00 82 20 13 88 00 83 58 40 C2 00 84 00 00 0A 00 85 40 00 00 00 86 C0 C0 60 00 70 03
22.08.2013 11:05			SPI			W			S				RSML					38		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00