call Timer1_init main: call Berechnung2 . . . . . rjmp main Timer1_init: ldi temp1,0b00000000 ;normal operation (overflow) sts TCCR1A,temp1 ldi temp1,0b00000011 ;prescaler /64 sts TCCR1B,temp1 ldi temp,0b00000001 sts TIMSK1,temp ret timer1_overflow: in twitest,sreg ; SREG sichern push twitest push twitemp push temp push temp3 push temp2 push temp1 ; temp 1 sichern push berechnung push DATA_EMPFANG_1 push DATA_EMPFANG_2 push schiebereg lds temp1,Kapzustand ldi temp2,100 mul temp1,temp2 mov temp2,r0 mov temp3,r1 sts DIVIDENT_L_L_SPG,temp2 sts DIVIDENT_L_H_SPG,temp3 ldi temp,0x00 sts DIVIDENT_H_L_SPG,temp sts DIVIDENT_H_H_SPG,temp lds temp,Kapreg sts DIVISOR_L_L_SPG,temp ldi temp,0x00 sts DIVISOR_L_H_SPG,temp ldi temp,0x00 sts DIVISOR_H_L_SPG,temp sts DIVISOR_H_H_SPG,temp call DIVISION_32_32_SPG lds temp1,ERGEBNIS_L_L_SPG lds temp3,ERGEBNIS_L_H_SPG pop schiebereg pop DATA_EMPFANG_2 pop DATA_EMPFANG_1 pop berechnung pop temp1 pop temp2 pop temp3 pop temp pop twitemp pop twitest out sreg,twitest ; sreg wieder herstellen reti ; das wars. Interrupt ist fertig Berechnung2: call ADCstart_voltage ldi temp1,HIGH(10000) sts m1M,temp1 ldi temp1,LOW(10000) sts m1L,temp1 sts m2M,temp3 ;m2M laden mit ADCH sts m2L,temp2 ;m2L laden mit ADCL call Multiplikation_16_16 lds temp,Res1 sts DIVIDENT_L_L_SPG,temp lds temp,Res2 sts DIVIDENT_L_H_SPG,temp lds temp,Res3 sts DIVIDENT_H_L_SPG,temp ldi temp,0x00 sts DIVIDENT_H_H_SPG,temp ldi temp,0x00 sts DIVISOR_L_L_SPG,temp ldi temp,0x04 sts DIVISOR_L_H_SPG,temp ldi temp,0x00 sts DIVISOR_H_L_SPG,temp sts DIVISOR_H_H_SPG,temp call DIVISION_32_32_SPG lds temp2,ERGEBNIS_L_L_SPG lds temp3,ERGEBNIS_L_H_SPG sts Gesamtspannung_L,temp2 sts Gesamtspannung_H,temp3 ret DIVISION_32_32_SPG: ; INITIALISIERUNG ldi temp1,0 sts ERGEBNIS_L_L_SPG,temp1 sts ERGEBNIS_L_H_SPG,temp1 sts ERGEBNIS_H_L_SPG,temp1 sts ERGEBNIS_H_H_SPG,temp1 ldi temp1,1 sts ZW_L_L_SPG,temp1 ;ldi ZW_L_L,1 ; +1 ldi temp1,0 sts ZW_L_H_SPG,temp1 sts ZW_H_L_SPG,temp1 sts ZW_H_H_SPG,temp1 ; FEHLERPRÜFUNG lds temp1,DIVISOR_L_L_SPG tst temp1 brne DIVISION_32_32_LINKS_SPG lds temp1,DIVISOR_L_H_SPG tst temp1 brne DIVISION_32_32_LINKS_SPG lds temp1,DIVISOR_H_L_SPG tst temp1 brne DIVISION_32_32_LINKS_SPG lds temp1,DIVISOR_H_H_SPG tst temp1 brne DIVISION_32_32_LINKS_SPG rjmp DIVISION_32_32_ERROR_SPG ; Divisor linksbündig DIVISION_32_32_LINKS_SPG: lds temp1,DIVISOR_H_H_SPG tst temp1 ; Linksbündig ? brmi DIVISION_32_32_START_SPG ; ja ==> SPRUNG lds temp1,ZW_L_L_SPG LSL temp1 sts ZW_L_L_SPG,temp1 ;LSL ZW_L_L ; 1x links lds temp1,ZW_L_H_SPG ROL temp1 sts ZW_L_H_SPG,temp1 lds temp1,ZW_H_L_SPG ROL temp1 sts ZW_H_L_SPG,temp1 lds temp1,ZW_H_H_SPG ROL temp1 sts ZW_H_H_SPG,temp1 lds temp1,DIVISOR_L_L_SPG LSL temp1 sts DIVISOR_L_L_SPG,temp1 ;LSL ZW_L_L ; 1x links lds temp1,DIVISOR_L_H_SPG ROL temp1 sts DIVISOR_L_H_SPG,temp1 lds temp1,DIVISOR_H_L_SPG ROL temp1 sts DIVISOR_H_L_SPG,temp1 lds temp1,DIVISOR_H_H_SPG ROL temp1 sts DIVISOR_H_H_SPG,temp1 rjmp DIVISION_32_32_LINKS_SPG x122xx_SPG: jmp DIVISION_32_32_SCHIEBEN_SPG ; DIVISION START DIVISION_32_32_START_SPG: lds temp1,DIVIDENT_H_H_SPG lds temp,divisor_H_H_SPG cp temp1,temp ; DIVIDENT ">=" DIVISOR ? (H_H) brlo x122xx_SPG ; nein=> SPRUNG breq DIVISION_32_32__w_SPG brsh DIVISION_32_32_ADD_SUB_SPG DIVISION_32_32__w_SPG: lds temp1,DIVIDENT_H_L_SPG lds temp,divisor_H_L_SPG cp temp1,temp ; DIVIDENT ">=" DIVISOR ? (H_H) brlo x122xx_SPG ; nein=> SPRUNG breq DIVISION_32_32__ww_SPG brsh DIVISION_32_32_ADD_SUB_SPG DIVISION_32_32__ww_SPG: lds temp1,DIVIDENT_L_H_SPG lds temp,divisor_L_H_SPG cp temp1,temp ; DIVIDENT ">=" DIVISOR ? (H_H) brlo x122xx_SPG ; nein=> SPRUNG breq DIVISION_32_32__www_SPG brsh DIVISION_32_32_ADD_SUB_SPG DIVISION_32_32__www_SPG: lds temp1,DIVIDENT_L_L_SPG lds temp,divisor_L_L_SPG cp temp1,temp ; DIVIDENT ">=" DIVISOR ? (H_H) brlo x122xx_SPG ; nein=> SPRUNG ; ADDIEREN und SUBTRAHIEREN DIVISION_32_32_ADD_SUB_SPG: lds temp1,ERGEBNIS_L_L_SPG lds temp,ZW_L_L_SPG add temp1,temp sts ERGEBNIS_L_L_SPG,temp1 sts ZW_L_L_SPG,temp lds temp1,ERGEBNIS_L_H_SPG lds temp,ZW_L_H_SPG adc temp1,temp sts ERGEBNIS_L_H_SPG,temp1 sts ZW_L_H_SPG,temp lds temp1,ERGEBNIS_H_L_SPG lds temp,ZW_H_L_SPG adc temp1,temp sts ERGEBNIS_H_L_SPG,temp1 sts ZW_H_L_SPG,temp lds temp1,ERGEBNIS_H_H_SPG lds temp,ZW_H_H_SPG adc temp1,temp sts ERGEBNIS_H_H_SPG,temp1 sts ZW_H_H_SPG,temp lds temp1,DIVIDENT_L_L_SPG lds temp,divisor_L_L_SPG sub temp1,temp sts DIVIDENT_L_L_SPG,temp1 sts divisor_L_L_SPG,temp lds temp1,DIVIDENT_L_H_SPG lds temp,divisor_L_H_SPG sbc temp1,temp sts DIVIDENT_L_H_SPG,temp1 sts divisor_L_H_SPG,temp lds temp1,DIVIDENT_H_L_SPG lds temp,divisor_H_L_SPG sbc temp1,temp sts DIVIDENT_H_L_SPG,temp1 sts divisor_H_L_SPG,temp lds temp1,DIVIDENT_H_H_SPG lds temp,divisor_H_H_SPG sbc temp1,temp sts DIVIDENT_H_H_SPG,temp1 sts divisor_H_H_SPG,temp ; 1 x rechts schieben DIVISION_32_32_SCHIEBEN_SPG: lds temp1,DIVISOR_H_H_SPG lsr temp1 sts DIVISOR_H_H_SPG,temp1 lds temp1,DIVISOR_H_L_SPG ror temp1 sts DIVISOR_H_L_SPG,temp1 lds temp1,DIVISOR_L_H_SPG ror temp1 sts DIVISOR_L_H_SPG,temp1 lds temp1,DIVISOR_L_L_SPG ror temp1 sts DIVISOR_L_L_SPG,temp1 lds temp1,ZW_H_H_SPG lsr temp1 sts ZW_H_H_SPG,temp1 lds temp1,ZW_H_L_SPG ror temp1 sts ZW_H_L_SPG,temp1 lds temp1,ZW_L_H_SPG ror temp1 sts ZW_L_H_SPG,temp1 lds temp1,ZW_L_L_SPG ror temp1 sts ZW_L_L_SPG,temp1 ; HILFSREGISTER=0 ? lds temp1,ZW_L_L_SPG tst temp1 ; =0 ? brne x88xx_SPG ; nein ==> SPRUNG lds temp1,ZW_L_H_SPG tst temp1 brne x88xx_SPG lds temp1,ZW_H_L_SPG tst temp1 brne x88xx_SPG lds temp1,ZW_H_H_SPG tst temp1 brne x88xx_SPG ret ; ERROR (DIVISION durch NULL) DIVISION_32_32_ERROR_SPG: ret x88xx_SPG: jmp DIVISION_32_32_START_SPG