I/O Timing Report 34 potential circuit loops found in timing analysis. // Design: top // Package: FTBGA256 // ncd File: top_impl1.ncd // Version: Diamond Version 2.0.0.154 // Written on Thu Feb 27 11:34:48 2014 // M: Minimum Performance Grade // iotiming top_impl1.ncd top_impl1.prf I/O Timing Report (All units are in ns) Worst Case Results across Performance Grades (M, 9, 8, 7): // Input Setup and Hold Times Port Clock Edge Setup Performance_Grade Hold Performance_Grade ---------------------------------------------------------------------- (no input setup/hold data) // Clock to Output Delay Port Clock Edge Max_Delay Performance_Grade Min_Delay Performance_Grade ------------------------------------------------------------------------ (no clock to output min/max data) // Internal_Clock to Input Port Internal_Clock -------------------------------------------------------- CAN1_ clk_125_c CAN1_ can_clk_c COM1_ clk_125_c COM1_ uart_clk_c COM2_ clk_125_c COM2_ uart_clk_c COM3_ clk_125_c COM3_ uart_clk_c COM3_ clk_125_c COM3_ uart_clk_c COM3_ clk_125_c COM3_ uart_clk_c COM3_ clk_125_c COM3_ uart_clk_c COM3_ clk_125_c COM3_ uart_clk_c COM4_ clk_125_c COM4_ uart_clk_c COM4_ clk_125_c COM4_ uart_clk_c COM4_ clk_125_c COM4_ uart_clk_c COM4_ clk_125_c COM4_ uart_clk_c COM4_ clk_125_c COM4_ uart_clk_c COM5_ clk_125_c COM5_ uart_clk_c COM5_ clk_125_c COM5_ uart_clk_c COM6_ clk_125_c COM6_ uart_clk_c INP[0 clk_125_c INP[1 clk_125_c INP[1 clk_125_c INP[1 clk_125_c INP[1 clk_125_c INP[1 clk_125_c INP[1 clk_125_c INP[1 clk_125_c INP[2 clk_125_c INP[3 clk_125_c INP[4 clk_125_c INP[5 clk_125_c INP[6 clk_125_c INP[7 clk_125_c INP[8 clk_125_c INP[9 clk_125_c SRAM_ clk_125_c SRAM_ wb_tlc/cpld/di SRAM_ clk_125_c SRAM_ wb_tlc/cpld/di SRAM_ clk_125_c SRAM_ wb_tlc/cpld/di SRAM_ clk_125_c SRAM_ wb_tlc/cpld/di SRAM_ clk_125_c SRAM_ wb_tlc/cpld/di SRAM_ clk_125_c SRAM_ wb_tlc/cpld/di SRAM_ clk_125_c SRAM_ wb_tlc/cpld/di SRAM_ clk_125_c SRAM_ wb_tlc/cpld/di SRAM_ clk_125_c SRAM_ wb_tlc/cpld/di SRAM_ clk_125_c SRAM_ wb_tlc/cpld/di SRAM_ clk_125_c SRAM_ wb_tlc/cpld/di SRAM_ clk_125_c SRAM_ wb_tlc/cpld/di SRAM_ clk_125_c SRAM_ wb_tlc/cpld/di SRAM_ clk_125_c SRAM_ wb_tlc/cpld/di SRAM_ clk_125_c SRAM_ wb_tlc/cpld/di SRAM_ clk_125_c SRAM_ wb_tlc/cpld/di rstn clk_125_c rstn pcie/pclk rstn pcie/u1_pcs_pi // Internal_Clock to Output Port Internal_Clock -------------------------------------------------------- CAN1_TX clk_125_c CAN1_TX can_clk_c COM1_TXD_TTL clk_125_c COM1_TXD_TTL uart_clk_c COM2_TXD clk_125_c COM2_TXD uart_clk_c COM3_DTR clk_125_c COM3_DTR uart_clk_c COM3_RTS clk_125_c COM3_RTS uart_clk_c COM3_TXD clk_125_c COM3_TXD uart_clk_c COM4_DTR clk_125_c COM4_DTR uart_clk_c COM4_RTS clk_125_c COM4_RTS uart_clk_c COM4_TXD clk_125_c COM4_TXD uart_clk_c COM5_RTS clk_125_c COM5_RTS uart_clk_c COM5_TXD clk_125_c COM5_TXD uart_clk_c COM6_TXD clk_125_c COM6_TXD uart_clk_c LED1Gn clk_125_c LED1Rn clk_125_c LED2Gn clk_125_c LED2Rn clk_125_c LED3Gn clk_125_c LED3Rn clk_125_c LED4Gn clk_125_c LED4Rn clk_125_c SRAM_A[10] clk_125_c SRAM_A[11] clk_125_c SRAM_A[12] clk_125_c SRAM_A[13] clk_125_c SRAM_A[14] clk_125_c SRAM_A[15] clk_125_c SRAM_A[16] clk_125_c SRAM_A[17] clk_125_c SRAM_A[18] clk_125_c SRAM_A[19] clk_125_c SRAM_A[1] clk_125_c SRAM_A[2] clk_125_c SRAM_A[3] clk_125_c SRAM_A[4] clk_125_c SRAM_A[5] clk_125_c SRAM_A[6] clk_125_c SRAM_A[7] clk_125_c SRAM_A[8] clk_125_c SRAM_A[9] clk_125_c SRAM_BHEn clk_125_c SRAM_BLEn clk_125_c SRAM_CE1n clk_125_c SRAM_D[0] clk_125_c SRAM_D[10] clk_125_c SRAM_D[11] clk_125_c SRAM_D[12] clk_125_c SRAM_D[13] clk_125_c SRAM_D[14] clk_125_c SRAM_D[15] clk_125_c SRAM_D[1] clk_125_c SRAM_D[2] clk_125_c SRAM_D[3] clk_125_c SRAM_D[4] clk_125_c SRAM_D[5] clk_125_c SRAM_D[6] clk_125_c SRAM_D[7] clk_125_c SRAM_D[8] clk_125_c SRAM_D[9] clk_125_c SRAM_OEn clk_125_c SRAM_WEn clk_125_c