list p=18F46k80



; PIC18F46K80 Configuration Bit Settings

#include "p18F46K80.inc"

; CONFIG1L
  CONFIG  RETEN = OFF           ; VREG Sleep Enable bit (Ultra low-power regulator is Disabled (Controlled by REGSLP bit))
  CONFIG  INTOSCSEL = HIGH      ; LF-INTOSC Low-power Enable bit (LF-INTOSC in High-power mode during Sleep)
  CONFIG  SOSCSEL = DIG         ; SOSC Power Selection and mode Configuration bits (Digital (SCLKI) mode)
  CONFIG  XINST = OFF           ; Extended Instruction Set (Disabled)

; CONFIG1H
  CONFIG  FOSC = INTIO2         ; Oscillator (Internal RC oscillator)
  CONFIG  PLLCFG = OFF          ; PLL x4 Enable bit (Disabled)
  CONFIG  FCMEN = OFF           ; Fail-Safe Clock Monitor (Disabled)
  CONFIG  IESO = OFF            ; Internal External Oscillator Switch Over Mode (Disabled)

; CONFIG2L
  CONFIG  PWRTEN = OFF          ; Power Up Timer (Disabled)
  CONFIG  BOREN = OFF           ; Brown Out Detect (Disabled in hardware, SBOREN disabled)
  CONFIG  BORV = 3              ; Brown-out Reset Voltage bits (1.8V)
  CONFIG  BORPWR = ZPBORMV      ; BORMV Power level (ZPBORMV instead of BORMV is selected)

; CONFIG2H
  CONFIG  WDTEN = OFF           ; Watchdog Timer (WDT disabled in hardware; SWDTEN bit disabled)
  CONFIG  WDTPS = 1048576       ; Watchdog Postscaler (1:1048576)

; CONFIG3H
  CONFIG  CANMX = PORTC         ; ECAN Mux bit (ECAN TX and RX pins are located on RC6 and RC7, respectively)
  CONFIG  MSSPMSK = MSK7        ; MSSP address masking (7 Bit address masking mode)
  CONFIG  MCLRE = OFF           ; Master Clear Enable (MCLR Disabled, RG5 Enabled)

; CONFIG4L
  CONFIG  STVREN = ON           ; Stack Overflow Reset (Enabled)
  CONFIG  BBSIZ = BB2K          ; Boot Block Size (2K word Boot Block size)

; CONFIG5L
  CONFIG  CP0 = OFF             ; Code Protect 00800-03FFF (Disabled)
  CONFIG  CP1 = OFF             ; Code Protect 04000-07FFF (Disabled)
  CONFIG  CP2 = OFF             ; Code Protect 08000-0BFFF (Disabled)
  CONFIG  CP3 = OFF             ; Code Protect 0C000-0FFFF (Disabled)

; CONFIG5H
  CONFIG  CPB = OFF             ; Code Protect Boot (Disabled)
  CONFIG  CPD = OFF             ; Data EE Read Protect (Disabled)

; CONFIG6L
  CONFIG  WRT0 = OFF            ; Table Write Protect 00800-03FFF (Disabled)
  CONFIG  WRT1 = OFF            ; Table Write Protect 04000-07FFF (Disabled)
  CONFIG  WRT2 = OFF            ; Table Write Protect 08000-0BFFF (Disabled)
  CONFIG  WRT3 = OFF            ; Table Write Protect 0C000-0FFFF (Disabled)

; CONFIG6H
  CONFIG  WRTC = OFF            ; Config. Write Protect (Disabled)
  CONFIG  WRTB = OFF            ; Table Write Protect Boot (Disabled)
  CONFIG  WRTD = OFF            ; Data EE Write Protect (Disabled)

; CONFIG7L
  CONFIG  EBTR0 = OFF           ; Table Read Protect 00800-03FFF (Disabled)
  CONFIG  EBTR1 = OFF           ; Table Read Protect 04000-07FFF (Disabled)
  CONFIG  EBTR2 = OFF           ; Table Read Protect 08000-0BFFF (Disabled)
  CONFIG  EBTR3 = OFF           ; Table Read Protect 0C000-0FFFF (Disabled)

; CONFIG7H
  CONFIG  EBTRB = OFF           ; Table Read Protect Boot (Disabled)

    Timer_1 equ 0x000
    Timer_2 equ 0x001



    org 0

    MOVLW D'0'
    MOVWF ANCON0    ;Deaktivieren der Analogfunktion
    MOVWF ANCON1


    MOVLW B'00000000'
    MOVWF TRISA

    MOVLW B'00000000'
    MOVWF TRISB

    MOVLW B'11111111'
    MOVWF TRISC

    MOVLW B'00000000'
    MOVWF TRISD

    MOVLW B'00000000'
    MOVWF TRISE

    BSF OSCCON,4    ;Taktfrequenz 4MHz
    BCF OSCCON,5
    BSF OSCCON,6

    CLRF PORTA
    CLRF PORTB
    CLRF PORTC
    CLRF PORTD
    CLRF PORTE

Marke
    BTFSS PORTC,0
    GOTO $-2
    BSF LATB,0
    BTFSS PORTC,1
    GOTO $-2
    BSF LATB,1
    BTFSS PORTC,2
    GOTO $-2
    BSF LATB,2
    BTFSS PORTC,3
    GOTO $-2
    BSF LATB,3
    BTFSS PORTC,4
    GOTO $-2
    BSF LATB,4
    BTFSS PORTC,5
    GOTO $-2
    BSF LATB,5
    BTFSS PORTC,6
    GOTO $-2
    BSF LATB,6
    BTFSS PORTC,7
    GOTO $-2
    BSF LATB,7

    GOTO Marke


END