Synthesizing Unit <pibla>.
    Related source file is "C:/Users/KommPute/FPGA/LowPower_PicoBlaze/Nachbau/00_hw/src/pibla.vhd".
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <rotshft_o> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <alu_o<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 64x8-bit single-port RAM <Mram_sp_ram> for signal <sp_ram>.
    Found 16x8-bit dual-port RAM <Mram_reg_f> for signal <reg_f>.
    Found 16x8-bit dual-port RAM <Mram_reg_f_ren> for signal <reg_f>.
    Found 30x10-bit single-port RAM <Mram_stack> for signal <stack>.
    Found 1-bit register for signal <interrupt_ack>.
    Found 1-bit register for signal <read_strobe>.
    Found 8-bit register for signal <out_port>.
    Found 1-bit register for signal <write_strobe>.
    Found 10-bit addsub for signal <alu_o$addsub0000>.
    Found 1-bit register for signal <carry_bit>.
    Found 10-bit register for signal <count_q>.
    Found 1-bit register for signal <flag_c<0>>.
    Found 1-bit xor8 for signal <flag_c_0$xor0000> created at line 399.
    Found 1-bit register for signal <flag_z<0>>.
    Found 1-bit register for signal <int_ena_q<0>>.
    Found 1-bit register for signal <interrupt_del_q>.
    Found 1-bit register for signal <irq_saved_flag_c<0>>.
    Found 1-bit register for signal <irq_saved_flag_z<0>>.
    Found 8-bit xor2 for signal <lalu$xor0000> created at line 339.
    Found 10-bit adder for signal <nx_address$addsub0000> created at line 170.
    Found 8-bit register for signal <port_id_q>.
    Found 5-bit addsub for signal <stack_index$share0000> created at line 134.
    Found 5-bit register for signal <stack_index_q>.
    Summary:
	inferred   4 RAM(s).
	inferred  41 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
	inferred   1 Xor(s).
Unit <pibla> synthesized.

    Found 4-bit register for signal <digit>.
    Found 8-bit register for signal <segment>.
    Found 1-bit tristate buffer for signal <rs232_tx>.
    Found 8-bit register for signal <leds_8bit_GPIO_d_out>.
    Summary:
	inferred  20 D-type flip-flop(s).
	inferred   1 Tristate(s).
Unit <sk_top> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 4
 16x8-bit dual-port RAM                                : 2
 30x10-bit single-port RAM                             : 1
 64x8-bit single-port RAM                              : 1
# Adders/Subtractors                                   : 3
 10-bit adder                                          : 1
 10-bit addsub                                         : 1
 5-bit addsub                                          : 1
# Registers                                            : 17
 1-bit register                                        : 10
 10-bit register                                       : 1
 4-bit register                                        : 1
 5-bit register                                        : 1
 8-bit register                                        : 4
# Tristates                                            : 1
 1-bit tristate buffer                                 : 1
# Xors                                                 : 2
 1-bit xor8                                            : 1
 8-bit xor2                                            : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <pibla>.
INFO:Xst:3031 - HDL ADVISOR - The RAM <Mram_sp_ram> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 64-word x 8-bit                     |          |
    |     clkA           | connected to signal <clk>           | rise     |
    |     weA            | connected to signal <sp_we>         | high     |
    |     addrA          | connected to signal <sp_a>          |          |
    |     diA            | connected to signal <freg_doSx>     |          |
    |     doA            | connected to signal <sp_do>         |          |
    -----------------------------------------------------------------------
INFO:Xst:3031 - HDL ADVISOR - The RAM <Mram_reg_f> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 16-word x 8-bit                     |          |
    |     clkA           | connected to signal <clk>           | rise     |
    |     weA            | connected to signal <freg_we>       | high     |
    |     addrA          | connected to signal <instruction>   |          |
    |     diA            | connected to signal <freg_di>       |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 16-word x 8-bit                     |          |
    |     addrB          | connected to signal <instruction>   |          |
    |     doB            | connected to signal <freg_doSx>     |          |
    -----------------------------------------------------------------------
INFO:Xst:3031 - HDL ADVISOR - The RAM <Mram_reg_f_ren> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 16-word x 8-bit                     |          |
    |     clkA           | connected to signal <clk>           | rise     |
    |     weA            | connected to signal <freg_we>       | high     |
    |     addrA          | connected to signal <instruction>   |          |
    |     diA            | connected to signal <freg_di>       |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 16-word x 8-bit                     |          |
    |     addrB          | connected to signal <instruction>   |          |
    |     doB            | connected to signal <freg_doSy>     |          |
    -----------------------------------------------------------------------
INFO:Xst:3031 - HDL ADVISOR - The RAM <Mram_stack> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 30-word x 10-bit                    |          |
    |     clkA           | connected to signal <clk>           | rise     |
    |     weA            | connected to signal <save_pc>       | high     |
    |     addrA          | connected to signal <stack_addr>    |          |
    |     diA            | connected to signal <nx_address>    |          |
    |     doA            | connected to signal <addr4stack>    |          |
    -----------------------------------------------------------------------
Unit <pibla> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 4
 16x8-bit dual-port distributed RAM                    : 2
 30x10-bit single-port distributed RAM                 : 1
 64x8-bit single-port distributed RAM                  : 1
# Adders/Subtractors                                   : 3
 10-bit adder                                          : 1
 10-bit addsub                                         : 1
 5-bit addsub                                          : 1
# Registers                                            : 61
 Flip-Flops                                            : 61
# Xors                                                 : 2
 1-bit xor8                                            : 1
 8-bit xor2                                            : 1

=========================================================================



=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 83
 Flip-Flops                                            : 83

=========================================================================


=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : sk_top
Output Format                      : NGC
Optimization Goal                  : Area
Keep Hierarchy                     : No

Design Statistics
# IOs                              : 111

Cell Usage :
# BELS                             : 368
#      GND                         : 1
#      LUT1                        : 9
#      LUT2                        : 28
#      LUT3                        : 68
#      LUT4                        : 191
#      MULT_AND                    : 1
#      MUXCY                       : 18
#      MUXF5                       : 32
#      VCC                         : 1
#      XORCY                       : 19
# FlipFlops/Latches                : 83
#      FD                          : 40
#      FDE                         : 41
#      FDR                         : 2
# RAMS                             : 42
#      RAM16X1D                    : 16
#      RAM32X1S                    : 26
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 65
#      IBUF                        : 12
#      OBUF                        : 52
#      OBUFT                       : 1
# Others                           : 1
#      core_mem                    : 1
=========================================================================
PACKER Warning: Lut b_pibla.pibla_1/alu_o_mux00002 driving carry b_pibla.pibla_1/Maddsub_alu_o_addsub0000_cy<0> can not be packed with the carry due to conflict with the common signal requirement between the LUT inputs and the Carry DI/MAND pins. This would result in an extra LUT for a feedthrough.

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                      215  out of   1920    11%  
 Number of Slice Flip Flops:             62  out of   3840     1%  
 Number of 4 input LUTs:                380  out of   3840     9%  
    Number used as logic:               296
    Number used as RAMs:                 84
 Number of IOs:                         111
 Number of bonded IOBs:                  66  out of    173    38%  
    IOB Flip Flops:                      21
 Number of GCLKs:                         1  out of      8    12%  


------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
sys_clk                            | BUFGP                  | 125   |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 16.644ns (Maximum Frequency: 60.080MHz)
   Minimum input arrival time before clock: 18.200ns
   Maximum output required time after clock: 17.691ns
   Maximum combinational path delay: 16.688ns