Project Settings
Project Name proj_1 Implementation Name impl
Top Module AddressDecoder Pipelining 1
Retiming 0 Resource Sharing 1
Fanout Guide 1000 Disable I/O Insertion 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 6 1 0 - 0m:03s - 21.10.2015
16:08:55
(premap)Complete 2 1 0 0m:00s 0m:00s 148MB 21.10.2015
16:08:57
(fpga_mapper)Complete 23 1 0 0m:15s 0m:15s 298MB 21.10.2015
16:09:13
Multi-srs Generator Complete0m:00s21.10.2015
16:08:57

Area Summary
Register bits 4662 I/O cells 4641
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
ORCA LUTs (total_luts) 412

Timing Summary
Clock NameReq FreqEst FreqSlack
AddressDecoder|iSysClk206.8 MHz175.8 MHz-0.853

Optimizations Summary
Combined Clock Conversion 1 / 0