#Build: Synplify Pro J-2015.03L, Build 030R, Apr 20 2015
#install: F:\Tools\Lattice\diamond\3.5_x64\synpbase
#OS: Windows 7 6.1
#Hostname: FETTE-WORK

#Implementation: impl

Synopsys HDL Compiler, version comp201503p1, Build 058R, built Apr 20 2015
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

Synopsys VHDL Compiler, version comp201503p1, Build 058R, built Apr 20 2015
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

@N:CD720 : std.vhd(123) | Setting time resolution to ns
@N: : AddressDecoder.vhd(21) | Top entity is set to AddressDecoder.
VHDL syntax check successful!
@N:CD630 : AddressDecoder.vhd(21) | Synthesizing work.addressdecoder.rtl 
Post processing for work.addressdecoder.rtl
@W:CL137 : AddressDecoder.vhd(96) | Combinational loop found at sAccessViolationWr_1_sqmuxa

At c_vhdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 90MB peak: 92MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Oct 21 16:08:55 2015

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Synopsys Netlist Linker, version comp201503p1, Build 058R, built Apr 20 2015
@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 72MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Oct 21 16:08:55 2015

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@END

At c_hdl Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Oct 21 16:08:55 2015

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Synopsys Netlist Linker, version comp201503p1, Build 058R, built Apr 20 2015
@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Oct 21 16:08:57 2015

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Pre-mapping Report

Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1176R, Built Apr 20 2015 17:38:44
Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
Product Version J-2015.03L

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

Linked File: AdressDecoderTest_impl_scck.rpt
Printing clock  summary report in "F:\work\AdressdecoderCLoop\diamond\impl\AdressDecoderTest_impl_scck.rpt" file 
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 108MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 108MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 119MB)

ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=15  set on top level netlist AddressDecoder

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 146MB peak: 148MB)



@S |Clock Summary
*****************

Start                      Requested     Requested     Clock        Clock                
Clock                      Frequency     Period        Type         Group                
-----------------------------------------------------------------------------------------
AddressDecoder|iSysClk     233.8 MHz     4.277         inferred     Autoconstr_clkgroup_0
=========================================================================================

@W:MT529 : addressdecoder.vhd(86) | Found inferred clock AddressDecoder|iSysClk which controls 4639 sequential elements including sAccessViolationWr. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 83MB peak: 148MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Oct 21 16:08:57 2015

###########################################################]
Map & Optimize Report

Synopsys Lattice Technology Mapper, Version maplat, Build 1176R, Built Apr 20 2015 17:38:44
Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
Product Version J-2015.03L

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 111MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 144MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 145MB peak: 146MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 159MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 158MB peak: 162MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 163MB peak: 164MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 164MB peak: 165MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 166MB peak: 167MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:06s; Memory used current: 165MB peak: 167MB)


Finished preparing to map (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 161MB peak: 167MB)


Finished technology mapping (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:07s; Memory used current: 182MB peak: 185MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:08s		    -1.96ns		 353 /      4639
   2		0h:00m:08s		    -1.96ns		 353 /      4639
   3		0h:00m:08s		    -1.95ns		 353 /      4639
@N:FX271 : addressdecoder.vhd(69) | Instance "sDspAddrA[4]" with 53 loads replicated 3 times to improve timing 
@N:FX271 : addressdecoder.vhd(69) | Instance "sDspAddrA[8]" with 13 loads replicated 1 times to improve timing 
@N:FX271 : addressdecoder.vhd(69) | Instance "sDspAddrA[7]" with 9 loads replicated 1 times to improve timing 
@N:FX271 : addressdecoder.vhd(69) | Instance "sDspRwN" with 6 loads replicated 1 times to improve timing 
@N:FX271 : addressdecoder.vhd(69) | Instance "sDspCsN" with 6 loads replicated 1 times to improve timing 
@N:FX271 : addressdecoder.vhd(69) | Instance "sDspAddrA[6]" with 13 loads replicated 2 times to improve timing 
@N:FX271 : addressdecoder.vhd(69) | Instance "sDspAddrA[5]" with 13 loads replicated 2 times to improve timing 
@N:FX271 : addressdecoder.vhd(69) | Instance "sDspAddrA[11]" with 5 loads replicated 1 times to improve timing 
@N:FX271 : addressdecoder.vhd(69) | Instance "sDspAddrA[10]" with 5 loads replicated 1 times to improve timing 
@N:FX271 : addressdecoder.vhd(69) | Instance "sDspAddrA[2]" with 15 loads replicated 1 times to improve timing 
@N:FX271 : addressdecoder.vhd(69) | Instance "sDspAddrA[3]" with 15 loads replicated 1 times to improve timing 
Timing driven replication report
Added 15 Registers via timing driven replication
Added 0 LUTs via timing driven replication

@N:FX271 : addressdecoder.vhd(69) | Instance "sDspAddrA[1]" with 33 loads replicated 3 times to improve timing 
@N:FX271 : addressdecoder.vhd(69) | Instance "sDspAddrA[0]" with 33 loads replicated 3 times to improve timing 
Added 6 Registers via timing driven replication
Added 0 LUTs via timing driven replication

@N:FX271 : addressdecoder.vhd(69) | Instance "sDspAddrA[9]" with 29 loads replicated 2 times to improve timing 
Added 2 Registers via timing driven replication
Added 0 LUTs via timing driven replication

   4		0h:00m:10s		    -1.70ns		 412 /      4662
   5		0h:00m:10s		    -1.24ns		 411 /      4662


   6		0h:00m:10s		    -1.24ns		 411 /      4662

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 182MB peak: 185MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:12s; CPU Time elapsed 0h:00m:12s; Memory used current: 290MB peak: 298MB)



#### START OF CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 4662 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

============================ Non-Gated/Non-Generated Clocks =============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance  
-----------------------------------------------------------------------------------------
ClockId0001        iSysClk             port                   4662       oBlock_1_0_0io[0]
=========================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 239MB peak: 298MB)

Writing Analyst data base F:\work\AdressdecoderCLoop\diamond\impl\synwork\AdressDecoderTest_impl_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 281MB peak: 298MB)

Writing EDIF Netlist and constraint files
J-2015.03L
@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 288MB peak: 298MB)


Start final timing analysis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 290MB peak: 298MB)

@W:MT420 :  | Found inferred clock AddressDecoder|iSysClk with period 4.84ns. Please declare a user-defined clock on object "p:iSysClk" 



@S |##### START OF TIMING REPORT #####[
# Timing Report written on Wed Oct 21 16:09:13 2015
#


Top view:               AddressDecoder
Requested Frequency:    206.8 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing. 

@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock. 



Performance Summary 
*******************


Worst slack in design: -0.853

                           Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock             Frequency     Frequency     Period        Period        Slack      Type         Group                
--------------------------------------------------------------------------------------------------------------------------------
AddressDecoder|iSysClk     206.8 MHz     175.8 MHz     4.835         5.689         -0.853     inferred     Autoconstr_clkgroup_0
================================================================================================================================





Clock Relationships
*******************

Clocks                                          |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------------------
Starting                Ending                  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------------------
AddressDecoder|iSysClk  AddressDecoder|iSysClk  |  4.835       -0.853  |  No paths    -      |  No paths    -      |  No paths    -    
=======================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: AddressDecoder|iSysClk
====================================



Starting Points with Worst Slack
********************************

                           Starting                                                               Arrival           
Instance                   Reference                  Type         Pin     Net                    Time        Slack 
                           Clock                                                                                    
--------------------------------------------------------------------------------------------------------------------
sDspAddrA_fast[2]          AddressDecoder|iSysClk     FD1S3DX      Q       sDspAddrA_fast[2]      1.373       -0.853
sDspAddrA_fast[3]          AddressDecoder|iSysClk     FD1S3DX      Q       sDspAddrA_fast[3]      1.340       -0.820
sDspAddrA[11]              AddressDecoder|iSysClk     FD1S3DX      Q       sDspAddrA[11]          1.213       -0.789
sDspAddrA_0io[10]          AddressDecoder|iSysClk     IFS1P3DX     Q       sDspAddrA[10]          1.213       -0.789
sDspAddrA_fast[9]          AddressDecoder|iSysClk     FD1S3DX      Q       sDspAddrA_fast[9]      1.213       -0.789
sDspAddrA_5_rep1           AddressDecoder|iSysClk     FD1S3DX      Q       sDspAddrA_5_rep1       1.279       -0.774
sDspAddrA_6_rep1           AddressDecoder|iSysClk     FD1S3DX      Q       sDspAddrA_6_rep1       1.279       -0.774
sDspAddrA_fast[7]          AddressDecoder|iSysClk     FD1S3DX      Q       sDspAddrA_fast[7]      1.279       -0.774
sDspAddrA_fast[10]         AddressDecoder|iSysClk     FD1S3DX      Q       sDspAddrA_fast[10]     1.298       -0.760
sDspAddrA_fast_0io[11]     AddressDecoder|iSysClk     IFS1P3DX     Q       sDspAddrA_fast[11]     1.298       -0.760
====================================================================================================================


Ending Points with Worst Slack
******************************

                       Starting                                                                 Required           
Instance               Reference                  Type         Pin     Net                      Time         Slack 
                       Clock                                                                                       
-------------------------------------------------------------------------------------------------------------------
sAccessViolationWr     AddressDecoder|iSysClk     FD1S3DX      D       N_17742_0                4.099        -0.853
oBlock_1_29_0io[0]     AddressDecoder|iSysClk     OFS1P3DX     SP      oBlock_1_29_0_sqmuxa     4.475        -0.384
oBlock_1_29_0io[1]     AddressDecoder|iSysClk     OFS1P3DX     SP      oBlock_1_29_0_sqmuxa     4.475        -0.384
oBlock_1_29_0io[2]     AddressDecoder|iSysClk     OFS1P3DX     SP      oBlock_1_29_0_sqmuxa     4.475        -0.384
oBlock_1_29_0io[3]     AddressDecoder|iSysClk     OFS1P3DX     SP      oBlock_1_29_0_sqmuxa     4.475        -0.384
oBlock_1_29_0io[4]     AddressDecoder|iSysClk     OFS1P3DX     SP      oBlock_1_29_0_sqmuxa     4.475        -0.384
oBlock_1_29_0io[5]     AddressDecoder|iSysClk     OFS1P3DX     SP      oBlock_1_29_0_sqmuxa     4.475        -0.384
oBlock_1_29_0io[6]     AddressDecoder|iSysClk     OFS1P3DX     SP      oBlock_1_29_0_sqmuxa     4.475        -0.384
oBlock_1_29_0io[7]     AddressDecoder|iSysClk     OFS1P3DX     SP      oBlock_1_29_0_sqmuxa     4.475        -0.384
oBlock_1_29_0io[8]     AddressDecoder|iSysClk     OFS1P3DX     SP      oBlock_1_29_0_sqmuxa     4.475        -0.384
===================================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      4.835
    - Setup time:                            0.736
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.099

    - Propagation time:                      4.953
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.853

    Number of logic level(s):                4
    Starting point:                          sDspAddrA_fast[2] / Q
    Ending point:                            sAccessViolationWr / D
    The start point is clocked by            AddressDecoder|iSysClk [rising] on pin CK
    The end   point is clocked by            AddressDecoder|iSysClk [rising] on pin CK

Instance / Net                                      Pin      Pin               Arrival     No. of    
Name                                   Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------
sDspAddrA_fast[2]                      FD1S3DX      Q        Out     1.373     1.373       -         
sDspAddrA_fast[2]                      Net          -        -       -         -           21        
sAccessViolationWr_1_sqmuxa_i_0_o3     ORCALUT4     A        In      0.000     1.373       -         
sAccessViolationWr_1_sqmuxa_i_0_o3     ORCALUT4     Z        Out     1.268     2.641       -         
N_371                                  Net          -        -       -         -           25        
sAccessViolationWr_1_sqmuxa_i_0_a2     ORCALUT4     A        In      0.000     2.641       -         
sAccessViolationWr_1_sqmuxa_i_0_a2     ORCALUT4     Z        Out     0.883     3.524       -         
N_658                                  Net          -        -       -         -           1         
sAccessViolationWr_0_RNO               ORCALUT4     A        In      0.000     3.524       -         
sAccessViolationWr_0_RNO               ORCALUT4     Z        Out     0.883     4.408       -         
N_2314_i                               Net          -        -       -         -           1         
sAccessViolationWr_0                   ORCALUT4     A        In      0.000     4.408       -         
sAccessViolationWr_0                   ORCALUT4     Z        Out     0.545     4.953       -         
N_17742_0                              Net          -        -       -         -           1         
sAccessViolationWr                     FD1S3DX      D        In      0.000     4.953       -         
=====================================================================================================


Path information for path number 2: 
      Requested Period:                      4.835
    - Setup time:                            0.736
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.099

    - Propagation time:                      4.953
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.853

    Number of logic level(s):                4
    Starting point:                          sDspAddrA_fast[2] / Q
    Ending point:                            sAccessViolationWr / D
    The start point is clocked by            AddressDecoder|iSysClk [rising] on pin CK
    The end   point is clocked by            AddressDecoder|iSysClk [rising] on pin CK

Instance / Net                                        Pin      Pin               Arrival     No. of    
Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
sDspAddrA_fast[2]                        FD1S3DX      Q        Out     1.373     1.373       -         
sDspAddrA_fast[2]                        Net          -        -       -         -           21        
sAccessViolationWr_1_sqmuxa_i_0_o3       ORCALUT4     A        In      0.000     1.373       -         
sAccessViolationWr_1_sqmuxa_i_0_o3       ORCALUT4     Z        Out     1.268     2.641       -         
N_371                                    Net          -        -       -         -           25        
sAccessViolationWr_1_sqmuxa_i_0_a2_1     ORCALUT4     A        In      0.000     2.641       -         
sAccessViolationWr_1_sqmuxa_i_0_a2_1     ORCALUT4     Z        Out     0.883     3.524       -         
N_711                                    Net          -        -       -         -           1         
sAccessViolationWr_0_RNO                 ORCALUT4     C        In      0.000     3.524       -         
sAccessViolationWr_0_RNO                 ORCALUT4     Z        Out     0.883     4.408       -         
N_2314_i                                 Net          -        -       -         -           1         
sAccessViolationWr_0                     ORCALUT4     A        In      0.000     4.408       -         
sAccessViolationWr_0                     ORCALUT4     Z        Out     0.545     4.953       -         
N_17742_0                                Net          -        -       -         -           1         
sAccessViolationWr                       FD1S3DX      D        In      0.000     4.953       -         
=======================================================================================================


Path information for path number 3: 
      Requested Period:                      4.835
    - Setup time:                            0.736
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.099

    - Propagation time:                      4.920
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.820

    Number of logic level(s):                4
    Starting point:                          sDspAddrA_fast[3] / Q
    Ending point:                            sAccessViolationWr / D
    The start point is clocked by            AddressDecoder|iSysClk [rising] on pin CK
    The end   point is clocked by            AddressDecoder|iSysClk [rising] on pin CK

Instance / Net                                      Pin      Pin               Arrival     No. of    
Name                                   Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------
sDspAddrA_fast[3]                      FD1S3DX      Q        Out     1.340     1.340       -         
sDspAddrA_fast[3]                      Net          -        -       -         -           14        
sAccessViolationWr_1_sqmuxa_i_0_o3     ORCALUT4     B        In      0.000     1.340       -         
sAccessViolationWr_1_sqmuxa_i_0_o3     ORCALUT4     Z        Out     1.268     2.608       -         
N_371                                  Net          -        -       -         -           25        
sAccessViolationWr_1_sqmuxa_i_0_a2     ORCALUT4     A        In      0.000     2.608       -         
sAccessViolationWr_1_sqmuxa_i_0_a2     ORCALUT4     Z        Out     0.883     3.491       -         
N_658                                  Net          -        -       -         -           1         
sAccessViolationWr_0_RNO               ORCALUT4     A        In      0.000     3.491       -         
sAccessViolationWr_0_RNO               ORCALUT4     Z        Out     0.883     4.375       -         
N_2314_i                               Net          -        -       -         -           1         
sAccessViolationWr_0                   ORCALUT4     A        In      0.000     4.375       -         
sAccessViolationWr_0                   ORCALUT4     Z        Out     0.545     4.920       -         
N_17742_0                              Net          -        -       -         -           1         
sAccessViolationWr                     FD1S3DX      D        In      0.000     4.920       -         
=====================================================================================================


Path information for path number 4: 
      Requested Period:                      4.835
    - Setup time:                            0.736
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.099

    - Propagation time:                      4.920
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.820

    Number of logic level(s):                4
    Starting point:                          sDspAddrA_fast[3] / Q
    Ending point:                            sAccessViolationWr / D
    The start point is clocked by            AddressDecoder|iSysClk [rising] on pin CK
    The end   point is clocked by            AddressDecoder|iSysClk [rising] on pin CK

Instance / Net                                        Pin      Pin               Arrival     No. of    
Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
sDspAddrA_fast[3]                        FD1S3DX      Q        Out     1.340     1.340       -         
sDspAddrA_fast[3]                        Net          -        -       -         -           14        
sAccessViolationWr_1_sqmuxa_i_0_o3       ORCALUT4     B        In      0.000     1.340       -         
sAccessViolationWr_1_sqmuxa_i_0_o3       ORCALUT4     Z        Out     1.268     2.608       -         
N_371                                    Net          -        -       -         -           25        
sAccessViolationWr_1_sqmuxa_i_0_a2_1     ORCALUT4     A        In      0.000     2.608       -         
sAccessViolationWr_1_sqmuxa_i_0_a2_1     ORCALUT4     Z        Out     0.883     3.491       -         
N_711                                    Net          -        -       -         -           1         
sAccessViolationWr_0_RNO                 ORCALUT4     C        In      0.000     3.491       -         
sAccessViolationWr_0_RNO                 ORCALUT4     Z        Out     0.883     4.375       -         
N_2314_i                                 Net          -        -       -         -           1         
sAccessViolationWr_0                     ORCALUT4     A        In      0.000     4.375       -         
sAccessViolationWr_0                     ORCALUT4     Z        Out     0.545     4.920       -         
N_17742_0                                Net          -        -       -         -           1         
sAccessViolationWr                       FD1S3DX      D        In      0.000     4.920       -         
=======================================================================================================


Path information for path number 5: 
      Requested Period:                      4.835
    - Setup time:                            0.736
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         4.099

    - Propagation time:                      4.889
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (non-critical) :                 -0.789

    Number of logic level(s):                4
    Starting point:                          sDspAddrA[11] / Q
    Ending point:                            sAccessViolationWr / D
    The start point is clocked by            AddressDecoder|iSysClk [rising] on pin CK
    The end   point is clocked by            AddressDecoder|iSysClk [rising] on pin CK

Instance / Net                                        Pin      Pin               Arrival     No. of    
Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
-------------------------------------------------------------------------------------------------------
sDspAddrA[11]                            FD1S3DX      Q        Out     1.213     1.213       -         
sDspAddrA[11]                            Net          -        -       -         -           4         
oBlock_3_0_0_sqmuxa_0_a2_0_a3_m1_e_0     ORCALUT4     B        In      0.000     1.213       -         
oBlock_3_0_0_sqmuxa_0_a2_0_a3_m1_e_0     ORCALUT4     Z        Out     1.364     2.577       -         
N_731                                    Net          -        -       -         -           67        
sAccessViolationWr_1_sqmuxa_i_0_a2       ORCALUT4     B        In      0.000     2.577       -         
sAccessViolationWr_1_sqmuxa_i_0_a2       ORCALUT4     Z        Out     0.883     3.460       -         
N_658                                    Net          -        -       -         -           1         
sAccessViolationWr_0_RNO                 ORCALUT4     A        In      0.000     3.460       -         
sAccessViolationWr_0_RNO                 ORCALUT4     Z        Out     0.883     4.344       -         
N_2314_i                                 Net          -        -       -         -           1         
sAccessViolationWr_0                     ORCALUT4     A        In      0.000     4.344       -         
sAccessViolationWr_0                     ORCALUT4     Z        Out     0.545     4.889       -         
N_17742_0                                Net          -        -       -         -           1         
sAccessViolationWr                       FD1S3DX      D        In      0.000     4.889       -         
=======================================================================================================



##### END OF TIMING REPORT #####]


Finished final timing analysis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 291MB peak: 298MB)


Finished timing report (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 291MB peak: 298MB)

---------------------------------------
Resource Usage Report
Part: lfxp2_17e-5

Register bits: 4662 of 16560 (28%)
PIC Latch:       0
I/O cells:       4641


Details:
FD1S3BX:        2
FD1S3DX:        22
GSR:            1
IB:             32
IFS1P3BX:       2
IFS1P3DX:       28
OB:             4609
OFS1P3DX:       4608
ORCALUT4:       412
PUR:            1
VHI:            1
VLO:            1
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 169MB peak: 298MB)

Process took 0h:00m:15s realtime, 0h:00m:15s cputime
# Wed Oct 21 16:09:13 2015

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