Project Settings
Project Name proj_1 Implementation Name impl
Top Module AddressDecoder Pipelining 1
Retiming 0 Resource Sharing 1
Fanout Guide 1000 Disable I/O Insertion 0
Clock Conversion 1 FSM Compiler 1

Run Status
Job Name Status CPU Time Real Time Memory Date/Time
(compiler)Complete 6 768 0 - 0m:02s - 21.10.2015
16:07:34
(premap)Complete 2 1 0 0m:00s 0m:00s 147MB 21.10.2015
16:07:36
(fpga_mapper)Complete 20 1 0 0m:13s 0m:13s 283MB 21.10.2015
16:07:50
Multi-srs Generator Complete0m:01s21.10.2015
16:07:35

Area Summary
Register bits 3888 I/O cells 4641
Block RAMs (v_ram) 0 DSPs (dsp_used) 0
ORCA LUTs (total_luts) 299

Timing Summary
Clock NameReq FreqEst FreqSlack
AddressDecoder|iSysClk210.4 MHz178.9 MHz-0.839

Optimizations Summary
Combined Clock Conversion 1 / 0