#Build: Synplify Pro J-2015.03L, Build 030R, Apr 20 2015
#install: F:\Tools\Lattice\diamond\3.5_x64\synpbase
#OS: Windows 7 6.1
#Hostname: FETTE-WORK

#Implementation: impl

Synopsys HDL Compiler, version comp201503p1, Build 058R, built Apr 20 2015
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

Synopsys VHDL Compiler, version comp201503p1, Build 058R, built Apr 20 2015
@N: :  | Running in 64-bit mode 
Copyright (C) 1994-2015 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.

@N:CD720 : std.vhd(123) | Setting time resolution to ns
@N: : AddressDecoder.vhd(21) | Top entity is set to AddressDecoder.
VHDL syntax check successful!
@N:CD630 : AddressDecoder.vhd(21) | Synthesizing work.addressdecoder.rtl 
Post processing for work.addressdecoder.rtl
@W:CL137 : AddressDecoder.vhd(62) | Combinational loop found at sAccessViolationWr_1_sqmuxa

At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 88MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Oct 22 11:58:56 2015

###########################################################]
Synopsys Netlist Linker, version comp201503p1, Build 058R, built Apr 20 2015
@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Oct 22 11:58:57 2015

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Oct 22 11:58:57 2015

###########################################################]
Synopsys Netlist Linker, version comp201503p1, Build 058R, built Apr 20 2015
@N: :  | Running in 64-bit mode 

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 68MB peak: 69MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Oct 22 11:58:58 2015

###########################################################]
Pre-mapping Report

Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1176R, Built Apr 20 2015 17:38:44
Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
Product Version J-2015.03L

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

Linked File: AdressDecoderTest_impl_scck.rpt
Printing clock  summary report in "F:\work\CombinatoricLoop\diamond\impl\AdressDecoderTest_impl_scck.rpt" file 
@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)

ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=15  set on top level netlist AddressDecoder

Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)



@S |Clock Summary
*****************

Start                      Requested     Requested     Clock        Clock                
Clock                      Frequency     Period        Type         Group                
-----------------------------------------------------------------------------------------
AddressDecoder|iSysClk     959.2 MHz     1.043         inferred     Autoconstr_clkgroup_0
=========================================================================================

@W:MT529 : addressdecoder.vhd(53) | Found inferred clock AddressDecoder|iSysClk which controls 259 sequential elements including sAccessViolationWr. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 141MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Thu Oct 22 11:58:58 2015

###########################################################]
Map & Optimize Report

Synopsys Lattice Technology Mapper, Version maplat, Build 1176R, Built Apr 20 2015 17:38:44
Copyright (C) 1994-2015, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc.  All other use, reproduction, or distribution of this software is strictly prohibited.
Product Version J-2015.03L

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@N:MF248 :  | Running in 64-bit mode. 
@N:MF666 :  | Clock conversion enabled  

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 110MB peak: 111MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 113MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)


Available hyper_sources - for debug and ip models
	None Found

@N:MT206 :  | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)


Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 145MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 145MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 145MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 145MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 145MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 145MB)


Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 141MB peak: 145MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 168MB peak: 170MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		100000.00ns		 294 /       259

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 168MB peak: 170MB)

@N:FX164 :  | The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.   

Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 169MB peak: 170MB)



#### START OF CLOCK OPTIMIZATION REPORT #####[

1 non-gated/non-generated clock tree(s) driving 259 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks

=========================== Non-Gated/Non-Generated Clocks ============================
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
---------------------------------------------------------------------------------------
ClockId0001        iSysClk             port                   259        oBlock_0io[0]  
=======================================================================================


##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 134MB peak: 170MB)

Writing Analyst data base F:\work\CombinatoricLoop\diamond\impl\synwork\AdressDecoderTest_impl_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 168MB peak: 170MB)

Writing EDIF Netlist and constraint files
J-2015.03L
@N:BW106 :  | Synplicity Constraint File capacitance units using default value of 1pF  

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 171MB peak: 174MB)


Start final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 172MB peak: 174MB)

@W:MT420 :  | Found inferred clock AddressDecoder|iSysClk with period 2.02ns. Please declare a user-defined clock on object "p:iSysClk" 



@S |##### START OF TIMING REPORT #####[
# Timing Report written on Thu Oct 22 11:59:01 2015
#


Top view:               AddressDecoder
Requested Frequency:    496.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:MT320 :  | Timing report estimates place and route data. Please look at the place and route timing report for final timing. 

@N:MT322 :  | Clock constraints cover only FF-to-FF paths associated with the clock. 



Performance Summary 
*******************


Worst slack in design: -0.356

                           Requested     Estimated     Requested     Estimated                Clock        Clock                
Starting Clock             Frequency     Frequency     Period        Period        Slack      Type         Group                
--------------------------------------------------------------------------------------------------------------------------------
AddressDecoder|iSysClk     496.0 MHz     421.6 MHz     2.016         2.372         -0.356     inferred     Autoconstr_clkgroup_0
================================================================================================================================





Clock Relationships
*******************

Clocks                                          |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------------------------------------
Starting                Ending                  |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------------------------------------
AddressDecoder|iSysClk  AddressDecoder|iSysClk  |  2.016       -0.356  |  No paths    -      |  No paths    -      |  No paths    -    
=======================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

No IO constraint found



====================================
Detailed Report for Clock: AddressDecoder|iSysClk
====================================



Starting Points with Worst Slack
********************************

                       Starting                                                              Arrival           
Instance               Reference                  Type        Pin     Net                    Time        Slack 
                       Clock                                                                                   
---------------------------------------------------------------------------------------------------------------
sAccessViolationWr     AddressDecoder|iSysClk     FD1S3DX     Q       oAccessViolation_c     1.091       -0.356
===============================================================================================================


Ending Points with Worst Slack
******************************

                       Starting                                                    Required           
Instance               Reference                  Type        Pin     Net          Time         Slack 
                       Clock                                                                          
------------------------------------------------------------------------------------------------------
sAccessViolationWr     AddressDecoder|iSysClk     FD1S3DX     D       N_2018_0     1.280        -0.356
======================================================================================================



Worst Path Information
View Worst Path in Analyst
***********************


Path information for path number 1: 
      Requested Period:                      2.016
    - Setup time:                            0.736
    + Clock delay at ending point:           0.000 (ideal)
    = Required time:                         1.280

    - Propagation time:                      1.636
    - Clock delay at starting point:         0.000 (ideal)
    = Slack (critical) :                     -0.356

    Number of logic level(s):                1
    Starting point:                          sAccessViolationWr / Q
    Ending point:                            sAccessViolationWr / D
    The start point is clocked by            AddressDecoder|iSysClk [rising] on pin CK
    The end   point is clocked by            AddressDecoder|iSysClk [rising] on pin CK

Instance / Net                          Pin      Pin               Arrival     No. of    
Name                       Type         Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------
sAccessViolationWr         FD1S3DX      Q        Out     1.091     1.091       -         
oAccessViolation_c         Net          -        -       -         -           2         
sAccessViolationWr_RNO     ORCALUT4     A        In      0.000     1.091       -         
sAccessViolationWr_RNO     ORCALUT4     Z        Out     0.545     1.636       -         
N_2018_0                   Net          -        -       -         -           1         
sAccessViolationWr         FD1S3DX      D        In      0.000     1.636       -         
=========================================================================================



##### END OF TIMING REPORT #####]


Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 172MB peak: 174MB)


Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 172MB peak: 174MB)

---------------------------------------
Resource Usage Report
Part: lfxp2_17e-5

Register bits: 259 of 16560 (2%)
PIC Latch:       0
I/O cells:       278


Details:
FD1S3DX:        1
GSR:            1
IB:             19
OB:             259
OFS1P3DX:       258
ORCALUT4:       294
PUR:            1
VHI:            1
VLO:            1
Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 52MB peak: 174MB)

Process took 0h:00m:02s realtime, 0h:00m:02s cputime
# Thu Oct 22 11:59:01 2015

###########################################################]