Project Settings |
---|
Project Name | proj_1 | Implementation Name | impl |
Top Module | AddressDecoder | Pipelining | 1 |
Retiming | 0 | Resource Sharing | 1 |
Fanout Guide | 1000 | Disable I/O Insertion | 0 |
Clock Conversion | 1 | FSM Compiler | 1 |
Run Status |
Job Name |
Status |
|
|
|
CPU Time |
Real Time |
Memory |
Date/Time |
(compiler) | Complete |
6 |
1 |
0 |
- |
0m:01s |
- |
22.10.2015 11:58:57 |
(premap) | Complete |
2 |
1 |
0 |
0m:00s |
0m:00s |
141MB |
22.10.2015 11:58:58 |
(fpga_mapper) | Complete |
9 |
1 |
0 |
0m:02s |
0m:02s |
174MB |
22.10.2015 11:59:01 |
Multi-srs Generator |
Complete | | | | 0m:00s | | | 22.10.2015 11:58:58 |
Area Summary |
|
Register bits | 259 |
I/O cells | 278 |
Block RAMs
(v_ram) | 0 |
DSPs
(dsp_used) | 0 |
ORCA LUTs
(total_luts) | 294 |
| |
Timing Summary |
|
Clock Name | Req Freq | Est Freq | Slack |
AddressDecoder|iSysClk | 496.0 MHz | 421.6 MHz | -0.356 |
Optimizations Summary |
Combined Clock Conversion | 1 / 0 |
| |
|