Version 4
SHEET 1 5945688 13421568
WIRE 3104 -1440 3088 -1440
WIRE 3344 -1440 3104 -1440
WIRE 3424 -1440 3344 -1440
WIRE 3536 -1440 3488 -1440
WIRE 3904 -1360 3824 -1360
WIRE 3984 -1360 3904 -1360
WIRE 3088 -1344 3088 -1440
WIRE 3344 -1328 3344 -1440
WIRE 3536 -1328 3536 -1440
WIRE 3824 -1296 3824 -1360
WIRE 3984 -1296 3984 -1360
WIRE 2928 -1264 2768 -1264
WIRE 3040 -1264 2928 -1264
WIRE 2768 -1232 2768 -1264
WIRE 2768 -1120 2768 -1152
WIRE 3088 -1120 3088 -1248
WIRE 3344 -1120 3344 -1248
WIRE 3536 -1120 3536 -1248
WIRE 3824 -1120 3824 -1216
WIRE 3984 -1120 3984 -1216
FLAG 3088 -1120 0
FLAG 3536 -1120 0
FLAG 3104 -1440 d
FLAG 3344 -1120 0
FLAG 2768 -1120 0
FLAG 2928 -1264 g
FLAG 3824 -1120 0
FLAG 3984 -1120 0
FLAG 3904 -1360 q
SYMBOL nmos 3040 -1344 R0
SYMATTR InstName M1
SYMATTR Value PSMN013100YSE
SYMBOL diode 3424 -1424 R270
WINDOW 0 32 32 VTop 2
WINDOW 3 0 32 VBottom 2
SYMATTR InstName D1
SYMATTR Value Dideal
SYMBOL CURRENT 3344 -1248 M180
WINDOW 0 24 88 Left 2
WINDOW 3 24 0 Left 2
SYMATTR InstName Id
SYMATTR Value {Id}
SYMBOL VOLTAGE 3536 -1344 R0
SYMATTR InstName Vds
SYMATTR Value {Vds}
SYMBOL voltage 2768 -1248 R0
WINDOW 123 0 0 Left 2
WINDOW 39 0 0 Left 2
SYMATTR InstName V1
SYMATTR Value PWL(0 0 120u 12)
SYMBOL bi2 3824 -1296 R0
SYMATTR InstName B1
SYMATTR Value I=-idt(I(v1))
SYMBOL res 3968 -1312 R0
SYMATTR InstName R1
SYMATTR Value 1
TEXT 2760 -1496 Left 2 !.tran 0 120u 0 0.1u
TEXT 2760 -1544 Left 2 !.params Vds=50 Id=20
TEXT 3104 -1528 Left 2 !.model  Dideal  d(is=1E-10 n=1 vpk=500)
TEXT 2744 -1016 Left 2 !.model PSMN013100YSE VDMOS(Rg=0.654 Vto=4.18 Rd=9.4m Rs=100u Rb=748u Kp=81.2 Lambda=0 Cgdmin=191p Cgdmax=3740p A=0.6 Cgs=3.18n Cjo=1.176n M=0.66 Is=1.1p VJ=0.5 N=1 TT=3n Fc=0.5 Bv=110 Ibv=250u Nbv=1 mfg=NXP Vds=100 Ron=13m Qg=75n)
TEXT 2768 -1728 Left 2 ;Gate Charge Test Circuit\nPlot V(g). The time axis is the gate charge. One can change the x-axis to time*1A for convenience.