Static Timing Analysis

Project : ST7735_LCD
Build Time : 03/05/16 14:32:30
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 5.00
VDDD : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 48.000 MHz 48.000 MHz 64.425 MHz
SPIM_IntClock CyHFCLK 24.000 MHz 24.000 MHz 47.468 MHz
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySYSCLK CySYSCLK 48.000 MHz 48.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 20.8333ns(48 MHz)
Affects clock : CyHFCLK
Source Destination FMax Delay (ns) Slack (ns) Violation
MISO(0)/fb \SPIM:BSPIM:sR8:Dp:u0\/route_si 64.425 MHz 15.522 5.311
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P2[3] 1 MISO(0) MISO(0)/in_clock MISO(0)/fb 4.047
Route 1 Net_573 MISO(0)/fb \SPIM:BSPIM:sR8:Dp:u0\/route_si 4.695
datapathcell1 U(1,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 6.780
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIM:BSPIM:sR8:Dp:u0\/so_comb \SPIM:BSPIM:mosi_pre_reg\/main_0 47.468 MHz 21.067 20.600
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ \SPIM:BSPIM:sR8:Dp:u0\/clock \SPIM:BSPIM:sR8:Dp:u0\/so_comb 8.300
Route 1 \SPIM:BSPIM:mosi_from_dp\ \SPIM:BSPIM:sR8:Dp:u0\/so_comb \SPIM:BSPIM:mosi_pre_reg_split\/main_3 3.687
macrocell1 U(1,0) 1 \SPIM:BSPIM:mosi_pre_reg_split\ \SPIM:BSPIM:mosi_pre_reg_split\/main_3 \SPIM:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \SPIM:BSPIM:mosi_pre_reg_split\ \SPIM:BSPIM:mosi_pre_reg_split\/q \SPIM:BSPIM:mosi_pre_reg\/main_0 2.220
macrocell14 U(1,0) 1 \SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SPIM:BSPIM:sR8:Dp:u0\/so_comb \SPIM:BSPIM:mosi_pre_reg\/main_1 47.596 MHz 21.010 20.657
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ \SPIM:BSPIM:sR8:Dp:u0\/clock \SPIM:BSPIM:sR8:Dp:u0\/so_comb 8.300
Route 1 \SPIM:BSPIM:mosi_from_dp\ \SPIM:BSPIM:sR8:Dp:u0\/so_comb \SPIM:BSPIM:mosi_pre_reg_split_1\/main_3 2.965
macrocell8 U(1,1) 1 \SPIM:BSPIM:mosi_pre_reg_split_1\ \SPIM:BSPIM:mosi_pre_reg_split_1\/main_3 \SPIM:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \SPIM:BSPIM:mosi_pre_reg_split_1\ \SPIM:BSPIM:mosi_pre_reg_split_1\/q \SPIM:BSPIM:mosi_pre_reg\/main_1 2.885
macrocell14 U(1,0) 1 \SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SPIM:BSPIM:state_2\/q \SPIM:BSPIM:mosi_pre_reg\/main_1 50.754 MHz 19.703 21.964
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,0) 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/clock_0 \SPIM:BSPIM:state_2\/q 1.250
Route 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/q \SPIM:BSPIM:mosi_pre_reg_split_1\/main_0 8.708
macrocell8 U(1,1) 1 \SPIM:BSPIM:mosi_pre_reg_split_1\ \SPIM:BSPIM:mosi_pre_reg_split_1\/main_0 \SPIM:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \SPIM:BSPIM:mosi_pre_reg_split_1\ \SPIM:BSPIM:mosi_pre_reg_split_1\/q \SPIM:BSPIM:mosi_pre_reg\/main_1 2.885
macrocell14 U(1,0) 1 \SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SPIM:BSPIM:state_2\/q \SPIM:BSPIM:sR8:Dp:u0\/cs_addr_2 57.947 MHz 17.257 24.410
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,0) 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/clock_0 \SPIM:BSPIM:state_2\/q 1.250
Route 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/q \SPIM:BSPIM:sR8:Dp:u0\/cs_addr_2 9.707
datapathcell1 U(1,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 6.300
Clock Skew 0.000
\SPIM:BSPIM:state_2\/q \SPIM:BSPIM:TxStsReg\/status_0 58.177 MHz 17.189 24.478
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,0) 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/clock_0 \SPIM:BSPIM:state_2\/q 1.250
Route 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/q \SPIM:BSPIM:tx_status_0\/main_0 8.708
macrocell5 U(1,1) 1 \SPIM:BSPIM:tx_status_0\ \SPIM:BSPIM:tx_status_0\/main_0 \SPIM:BSPIM:tx_status_0\/q 3.350
Route 1 \SPIM:BSPIM:tx_status_0\ \SPIM:BSPIM:tx_status_0\/q \SPIM:BSPIM:TxStsReg\/status_0 2.311
statusicell1 U(1,1) 1 \SPIM:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM:BSPIM:state_0\/q \SPIM:BSPIM:mosi_pre_reg\/main_1 60.474 MHz 16.536 25.131
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,0) 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/clock_0 \SPIM:BSPIM:state_0\/q 1.250
Route 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/q \SPIM:BSPIM:mosi_pre_reg_split_1\/main_2 5.541
macrocell8 U(1,1) 1 \SPIM:BSPIM:mosi_pre_reg_split_1\ \SPIM:BSPIM:mosi_pre_reg_split_1\/main_2 \SPIM:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \SPIM:BSPIM:mosi_pre_reg_split_1\ \SPIM:BSPIM:mosi_pre_reg_split_1\/q \SPIM:BSPIM:mosi_pre_reg\/main_1 2.885
macrocell14 U(1,0) 1 \SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SPIM:BSPIM:state_2\/q \SPIM:BSPIM:mosi_pre_reg\/main_0 62.298 MHz 16.052 25.615
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,0) 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/clock_0 \SPIM:BSPIM:state_2\/q 1.250
Route 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/q \SPIM:BSPIM:mosi_pre_reg_split\/main_0 5.722
macrocell1 U(1,0) 1 \SPIM:BSPIM:mosi_pre_reg_split\ \SPIM:BSPIM:mosi_pre_reg_split\/main_0 \SPIM:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \SPIM:BSPIM:mosi_pre_reg_split\ \SPIM:BSPIM:mosi_pre_reg_split\/q \SPIM:BSPIM:mosi_pre_reg\/main_0 2.220
macrocell14 U(1,0) 1 \SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:TxStsReg\/status_3 64.251 MHz 15.564 26.103
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 2.110
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:load_rx_data\/main_1 3.898
macrocell3 U(1,0) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_1 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 4.636
statusicell1 U(1,1) 1 \SPIM:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:TxStsReg\/status_3 64.317 MHz 15.548 26.119
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 2.110
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:load_rx_data\/main_3 3.882
macrocell3 U(1,0) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_3 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 4.636
statusicell1 U(1,1) 1 \SPIM:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:TxStsReg\/status_3 64.321 MHz 15.547 26.120
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 2.110
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:load_rx_data\/main_4 3.881
macrocell3 U(1,0) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_4 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 4.636
statusicell1 U(1,1) 1 \SPIM:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
MISO(0)/fb \SPIM:BSPIM:sR8:Dp:u0\/route_si 7.435
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P2[3] 1 MISO(0) MISO(0)/in_clock MISO(0)/fb 2.740
Route 1 Net_573 MISO(0)/fb \SPIM:BSPIM:sR8:Dp:u0\/route_si 4.695
datapathcell1 U(1,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SPIM:BSPIM:mosi_from_dp_reg\/q \SPIM:BSPIM:mosi_hs_reg\/main_5 3.482
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(0,0) 1 \SPIM:BSPIM:mosi_from_dp_reg\ \SPIM:BSPIM:mosi_from_dp_reg\/clock_0 \SPIM:BSPIM:mosi_from_dp_reg\/q 1.250
Route 1 \SPIM:BSPIM:mosi_from_dp_reg\ \SPIM:BSPIM:mosi_from_dp_reg\/q \SPIM:BSPIM:mosi_hs_reg\/main_5 2.232
macrocell13 U(0,0) 1 \SPIM:BSPIM:mosi_hs_reg\ HOLD 0.000
Clock Skew 0.000
Net_29/q Net_29/main_3 3.484
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(0,0) 1 Net_29 Net_29/clock_0 Net_29/q 1.250
macrocell12 U(0,0) 1 Net_29 Net_29/q Net_29/main_3 2.234
macrocell12 U(0,0) 1 Net_29 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:load_cond\/q \SPIM:BSPIM:load_cond\/main_8 3.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,1) 1 \SPIM:BSPIM:load_cond\ \SPIM:BSPIM:load_cond\/clock_0 \SPIM:BSPIM:load_cond\/q 1.250
macrocell15 U(1,1) 1 \SPIM:BSPIM:load_cond\ \SPIM:BSPIM:load_cond\/q \SPIM:BSPIM:load_cond\/main_8 2.306
macrocell15 U(1,1) 1 \SPIM:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:mosi_hs_reg\/q \SPIM:BSPIM:mosi_hs_reg\/main_4 3.784
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(0,0) 1 \SPIM:BSPIM:mosi_hs_reg\ \SPIM:BSPIM:mosi_hs_reg\/clock_0 \SPIM:BSPIM:mosi_hs_reg\/q 1.250
macrocell13 U(0,0) 1 \SPIM:BSPIM:mosi_hs_reg\ \SPIM:BSPIM:mosi_hs_reg\/q \SPIM:BSPIM:mosi_hs_reg\/main_4 2.534
macrocell13 U(0,0) 1 \SPIM:BSPIM:mosi_hs_reg\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:ld_ident\/q \SPIM:BSPIM:ld_ident\/main_8 4.043
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,1) 1 \SPIM:BSPIM:ld_ident\ \SPIM:BSPIM:ld_ident\/clock_0 \SPIM:BSPIM:ld_ident\/q 1.250
macrocell17 U(1,1) 1 \SPIM:BSPIM:ld_ident\ \SPIM:BSPIM:ld_ident\/q \SPIM:BSPIM:ld_ident\/main_8 2.793
macrocell17 U(1,1) 1 \SPIM:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:cnt_enable\/q \SPIM:BSPIM:cnt_enable\/main_3 4.043
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,1) 1 \SPIM:BSPIM:cnt_enable\ \SPIM:BSPIM:cnt_enable\/clock_0 \SPIM:BSPIM:cnt_enable\/q 1.250
macrocell18 U(0,1) 1 \SPIM:BSPIM:cnt_enable\ \SPIM:BSPIM:cnt_enable\/q \SPIM:BSPIM:cnt_enable\/main_3 2.793
macrocell18 U(0,1) 1 \SPIM:BSPIM:cnt_enable\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:ld_ident\/q \SPIM:BSPIM:state_1\/main_9 4.044
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,1) 1 \SPIM:BSPIM:ld_ident\ \SPIM:BSPIM:ld_ident\/clock_0 \SPIM:BSPIM:ld_ident\/q 1.250
Route 1 \SPIM:BSPIM:ld_ident\ \SPIM:BSPIM:ld_ident\/q \SPIM:BSPIM:state_1\/main_9 2.794
macrocell10 U(1,1) 1 \SPIM:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:cnt_enable\/q \SPIM:BSPIM:BitCounter\/enable 4.078
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,1) 1 \SPIM:BSPIM:cnt_enable\ \SPIM:BSPIM:cnt_enable\/clock_0 \SPIM:BSPIM:cnt_enable\/q 1.250
Route 1 \SPIM:BSPIM:cnt_enable\ \SPIM:BSPIM:cnt_enable\/q \SPIM:BSPIM:BitCounter\/enable 2.828
count7cell U(0,1) 1 \SPIM:BSPIM:BitCounter\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:state_0\/q \SPIM:BSPIM:mosi_hs_reg\/main_2 4.238
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,0) 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/clock_0 \SPIM:BSPIM:state_0\/q 1.250
Route 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/q \SPIM:BSPIM:mosi_hs_reg\/main_2 2.988
macrocell13 U(0,0) 1 \SPIM:BSPIM:mosi_hs_reg\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:state_0\/q \SPIM:BSPIM:state_2\/main_2 4.532
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,0) 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/clock_0 \SPIM:BSPIM:state_0\/q 1.250
Route 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/q \SPIM:BSPIM:state_2\/main_2 3.282
macrocell9 U(1,0) 1 \SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ SPIM_IntClock
Source Destination Delay (ns)
\SPIM:BSPIM:state_2\/q MOSI(0)_PAD 32.442
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,0) 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/clock_0 \SPIM:BSPIM:state_2\/q 1.250
Route 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/q Net_19/main_0 7.016
macrocell4 U(0,0) 1 Net_19 Net_19/main_0 Net_19/q 3.350
Route 1 Net_19 Net_19/q MOSI(0)/pin_input 5.446
iocell2 P3[7] 1 MOSI(0) MOSI(0)/pin_input MOSI(0)/pad_out 15.380
Route 1 MOSI(0)_PAD MOSI(0)/pad_out MOSI(0)_PAD 0.000
Clock Clock path delay 0.000
Net_28/q SCK(0)_PAD 22.970
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(0,1) 1 Net_28 Net_28/clock_0 Net_28/q 1.250
Route 1 Net_28 Net_28/q SCK(0)/pin_input 6.190
iocell3 P0[0] 1 SCK(0) SCK(0)/pin_input SCK(0)/pad_out 15.530
Route 1 SCK(0)_PAD SCK(0)/pad_out SCK(0)_PAD 0.000
Clock Clock path delay 0.000