Static Timing Analysis

Project : ILI9341_LCD
Build Time : 03/06/16 20:13:32
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 5.00
VDDD : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 48.000 MHz 48.000 MHz 64.425 MHz
SPIM_IntClock CyHFCLK 24.000 MHz 24.000 MHz 48.132 MHz
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySYSCLK CySYSCLK 48.000 MHz 48.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 20.8333ns(48 MHz)
Affects clock : CyHFCLK
Source Destination FMax Delay (ns) Slack (ns) Violation
MISO(0)/fb \SPIM:BSPIM:sR8:Dp:u0\/route_si 64.425 MHz 15.522 5.311
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P2[3] 1 MISO(0) MISO(0)/in_clock MISO(0)/fb 4.047
Route 1 Net_573 MISO(0)/fb \SPIM:BSPIM:sR8:Dp:u0\/route_si 4.695
datapathcell1 U(1,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 6.780
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIM:BSPIM:sR8:Dp:u0\/so_comb \SPIM:BSPIM:mosi_pre_reg\/main_1 48.132 MHz 20.776 20.891
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ \SPIM:BSPIM:sR8:Dp:u0\/clock \SPIM:BSPIM:sR8:Dp:u0\/so_comb 8.300
Route 1 \SPIM:BSPIM:mosi_from_dp\ \SPIM:BSPIM:sR8:Dp:u0\/so_comb \SPIM:BSPIM:mosi_pre_reg_split_1\/main_3 3.375
macrocell7 U(0,0) 1 \SPIM:BSPIM:mosi_pre_reg_split_1\ \SPIM:BSPIM:mosi_pre_reg_split_1\/main_3 \SPIM:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \SPIM:BSPIM:mosi_pre_reg_split_1\ \SPIM:BSPIM:mosi_pre_reg_split_1\/q \SPIM:BSPIM:mosi_pre_reg\/main_1 2.241
macrocell13 U(1,0) 1 \SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SPIM:BSPIM:sR8:Dp:u0\/so_comb \SPIM:BSPIM:mosi_pre_reg\/main_0 48.139 MHz 20.773 20.894
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ \SPIM:BSPIM:sR8:Dp:u0\/clock \SPIM:BSPIM:sR8:Dp:u0\/so_comb 8.300
Route 1 \SPIM:BSPIM:mosi_from_dp\ \SPIM:BSPIM:sR8:Dp:u0\/so_comb \SPIM:BSPIM:mosi_pre_reg_split\/main_3 3.363
macrocell1 U(0,0) 1 \SPIM:BSPIM:mosi_pre_reg_split\ \SPIM:BSPIM:mosi_pre_reg_split\/main_3 \SPIM:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \SPIM:BSPIM:mosi_pre_reg_split\ \SPIM:BSPIM:mosi_pre_reg_split\/q \SPIM:BSPIM:mosi_pre_reg\/main_0 2.250
macrocell13 U(1,0) 1 \SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SPIM:BSPIM:RxStsReg\/status_6 56.051 MHz 17.841 23.826
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ \SPIM:BSPIM:sR8:Dp:u0\/clock \SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb 5.280
Route 1 \SPIM:BSPIM:rx_status_4\ \SPIM:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SPIM:BSPIM:rx_status_6\/main_5 3.186
macrocell6 U(1,1) 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/main_5 \SPIM:BSPIM:rx_status_6\/q 3.350
Route 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/q \SPIM:BSPIM:RxStsReg\/status_6 4.455
statusicell2 U(1,0) 1 \SPIM:BSPIM:RxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM:BSPIM:state_1\/q \SPIM:BSPIM:TxStsReg\/status_0 56.951 MHz 17.559 24.108
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,0) 1 \SPIM:BSPIM:state_1\ \SPIM:BSPIM:state_1\/clock_0 \SPIM:BSPIM:state_1\/q 1.250
Route 1 \SPIM:BSPIM:state_1\ \SPIM:BSPIM:state_1\/q \SPIM:BSPIM:tx_status_0\/main_1 7.230
macrocell4 U(1,1) 1 \SPIM:BSPIM:tx_status_0\ \SPIM:BSPIM:tx_status_0\/main_1 \SPIM:BSPIM:tx_status_0\/q 3.350
Route 1 \SPIM:BSPIM:tx_status_0\ \SPIM:BSPIM:tx_status_0\/q \SPIM:BSPIM:TxStsReg\/status_0 4.159
statusicell1 U(1,1) 1 \SPIM:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM:BSPIM:state_2\/q \SPIM:BSPIM:TxStsReg\/status_0 62.364 MHz 16.035 25.632
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(1,0) 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/clock_0 \SPIM:BSPIM:state_2\/q 1.250
Route 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/q \SPIM:BSPIM:tx_status_0\/main_0 5.706
macrocell4 U(1,1) 1 \SPIM:BSPIM:tx_status_0\ \SPIM:BSPIM:tx_status_0\/main_0 \SPIM:BSPIM:tx_status_0\/q 3.350
Route 1 \SPIM:BSPIM:tx_status_0\ \SPIM:BSPIM:tx_status_0\/q \SPIM:BSPIM:TxStsReg\/status_0 4.159
statusicell1 U(1,1) 1 \SPIM:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:mosi_pre_reg\/main_0 62.473 MHz 16.007 25.660
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 2.110
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:mosi_pre_reg_split\/main_6 4.787
macrocell1 U(0,0) 1 \SPIM:BSPIM:mosi_pre_reg_split\ \SPIM:BSPIM:mosi_pre_reg_split\/main_6 \SPIM:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \SPIM:BSPIM:mosi_pre_reg_split\ \SPIM:BSPIM:mosi_pre_reg_split\/q \SPIM:BSPIM:mosi_pre_reg\/main_0 2.250
macrocell13 U(1,0) 1 \SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:mosi_pre_reg\/main_1 62.473 MHz 16.007 25.660
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 2.110
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:mosi_pre_reg_split_1\/main_6 4.796
macrocell7 U(0,0) 1 \SPIM:BSPIM:mosi_pre_reg_split_1\ \SPIM:BSPIM:mosi_pre_reg_split_1\/main_6 \SPIM:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \SPIM:BSPIM:mosi_pre_reg_split_1\ \SPIM:BSPIM:mosi_pre_reg_split_1\/q \SPIM:BSPIM:mosi_pre_reg\/main_1 2.241
macrocell13 U(1,0) 1 \SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SPIM:BSPIM:state_2\/q \SPIM:BSPIM:mosi_pre_reg\/main_1 62.613 MHz 15.971 25.696
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(1,0) 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/clock_0 \SPIM:BSPIM:state_2\/q 1.250
Route 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/q \SPIM:BSPIM:mosi_pre_reg_split_1\/main_0 5.620
macrocell7 U(0,0) 1 \SPIM:BSPIM:mosi_pre_reg_split_1\ \SPIM:BSPIM:mosi_pre_reg_split_1\/main_0 \SPIM:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \SPIM:BSPIM:mosi_pre_reg_split_1\ \SPIM:BSPIM:mosi_pre_reg_split_1\/q \SPIM:BSPIM:mosi_pre_reg\/main_1 2.241
macrocell13 U(1,0) 1 \SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SPIM:BSPIM:state_2\/q \SPIM:BSPIM:mosi_pre_reg\/main_0 63.646 MHz 15.712 25.955
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell8 U(1,0) 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/clock_0 \SPIM:BSPIM:state_2\/q 1.250
Route 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/q \SPIM:BSPIM:mosi_pre_reg_split\/main_0 5.352
macrocell1 U(0,0) 1 \SPIM:BSPIM:mosi_pre_reg_split\ \SPIM:BSPIM:mosi_pre_reg_split\/main_0 \SPIM:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \SPIM:BSPIM:mosi_pre_reg_split\ \SPIM:BSPIM:mosi_pre_reg_split\/q \SPIM:BSPIM:mosi_pre_reg\/main_0 2.250
macrocell13 U(1,0) 1 \SPIM:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\SPIM:BSPIM:state_1\/q \SPIM:BSPIM:sR8:Dp:u0\/cs_addr_1 64.549 MHz 15.492 26.175
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,0) 1 \SPIM:BSPIM:state_1\ \SPIM:BSPIM:state_1\/clock_0 \SPIM:BSPIM:state_1\/q 1.250
Route 1 \SPIM:BSPIM:state_1\ \SPIM:BSPIM:state_1\/q \SPIM:BSPIM:sR8:Dp:u0\/cs_addr_1 7.942
datapathcell1 U(1,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 6.300
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
MISO(0)/fb \SPIM:BSPIM:sR8:Dp:u0\/route_si 7.435
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P2[3] 1 MISO(0) MISO(0)/in_clock MISO(0)/fb 2.740
Route 1 Net_573 MISO(0)/fb \SPIM:BSPIM:sR8:Dp:u0\/route_si 4.695
datapathcell1 U(1,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SPIM:BSPIM:load_cond\/q \SPIM:BSPIM:load_cond\/main_8 3.480
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 \SPIM:BSPIM:load_cond\ \SPIM:BSPIM:load_cond\/clock_0 \SPIM:BSPIM:load_cond\/q 1.250
macrocell14 U(1,0) 1 \SPIM:BSPIM:load_cond\ \SPIM:BSPIM:load_cond\/q \SPIM:BSPIM:load_cond\/main_8 2.230
macrocell14 U(1,0) 1 \SPIM:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
Net_29/q Net_29/main_3 3.547
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,1) 1 Net_29 Net_29/clock_0 Net_29/q 1.250
macrocell11 U(1,1) 1 Net_29 Net_29/q Net_29/main_3 2.297
macrocell11 U(1,1) 1 Net_29 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:mosi_from_dp_reg\/q \SPIM:BSPIM:mosi_hs_reg\/main_5 3.550
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,1) 1 \SPIM:BSPIM:mosi_from_dp_reg\ \SPIM:BSPIM:mosi_from_dp_reg\/clock_0 \SPIM:BSPIM:mosi_from_dp_reg\/q 1.250
Route 1 \SPIM:BSPIM:mosi_from_dp_reg\ \SPIM:BSPIM:mosi_from_dp_reg\/q \SPIM:BSPIM:mosi_hs_reg\/main_5 2.300
macrocell12 U(1,1) 1 \SPIM:BSPIM:mosi_hs_reg\ HOLD 0.000
Clock Skew 0.000
Net_653/q Net_653/main_3 3.552
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,1) 1 Net_653 Net_653/clock_0 Net_653/q 1.250
macrocell18 U(0,1) 1 Net_653 Net_653/q Net_653/main_3 2.302
macrocell18 U(0,1) 1 Net_653 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:mosi_hs_reg\/q \SPIM:BSPIM:mosi_hs_reg\/main_4 4.026
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,1) 1 \SPIM:BSPIM:mosi_hs_reg\ \SPIM:BSPIM:mosi_hs_reg\/clock_0 \SPIM:BSPIM:mosi_hs_reg\/q 1.250
macrocell12 U(1,1) 1 \SPIM:BSPIM:mosi_hs_reg\ \SPIM:BSPIM:mosi_hs_reg\/q \SPIM:BSPIM:mosi_hs_reg\/main_4 2.776
macrocell12 U(1,1) 1 \SPIM:BSPIM:mosi_hs_reg\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:cnt_enable\/q \SPIM:BSPIM:cnt_enable\/main_3 4.042
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(0,1) 1 \SPIM:BSPIM:cnt_enable\ \SPIM:BSPIM:cnt_enable\/clock_0 \SPIM:BSPIM:cnt_enable\/q 1.250
macrocell17 U(0,1) 1 \SPIM:BSPIM:cnt_enable\ \SPIM:BSPIM:cnt_enable\/q \SPIM:BSPIM:cnt_enable\/main_3 2.792
macrocell17 U(0,1) 1 \SPIM:BSPIM:cnt_enable\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:cnt_enable\/q \SPIM:BSPIM:BitCounter\/enable 4.048
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(0,1) 1 \SPIM:BSPIM:cnt_enable\ \SPIM:BSPIM:cnt_enable\/clock_0 \SPIM:BSPIM:cnt_enable\/q 1.250
Route 1 \SPIM:BSPIM:cnt_enable\ \SPIM:BSPIM:cnt_enable\/q \SPIM:BSPIM:BitCounter\/enable 2.798
count7cell U(0,1) 1 \SPIM:BSPIM:BitCounter\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:state_0\/q \SPIM:BSPIM:state_2\/main_2 4.815
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,0) 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/clock_0 \SPIM:BSPIM:state_0\/q 1.250
Route 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/q \SPIM:BSPIM:state_2\/main_2 3.565
macrocell8 U(1,0) 1 \SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:state_0\/q \SPIM:BSPIM:load_cond\/main_2 4.815
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,0) 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/clock_0 \SPIM:BSPIM:state_0\/q 1.250
Route 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/q \SPIM:BSPIM:load_cond\/main_2 3.565
macrocell14 U(1,0) 1 \SPIM:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:state_0\/q \SPIM:BSPIM:ld_ident\/main_2 4.862
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,0) 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/clock_0 \SPIM:BSPIM:state_0\/q 1.250
Route 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/q \SPIM:BSPIM:ld_ident\/main_2 3.612
macrocell16 U(0,0) 1 \SPIM:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ SPIM_IntClock
Source Destination Delay (ns)
\SPIM:BSPIM:state_1\/q MOSI(0)_PAD 34.563
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,0) 1 \SPIM:BSPIM:state_1\ \SPIM:BSPIM:state_1\/clock_0 \SPIM:BSPIM:state_1\/q 1.250
Route 1 \SPIM:BSPIM:state_1\ \SPIM:BSPIM:state_1\/q Net_19/main_1 7.230
macrocell3 U(1,1) 1 Net_19 Net_19/main_1 Net_19/q 3.350
Route 1 Net_19 Net_19/q MOSI(0)/pin_input 5.833
iocell2 P3[4] 1 MOSI(0) MOSI(0)/pin_input MOSI(0)/pad_out 16.900
Route 1 MOSI(0)_PAD MOSI(0)/pad_out MOSI(0)_PAD 0.000
Clock Clock path delay 0.000
Net_653/q SCK(0)_PAD 21.670
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,1) 1 Net_653 Net_653/clock_0 Net_653/q 1.250
Route 1 Net_653 Net_653/q SCK(0)/pin_input 6.200
iocell3 P3[6] 1 SCK(0) SCK(0)/pin_input SCK(0)/pad_out 14.220
Route 1 SCK(0)_PAD SCK(0)/pad_out SCK(0)_PAD 0.000
Clock Clock path delay 0.000