; ##############################################################################
; ##############################################################################
; ##############################################################################
ENC_INITIALISIERUNG:
	call ENC_WAIT_CLKRDY	; wait CLKRDY	
	call ENC_SOFT_RESET		; Reset			
	call ENC_CLKOUT_PIN		; CLKOUT-PIN (bei Bedarf)
	call ENC_LED_BLINKEN_ON
	call WAIT_1s
	call WAIT_1s
	call WAIT_1s
	call ENC_LED_BLINKEN_OFF
	;call ENC_INITIALISIERUNG_NACH_DATENBLATT
	call ENC_INITIALISIERUNG_NACH_BEN
;-------------------------------------------------------------------------------
	call ENC_MAC_ADRESSE_CHECK	
ret
; ##############################################################################
; ##############################################################################
; ##############################################################################
; Quelle: Ben's Hobby-Corner													
; http://members.home.nl/bzijlstra/software/examples/enc28j60.htm				
;																				
; Bemerkung:																	
; Die Originalversion stammt von Ben's Hobby-Corner Tutorial und wurde			
; entsprechend ergänzt und abgeändert.											
;																				
;																				
ENC_INITIALISIERUNG_NACH_BEN:
;(A)----------------------------------------------------------------------------
; 'initialize receive buffer													
; '16-bit transfers, must write low byte first									
; 'set receive buffer start address												
; Nextpacketptr = Rxstart_init													
; Value = Low(rxstart_init)														
; Call Enc28j60writecontrolregbyte(erxstl , Value)								
; Value = High(rxstart_init)													
; Call Enc28j60writecontrolregbyte(erxsth , Value)								
;																				
	ldi temp1,(ERXSTL)
	ldi temp2,Low(rxstart_init)	
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_CHECK_TEMP1_TEMP2 	; INP: temp1(cod+addr) temp2(data)				
	ldi temp1,(ERXSTH)
	ldi temp2,HIGH(rxstart_init)	
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_CHECK_TEMP1_TEMP2 	; INP: temp1(cod+addr) temp2(data)				
;(B)----------------------------------------------------------------------------
; 'set receive pointer address													
; Value = Low(rxstart_init)														
; Call Enc28j60writecontrolregbyte(erxrdptl , Value)							
; Value = High(rxstart_init)													
; Call Enc28j60writecontrolregbyte(erxrdpth , Value)							
;																				
	ldi temp1,(ERXRDPTL)
	ldi temp2,Low(rxstart_init)	
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_CHECK_TEMP1_TEMP2 	; INP: temp1(cod+addr) temp2(data)				
	ldi temp1,(ERXRDPTH)
	ldi temp2,HIGH(rxstart_init)	
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_CHECK_TEMP1_TEMP2 	; INP: temp1(cod+addr) temp2(data)				
;(C)----------------------------------------------------------------------------
; 'set receive buffer end														
; Value = Low(rxstop_init)														
; Call Enc28j60writecontrolregbyte(erxndl , Value)								
; Value = High(rxstop_init)														
; Call Enc28j60writecontrolregbyte(erxndh , Value)								
;																				
	ldi temp1,(ERXNDL)
	ldi temp2,Low(rxstop_init)	
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_CHECK_TEMP1_TEMP2 	; INP: temp1(cod+addr) temp2(data)				
	ldi temp1,(ERXNDH)
	ldi temp2,HIGH(rxstop_init)	
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_CHECK_TEMP1_TEMP2 	; INP: temp1(cod+addr) temp2(data)				
;(D)----------------------------------------------------------------------------
; 'set transmit buffer start													
; Value = Low(txstart_init)														
; Call Enc28j60writecontrolregbyte(etxstl , Value)								
; Value = High(txstart_init)													
; Call Enc28j60writecontrolregbyte(etxsth , Value)								
;																				
	ldi temp1,(ETXSTL)
	ldi temp2,Low(txstart_init)	
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_CHECK_TEMP1_TEMP2 	; INP: temp1(cod+addr) temp2(data)				
	ldi temp1,(ETXSTH)
	ldi temp2,HIGH(txstart_init)	
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_CHECK_TEMP1_TEMP2 	; INP: temp1(cod+addr) temp2(data)				
;(E)----------------------------------------------------------------------------
; 'enable MAC receive															
; Value.macon1_marxen = 1														
; Value.macon1_txpaus = 1														
; Value.macon1_rxpaus = 1														
; Call Enc28j60writecontrolregbyte(macon1 , Value)								
;																				
	ldi temp1,(MACON1)
	ldi temp2,(1<<MACON1_TXPAUS)|(1<<MACON1_RXPAUS)|(0<<MACON1_PASSALL)|(1<<MACON1_MARXEN)
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_CHECK_TEMP1_TEMP2 	; INP: temp1(cod+addr) temp2(data)				
;(F)----------------------------------------------------------------------------
; 'enable automatic padding and CRC operations									
; Value.macon3_padcfg0 = 1														
; Value.macon3_txcrcen = 1														
; Value.macon3_frmlnen = 1														
; Call Enc28j60writecontrolregbyte(macon3 , Value)								
;																				
	ldi temp1,(MACON3)
	ldi temp2,(0<<MACON3_PADCFG2)|(0<<MACON3_PADCFG1)|(1<<MACON3_PADCFG0)|(1<<MACON3_TXCRCEN)|(0<<MACON3_PHDREN)|(0<<MACON3_HFRMEN)|(1<<MACON3_FRMLNEN)|(0<<MACON3_FULDPX)
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_CHECK_TEMP1_TEMP2 	; INP: temp1(cod+addr) temp2(data)				
;(G)----------------------------------------------------------------------------
; 'set inter-frame gap (non-back-to-back)										
; Call Enc28j60writecontrolregbyte(maipgl , &H12)								
; Call Enc28j60writecontrolregbyte(maipgh , &H0C)								
;																				
	ldi temp1,(MAIPGL)
	ldi temp2,(0x12)	; h12
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_CHECK_TEMP1_TEMP2 	; INP: temp1(cod+addr) temp2(data)				
	ldi temp1,(MAIPGH)
	ldi temp2,(0x0C)	; h0C
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_CHECK_TEMP1_TEMP2 	; INP: temp1(cod+addr) temp2(data)				
;(H)----------------------------------------------------------------------------
; 'set inter-frame gap (back-to-back)											
; Call Enc28j60writecontrolregbyte(mabbipg , &H12)								
;																				
	ldi temp1,(MABBIPG)
	ldi temp2,(0x12)	; h12
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_CHECK_TEMP1_TEMP2 	; INP: temp1(cod+addr) temp2(data)				
;(I)----------------------------------------------------------------------------
; 'set the maximum packet size which the controller will accept					
; Value = Low(max_framelen)														
; Call Enc28j60writecontrolregbyte(mamxfll , Value)								
; Value = High(max_framelen)													
; Call Enc28j60writecontrolregbyte(mamxflh , Value)								
;																				
	ldi temp1,(MAMXFLL)
	ldi temp2,LOW(MAX_FRAMELEN)
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_CHECK_TEMP1_TEMP2 	; INP: temp1(cod+addr) temp2(data)				
	ldi temp1,(MAMXFLH)
	ldi temp2,HIGH(MAX_FRAMELEN)
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_CHECK_TEMP1_TEMP2 	; INP: temp1(cod+addr) temp2(data)				
;(J)----------------------------------------------------------------------------
; Call Enc28j60writecontrolregbyte(maadr5 , Ethaddr0)							
; Call Enc28j60writecontrolregbyte(maadr4 , Ethaddr1)							
; Call Enc28j60writecontrolregbyte(maadr3 , Ethaddr2)							
; Call Enc28j60writecontrolregbyte(maadr2 , Ethaddr3)							
; Call Enc28j60writecontrolregbyte(maadr1 , Ethaddr4)							
; Call Enc28j60writecontrolregbyte(maadr0 , Ethaddr5)							
;																				
	rcall ENC_MAC_ADRESSE_SET
;(K)----------------------------------------------------------------------------
; 'no loopback of transmitted frames											
; Call Enc28j60writephyword(phcon2 , Phcon2_hdldis)								
;																				
	ldi temp1,(PHCON2)
	ldi temp2,LOW (0x0100)
	ldi temp3,HIGH(0x0100)
	rcall ENC_SPI_WRITE_PHY_REGISTER_TEMP1_TEMP2_TEMP3; INP: temp1(phy.addr) temp2(data) temp3(data)	
;(L)----------------------------------------------------------------------------
; 'enable interrupts															
; Value.eie_intie = 1															
; Value.eie_pktie = 1															
; Call Enc28j60bitfield_set(eie , Value)										
;																				
	ldi temp1,(EIE)
	ldi temp2,(1<<EIE_INTIE)| (1<<EIE_PKTIE)|(0<<EIE_DMAIE)|(0<<EIE_LINKIE)|(0<<EIE_TXIE)|(0<<EIE_TXERIE)|(0<<EIE_RXERIE)
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_CHECK_TEMP1_TEMP2 	; INP: temp1(cod+addr) temp2(data)				
;(M)----------------------------------------------------------------------------
; 'enable packet reception														
; Value.econ1_rxen = 1															
; Call Enc28j60bitfield_set(econ1 , Value)										
;																				
	ldi temp1,(ECON1)
	ldi temp2,(0<<ECON1_TXRST)|(0<<ECON1_RXRST)|(0<<ECON1_DMAST)|(0<<ECON1_CSUMEN)|(0<<ECON1_TXRTS)|(1<<ECON1_RXEN)|(0<<ECON1_BSEL1)|(0<<ECON1_BSEL0)
	rcall ENC_SPI_SET_BIT_TEMP1_TEMP2					; INP: temp1(cod+addr) temp2(data)	
ret
; ##############################################################################
; ##############################################################################
; ##############################################################################
; ##############################################################################
; ##############################################################################
; ##############################################################################
ENC_INITIALISIERUNG_NACH_DATENBLATT:
;-------------------------------------------------------------------------------
; 1. Set the MARXEN bit in MACON1 to enable the MAC to receive frames. 														
; If using full duplex, most applications should also set TXPAUS and RXPAUS to allow IEEE defined flow control to function.	
	ldi temp1,(MACON1)
	ldi temp2,(1<<MACON1_TXPAUS)|(1<<MACON1_RXPAUS)|(0<<MACON1_PASSALL)|(1<<MACON1_MARXEN)
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2		; INP: temp1(cod+addr) temp2(data)				
;-------------------------------------------------------------------------------
; 2. Configure the PADCFG, TXCRCEN and FULDPX bits of MACON3. 					
; Most applications should enable automatic padding to at least	60 bytes and always append a valid CRC. For convenience, many applications may 
; wish to set the FRMLNEN bit as well to enable frame length status reporting. The FULDPX bit should be set if the application will be connected to a full-duplex configured remote node; otherwise, it  should be left clear.															
	ldi temp1,(MACON3)
	ldi temp2,(1<<MACON3_PADCFG2)|(1<<MACON3_PADCFG1)|(1<<MACON3_PADCFG0)|(1<<MACON3_TXCRCEN)|(0<<MACON3_PHDREN)|(0<<MACON3_HFRMEN)|(1<<MACON3_FRMLNEN)|(0<<MACON3_FULDPX)
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
;-------------------------------------------------------------------------------
; 3. Configure the bits in MACON4. For conformance to the IEEE 802.3 standard, set the DEFER bit.		
	ldi temp1,(MACON4)
	ldi temp2,(1<<MACON4_DEFER)|(0<<MACON4_BPEN)|(0<<MACON4_NOBKOFF)
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
;-------------------------------------------------------------------------------
; 4. Program the MAMXFL registers with the maximum frame length to be permitted to be received			
; or transmitted. Normal network nodes are designed to handle packets that are 1518 bytes or less.		
	ldi temp1,(MAMXFLL)
	ldi temp2,LOW(1518)
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
	ldi temp1,(MAMXFLH)
	ldi temp2,HIGH(1518)
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
;-------------------------------------------------------------------------------
; 5. Configure the Back-to-Back Inter-Packet Gap								
; register, MABBIPG. Most applications will program								
; this register with 15h when Full-Duplex										
; mode is used and 12h when Half-Duplex mode is used.							
;																				
	ldi temp1,(MABBIPG)
	ldi temp2,(0x12)
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
;-------------------------------------------------------------------------------
; 6. Configure the Non-Back-to-Back Inter-Packet								
; Gap register low byte, MAIPGL. Most applications								
; will program this register with 12h.											
	ldi temp1,(MAIPGL)
	ldi temp2,(0x12)
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
;-------------------------------------------------------------------------------
; 7. If half duplex is used, the Non-Back-to-Back Inter-Packet Gap register high byte, 					
; MAIPGH, should be programmed. Most applications will program this register to 0Ch.					
	ldi temp1,(MAIPGH)
	ldi temp2,(0x0C)
	rcall ENC_SPI_WRITE_CONTROL_REGISTER_TEMP1_TEMP2	; INP: temp1(cod+addr) temp2(data)				
;-------------------------------------------------------------------------------
; 8. If Half-Duplex mode is used, program the Retransmission and Collision Window registers, MACLCON1 and MACLCON2. 
; Most applications will not need to change the default Reset values.												
; If the network is spread over exceptionally long cables, the default value of MACLCON2 may need to be increased.	
;																				


;-------------------------------------------------------------------------------
; 9. Program the local MAC address into the MAADR1:MAADR6 registers.			
	rcall ENC_MAC_ADRESSE_SET
;-------------------------------------------------------------------------------
	ldi temp1,(ECON1)
	ldi temp2,(0<<ECON1_TXRST)|(0<<ECON1_RXRST)|(0<<ECON1_DMAST)|(0<<ECON1_CSUMEN)|(0<<ECON1_TXRTS)|(1<<ECON1_RXEN)|(0<<ECON1_BSEL1)|(0<<ECON1_BSEL0)
	rcall ENC_SPI_SET_BIT_TEMP1_TEMP2					; INP: temp1(cod+addr) temp2(data)	
ret
; ##############################################################################
; ##############################################################################
; ##############################################################################
; ##############################################################################
; ##############################################################################
; ##############################################################################