library ieee;
use ieee.std_logic_1164.all;

entity Lauflicht is
	generic (n: integer := 50000000); -- => 1 Hz
	port( 
		clk: in std_logic;
		y1: inout std_logic;
		q1: buffer std_logic;
		q2: buffer std_logic;
		q3: buffer std_logic;
		s1: in bit;
		s2: in bit;
		s3: in bit;
		l0,l1,l2,l3,l4,l5,l6: inout bit
		);
end Lauflicht;

architecture behavior of Lauflicht is
	signal Z1: integer range 0 to n-1;
	signal Z2: integer range 0 to n-1;
	signal Z3: integer range 0 to n-1;
	signal leds: bit_vector(6 downto 0);
	signal zwischen1: bit_vector(6 downto 0);
	signal zwischen2: bit_vector(6 downto 0);
	
	begin
	
	leds <= l0 & l1 & l2 & l3 & l4 & l5 & l6;
	
	
--Clock

	clock1: process (clk,s1,s2,s3,q1,q2,q3)
	begin
		if(s1='1' and s2='0' and s3='0') then
			if (rising_edge(clk)) then  				--L/H Flanke --clock1
			
				if Z1 = n then Z1 <= 0;
					else Z1 <= Z1 +1 ;
				end if;
				
				
				if Z1 = 0 then 
					q1 <= not q1; 				
				end if;
				
			end if;
			y1 <= q1;
		end if;
		
		if(s1='0' and s2='1' and s3='0') then
			if (rising_edge(clk)) then  				--L/H Flanke --clock 2
			
				if Z2 = 2 * n then Z2 <= 0;
					else Z2 <= Z2 +1 ;
				end if;
				
				
				if Z2 = 0 then 
					q2 <= not q2; 				
				end if;
				
			end if;
			y1 <= q2;
		end if;
		
		if(s1='0' and s2='0' and s3='1') then
			if (rising_edge(clk)) then  				--L/H Flanke --clock 3  
			
				if Z3 = 3 * n then Z3 <= 0;
					else Z3 <= Z3 +1 ;
				end if;
				
				
				if Z3 = 0 then 
					q3 <= not q3; 				
				end if;
				
			end if;
			y1 <= q3;
		end if;
	end process clock1;

	

	
-- Prozess des Lauflichts	
	lauflicht: process (y1)
		begin
			if (y1='1') then
				if(zwischen1="0000001") then
						zwischen1 <= "1000000";
						leds <= zwischen1;
				else
						zwischen2 <= zwischen1 srl 1;
						leds <= zwischen2;
				end if;
			else
			end if;
	end process lauflicht;
		
end behavior;