; macro_basic.inc ; 08.05.2021 ; Minimalistische Variante, temp geaendert fuer r24,r25 ; ;=== Alternativnamen fuer Register ======================================= ; templ = r24, temph = r25, ; temp = r24, ;========================================================================= ;=== Basic-Funktionen fuer Start ========================================= ;========================================================================= ; setstack 4c, 8b ; ramnull 18b ; regnull: 156c 10b ;========================================================================= ;=== IO-RAM-REG-Konst ==================================================== ;========================================================================= ; outi @0 Ziel, @1 Data, temp wird benutzt, 2-3c, 4-6b ; outi16 @0 Ziel, @1 Data16, temp wird benutzt, 4-6c, 8-12b ; outi24 @0 Ziel, @1 Data24, temp wird benutzt, 6-9c, 12-18b ; outi32 @0 Ziel, @1 Data32, temp wird benutzt, 12c, 24b ; outi40 @0 Ziel, @1 Data40, temp wird benutzt, 15c, 30b ; outi48 @0 Ziel, @1 Data48, temp wird benutzt, 18c, 36b ; outi56 @0 Ziel, @1 Data54, temp wird benutzt, 21c, 42b ; outi64 @0 Ziel, @1 Data64, temp wird benutzt, 24c, 48b ; ; inreg @0 r0-r31, @1 IO-RAM, 1-2c, 2-4b ; inreg16 @0 r0-r30, @1 IO-RAM, 2-4c, 4-8b ; inreg24 @0 r0-r29, @1 IO-RAM, 3-6c, 6-12b ; inreg32 @0 r0-r28, @1 IO-RAM, 8c, 16b ; inreg40 @0 r0-r27, @1 IO-RAM, 10c, 20b ; inreg48 @0 r0-r26, @1 IO-RAM, 12c, 24b ; inreg56 @0 r0-r25, @1 IO-RAM, 14c, 28b ; inreg64 @0 r0-r24, @1 IO-RAM, 16c, 32b ; ; outreg @0 IO-RAM, @1 r0-r31, 1-2c, 2-4b ; outreg16 @0 IO-RAM, @1 r0-r30, 2-4c, 4-8b ; outreg24 @0 IO-RAM, @1 r0-r29, 3-6c, 6-12b ; outreg32 @0 IO-RAM, @1 r0-r28, 8c, 16b ; outreg40 @0 IO-RAM, @1 r0-r27, 10c, 20b ; outreg48 @0 IO-RAM, @1 r0-r26. 12c, 24b ; outreg56 @0 IO-RAM, @1 r0-r25. 14c, 28b ; outreg64 @0 IO-RAM, @1 r0-r24, 16c, 32b ; ; ldireg @0 r0-r31, @1 Data8, 1-2c, 2-4b, wenn r0-r15, temp benutzt ; ldireg16 @0 r0-r30, @1 Data16, 2-4c, 4-8b, wenn r0-r15, temp benutzt ; ldireg24 @0 r0-r29, @1 Data24, 3-6c, 6-12b, wenn r0-r15, temp benutzt ; ldireg32 @0 r0-r28, @1 Data32, 4-8c, 8-16b, wenn r0-r15, temp benutzt ; ldireg40 @0 r0-r27, @1 Data40, 5-10c, 10-20b, wenn r0-r15, temp benutzt ; ldireg48 @0 r0-r26, @1 Data48, 6-12c, 12-24b, wenn r0-r15, temp benutzt ; ldireg56 @0 r0-r25, @1 Data56, 7-14c, 14-28b, wenn r0-r15, temp benutzt ; ldireg64 @0 r0-r24, @1 Data64, 8-16c, 16-32b, wenn r0-r15, temp benutzt ; ; xchreg @0, @1 reg @0 <-> @1 3c,6b ; ; subireg ; @0 r0-r31, @1 Data8, @2 temp-Oberreg, 1-2c, 2-4b, ; wenn r0-r15, @2 benutzt ; subireg16 ; @0 r0-r30, @1 Data16, @2 temp-Oberreg, 2-4c, 4-8b ; wenn r0-r15, @2 benutzt ; sbcireg ; @0 r0-r31, @1 Data8, @2 temp-Oberreg, 1-2c, 2-4b, ; wenn r0-r15, @2 benutzt ; sbcireg16 ; @0 r0-r30, @1 Data16, @2 temp-Oberreg, 2-4c, 4-8b ; wenn r0-r15, @2 benutzt ; adireg ; @0 r0-r31, @1 Data8, @2 temp-Oberreg, 1-2c, 2-4b, ; wenn r0-r15, @2 benutzt ; adireg16 ; @0 r0-r30, @1 Data16, @2 temp-Oberreg, 2-4c, 4-8b ; wenn r0-r15, @2 benutzt ; adcireg ; @0 r0-r31, @1 Data8, @2 temp-Oberreg, 1-2c, 2-4b, ; wenn r0-r15, @2 benutzt ; adcireg16 ; @0 r0-r30, @1 Data16, @2 temp-Oberreg, 2-4c, 4-8b ; wenn r0-r15, @2 benutzt ; cpireg ; @0 r0-r31, @1 Data8, @2 temp-Oberreg, 1-2c, 2-4b, ; wenn r0-r15, @2 benutzt ; cpireg16 ; @0 r0-r30, @1 Data16, @2 temp-Oberreg, 3-4c, 6-8b ; cpcireg ; @0 r0-r31, @1 Data8, @2 temp-Oberreg, 1-2c, 2-4b ; ;========================================================================= ;=== REG Rotieren ======================================================== ;========================================================================= ; rol16 @0 r0-r30 2c, 4b ; rol24 @0 r0-r29 3c, 6b ; rol32 @0 r0-r28 4c, 8b ; rol40 @0 r0-r27 5c, 10b ; rol48 @0 r0-r26 6c, 12b ; rol56 @0 r0-r25 7c, 14b ; rol64 @0 r0-r24 8c, 16b ; ; ror16 @0 r0-r30 2c, 4b ; ror24 @0 r0-r29 3c, 6b ; ror32 @0 r0-r28 4c, 8b ; ror40 @0 r0-r27 5c, 10b ; ror48 @0 r0-r26 6c, 12b ; ror56 @0 r0-r25 7c, 14b ; ror64 @0 r0-r24 8c, 16b ; ; lsl16 @0 r0-r30 2c, 4b ; lsl24 @0 r0-r29 3c, 6b ; lsl32 @0 r0-r28 4c, 8b ; lsl40 @0 r0-r27 5c, 10b ; lsl48 @0 r0-r26 6c, 12b ; lsl56 @0 r0-r25 7c, 14b ; lsl64 @0 r0-r24 8c, 16b ; ; lsr16 @0 r0-r30 2c, 4b ; lsr24 @0 r0-r29 3c, 6b ; lsr32 @0 r0-r28 4c, 8b ; lsr40 @0 r0-r27 5c, 10b ; lsr48 @0 r0-r26 6c, 12b ; lsr56 @0 r0-r25 7c, 14b ; lsr64 @0 r0-r24 8c, 16b ; ; asr16 @0 r0-r30 2c, 4b ; asr24 @0 r0-r29 3c, 6b ; asr32 @0 r0-r28 4c, 8b ; asr40 @0 r0-r27 5c, 10b ; asr48 @0 r0-r26 6c, 12b ; asr56 @0 r0-r25 7c, 14b ; asr64 @0 r0-r24 8c, 16b ; ; rl @0 r0-r31 4c, 8b ; rl16 @0 r0-r30 5c, 10b ; rl24 @0 r0-r29 6c, 12b ; rl32 @0 r0-r28 7c, 14b ; rl40 @0 r0-r27 8c, 16b ; rl48 @0 r0-r26 9c, 18b ; rl56 @0 r0-r25 10c, 20b ; rl64 @0 r0-r24 11c, 22b ; ; rr @0 r0-r31 4c, 8b ; rr16 @0 r0-r30 5c, 10b ; rr24 @0 r0-r29 6c, 12b ; rr32 @0 r0-r28 7c, 14b ; rr40 @0 r0-r27 8c, 16b ; rr48 @0 r0-r26 9c, 18b ; rr56 @0 r0-r25 10c, 20b ; rr64 @0 r0-r24 11c, 22b ; ; setcarry @0 Reg, @1 Bitnummer, C <- Bit, 3c, 6b ; ;========================================================================= ;=== Bitarbeit =========================================================== ;========================================================================= ;=== Bits in SREG === ; Bitnummer (0...7): SREG_C, SREG_Z, SREG_N, SREG_V, ; SREG_S, SREG_H, SREG_T, SREG_I ; set_sregb @0 Bitnummer 1c 2b ; clr_sregb @0 Bitnummer 1c 2b ; inv_sregb @0 Bitnummer 3-4c 8b ; in_c @0 r0-r31, @1 Bitnummer (0...7) c <- Reg.bit ; mov_tc T <- C ; ;=== Bits in r0-r31 === ; set_regbit @0 r0-r31, @1 Bitnummer (0...7) ; wenn r0-r15, temp benutzt 1-2c 2-4b ; clr_regbit @0 r0-r31, @1 Bitnummer (0...7) ; wenn r0-r15, temp benutzt 1-2c 2-4b ; inv_regbit @0 r0-r31, @1 Bitnummer (0...7) ; wenn r0-r15, temp benutzt 4-5-5-6c 8-10b ; andtreg @0 r0-r31, @1 Bitnummer (0...7) T &= Reg.bit ; nandtreg @0 r0-r31, @1 Bitnummer (0...7) T ~&= Reg.bit ; ortreg @0 r0-r31, @1 Bitnummer (0...7) T |= Reg.bit ; nortreg @0 r0-r31, @1 Bitnummer (0...7) T ~|= Reg.bit ; exortreg @0 r0-r31, @1 Bitnummer (0...7) T ^= Reg.bit ; exnortreg @0 r0-r31, @1 Bitnummer (0...7) T ~^= Reg.bit ; ;=== Bits in IO-RAM === ; set_membit @0 IO-MEM Adr, @1 Bitnummer (0...7) ; wenn @0>0x1f, temp benutzt 2-3-5c 2-6-10b ; clr_membit @0 IO-MEM Adr, @1 Bitnummer (0...7) ; wenn @0>0x1f, temp benutzt 2-3-5c 2-6-10b ; inv_membit @0 IO-MEM Adr, @1 Bitnummer (0...7) ; wenn @0>0x1f, temp benutzt, 5-6-8-9c 10-18b ; ; andtmem @0 Adr-Ziel, @1 bit-Ziel (0...7), T &= Bit ; nandtmem @0 Adr-Ziel, @1 bit-Ziel (0...7), T ~&= Bit ; ortmem @0 Adr-Ziel, @1 bit-Ziel (0...7), T |= Bit ; nortmem @0 Adr-Ziel, @1 bit-Ziel (0...7), T ~|= Bit ; exortmem @0 Adr-Ziel, @1 bit-Ziel (0...7), T ^= Bit ; exnortmem @0 Adr-Ziel, @1 bit-Ziel (0...7), T ~^= Bit ; ;=== Bits in-out === ; inbitmem @0 Adr, @1 bit (0...7), temp benutzt 2-3c 4-6b ; bit -> T, weiter mit brts, brtc ; outbitmem @0 Adr, @1 bit (0...7), temp benutzt if Adr >= 0x20 ; T ->bit 3-5c 6-10b ; movbitmem @0 Adr-Ziel, @1 bit-Ziel (0...7), ; @2 Adr-Quelle, @3 bit-Quelle (0...7), ; temp benutzt if Adr >= 0x20 ; bit ->T ->bit 5-8c 10-16b ; ;========================================================================= ;=== Spruenge ============================================================ ;========================================================================= ; Bitnummer (0...7): SREG_C, SREG_Z, SREG_N, SREG_V, ; SREG_S, SREG_H, SREG_T, SREG_I ; jb @0 Bitnummer in SREG, @1 Label. Wenn Bit=1, springen 2-3c, 4b ; jnb @0 Bitnummer in SREG, @1 Label. Wenn Bit=0, springen 2-3c, 4b ; jmpb @0 Bitnummer in SREG, @1 Label. Wenn Bit=1, springen 2-4c, 6b ; jmpnb @0 Bitnummer in SREG, @1 Label. Wenn Bit=0, springen 2-4c, 6b ; ; jbr @0 r0-r31, @1 bit (0...7), @2 Label. Wenn Bit=1, springen 2-3c, 4b ; jnbr @0 r0-r31, @1 bit (0...7), @2 Label. Wenn Bit=0, springen 2-3c, 4b ; jmpbr @0 r0-r31, @1 bit (0...7), @2 Label. Wenn Bit=1, springen 3-4c, 6b ; jmpnbr @0 r0-r31, @1 bit (0...7), @2 Label. Wenn Bit=0, springen 3-4c, 6b ; ; jbm @0 IO-RAM-Adr, @1 bit (0...7), @2 Label. Wenn Bit=1, springen ; bei @0>0x20 temp wird benutzt. 2-5c, 4-8b ; jnbm @0 IO-RAM-Adr, @1 bit (0...7), @2 Label. Wenn Bit=0, springen ; bei @0>0x20 temp wird benutzt. 2-5c, 4-8b ; jmpbm @0 IO-RAM-Adr, @1 bit (0...7), @2 Label. Wenn Bit=1, springen ; bei @0>0x20 temp wird benutzt. 3-6c, 6-10b ; jmpnbm @0 IO-RAM-Adr, @1 bit (0...7), @2 Label. Wenn Bit=0, springen ; bei @0>0x20 temp wird benutzt. 3-6c, 6-10b ; ; jmptabindex @0 Tab16 fuer jmp, Index in Z 13c, 16b, temp benutzt ; ;========================================================================= ; ; Bitnummer (0...7): SREG_C, SREG_Z, SREG_N, SREG_V, ; SREG_S, SREG_H, SREG_T, SREG_I ; rcallb @0 Bitnummer in SREG, @1 Label. Wenn Bit=1, springen 2-4c, 4b ; rcallnb @0 Bitnummer in SREG, @1 Label. Wenn Bit=0, springen 2-4c, 4b ; callb @0 Bitnummer in SREG, @1 Label. Wenn Bit=1, springen 2-5c, 6b ; callnb @0 Bitnummer in SREG, @1 Label. Wenn Bit=0, springen 2-5c, 6b ; ; rcallbr @0 r0-r31, @1 bit (0...7), @2 Label. Wenn Bit=1, springen 2-4c, 4b ; rcallnbr @0 r0-r31, @1 bit (0...7), @2 Label. Wenn Bit=0, springen 2-4c, 4b ; callbr @0 r0-r31, @1 bit (0...7), @2 Label. Wenn Bit=1, springen 3-5c, 6b ; callnbr @0 r0-r31, @1 bit (0...7), @2 Label. Wenn Bit=0, springen 3-5c, 6b ; ; rcallbm @0 IO-RAM-Adr, @1 bit (0...7), @2 Label. Wenn Bit=1, springen ; bei @0>0x20 temp wird benutzt. 2-6c, 4-8b ; rcallnbm @0 IO-RAM-Adr, @1 bit (0...7), @2 Label. Wenn Bit=0, springen ; bei @0>0x20 temp wird benutzt. 2-6c, 4-8b ; callbm @0 IO-RAM-Adr, @1 bit (0...7), @2 Label. Wenn Bit=1, springen ; bei @0>0x20 temp wird benutzt. 3-7c, 6-10b ; callnbm @0 IO-RAM-Adr, @1 bit (0...7), @2 Label. Wenn Bit=0, springen ; bei @0>0x20 temp wird benutzt. 3-7c, 6-10b ; ; calltabindex @0 Tab16 fuer jmp, Index in Z 14c, 16b, temp benutzt ; ;========================================================================= ;========================================================================= #ifndef _MACRO_BASIC_ #define _MACRO_BASIC_ ;========================================================================= ;=== macro_def =========================================================== #ifndef templ #define templ r24 #endif #ifndef temph #define temph r25 #endif #ifndef temp #define temp r24 #endif #ifndef BYTE_H #define BYTE_H #define byte5(x) (x>>32)&0xff #define byte6(x) (x>>40)&0xff #define byte7(x) (x>>48)&0xff #define byte8(x) (x>>56)&0xff #endif /* BYTE_H */ #ifndef _INTEMP_ #define _INTEMP_ .macro intemp ; @0 IO-RAM, 1-2c, 2-4b .if @0<0x40 in temp, @0 .else lds temp, @0 .endif .endm #endif /* INTEMP */ #ifndef _OUTTEMP_ #define _OUTTEMP_ .macro outtemp ; @0 IO-RAM, 1-2c, 2-4b .if @0<0x40 out @0, temp .else sts @0, temp .endif .endm #endif /* OUTTEMP */ ;================================================================ ;====fuer Unterscheiden zwischen oberen und unteren Register ==== ;================================================================ #ifndef OBEREREG #define OBEREREG r16_mpr || r17_mpr || r18_mpr || r19_mpr || r20_mpr || r21_mpr || r22_mpr || r23_mpr || r24_mpr || r25_mpr || r26_mpr || r27_mpr || r28_mpr || r29_mpr || r30_mpr || r31_mpr #endif #ifndef _SETR_ #define _SETR_ .macro setr16 ; fuer 1 Byte, wo nur zwischen r0-r15 und r16-r31 zu unterscheiden ist .set r16_mpr = 0 .set r17_mpr = 0 .set r18_mpr = 0 .set r19_mpr = 0 .set r20_mpr = 0 .set r21_mpr = 0 .set r22_mpr = 0 .set r23_mpr = 0 .set r24_mpr = 0 .set r25_mpr = 0 .set r26_mpr = 0 .set r27_mpr = 0 .set r28_mpr = 0 .set r29_mpr = 0 .set r30_mpr = 0 .set r31_mpr = 0 .set xl_mpr = 0 .set xh_mpr = 0 .set yl_mpr = 0 .set yh_mpr = 0 .set zl_mpr = 0 .set zh_mpr = 0 .set temp_mpr = 0 .set templ_mpr = 0 .set temph_mpr = 0 .set X_mpr = 0 .set Y_mpr = 0 .set Z_mpr = 0 .endm .macro setr ; fuer mehrere Byte, wo die Register einzeln zu behandeln sind .set r0_mpr = 0 .set r1_mpr = 0 .set r2_mpr = 0 .set r3_mpr = 0 .set r4_mpr = 0 .set r5_mpr = 0 .set r6_mpr = 0 .set r7_mpr = 0 .set r8_mpr = 0 .set r9_mpr = 0 .set r10_mpr = 0 .set r11_mpr = 0 .set r12_mpr = 0 .set r13_mpr = 0 .set r14_mpr = 0 .set r15_mpr = 0 .set r16_mpr = 0 .set r17_mpr = 0 .set r18_mpr = 0 .set r19_mpr = 0 .set r20_mpr = 0 .set r21_mpr = 0 .set r22_mpr = 0 .set r23_mpr = 0 .set r24_mpr = 0 .set r25_mpr = 0 .set r26_mpr = 0 .set r27_mpr = 0 .set r28_mpr = 0 .set r29_mpr = 0 .set r30_mpr = 0 .set r31_mpr = 0 .set xl_mpr = 0 .set xh_mpr = 0 .set yl_mpr = 0 .set yh_mpr = 0 .set zl_mpr = 0 .set zh_mpr = 0 .set temp_mpr = 0 .set templ_mpr = 0 .set temph_mpr = 0 .set X_mpr = 0 .set Y_mpr = 0 .set Z_mpr = 0 .endm #endif /* _SETR_ */ ;========================================================================= ;========================================================================= ;========================================================================= ;=== Basic-Funktionen fuer Start ========================================= ;========================================================================= #ifdef _4433DEF_INC_ #define SPL SP #endif #ifdef _TN26DEF_INC_ #define SPL SP #endif .set _MITSPH_ = 0 #ifdef _TN4DEF_INC_ .set _MITSPH_ = 1 #elif defined _TN5DEF_INC_ .set _MITSPH_ = 1 #elif defined _TN9DEF_INC_ .set _MITSPH_ = 1 #elif defined _TN10DEF_INC_ .set _MITSPH_ = 1 #elif defined _TN20DEF_INC_ .set _MITSPH_ = 1 #endif .macro setstack .if SRAM_SIZE > 0 .if (SRAM_SIZE > 128) || _MITSPH_ ldi r16, low(RAMEND) ; 4c, 8b Stack out SPL, r16 ldi r16, high(RAMEND) out SPH, r16 .else ldi r16, RAMEND ; 2c, 4b out SPL, r16 .endif .endif .endm .macro ramnull ; RAM -> 0, 18b ldi ZL,Low(SRAM_START) ; RAM_Anfangsadresse -> Z ldi ZH,High(SRAM_START) clr r16 ; r16 ->0 $ramnull_: st Z+,r16 ; 0 -> RAM-Zelle, naechste cpi ZH,High(RAMEND+1) ; Ende? brne $ramnull_ ; Wenn nicht, weiter cpi ZL,Low(RAMEND+1) ; auch untere byte zu Ende? brne $ramnull_ .endm .macro regnull ; 156c 10b ; Reg ->0 ldi ZL, 30 ; Adresse von oberen Reg clr ZH ; Null dec ZL ; Adresse-- st Z, ZH ; Reg ->0 brne PC-2 ; wiederholen bis r0 .endm ;========================================================================= ;=== IO-RAM-REG-Konst 8-16 =============================================== ;========================================================================= .macro outi ; @0 Ziel, @1 Data, temp wird benutzt, 2-3c, 4-6b ldi temp, @1 ; 2-3c, 4-6b .if @0 < 0x40 out @0, temp .else sts @0, temp .endif .endm .macro outi16 ; @0 Ziel, @1 Data16, temp wird benutzt, 4-6c, 8-12b outi @0, low(@1) outi @0+1, high(@1) .endm .macro outi24 ; @0 Ziel, @1 Data24, temp wird benutzt, outi @0, low(@1) ; 6-9c, 12-18b outi @0+1, high(@1) outi @0+2, byte3(@1) .endm .macro outi32 ; @0 Ziel, @1 Data32, temp wird benutzt, outi @0, low(@1) ; 12c, 24b outi @0+1, high(@1) outi @0+2, byte3(@1) outi @0+3, byte4(@1) .endm .macro outi40 ; @0 Ziel, @1 Data40, temp wird benutzt, outi @0, low(@1) ; 15c, 30b outi @0+1, high(@1) outi @0+2, byte3(@1) outi @0+3, byte4(@1) outi @0+4, byte5(@1) .endm .macro outi48 ; @0 Ziel, @1 Data48, temp wird benutzt, outi @0, low(@1) ; 18c, 36b outi @0+1, high(@1) outi @0+2, byte3(@1) outi @0+3, byte4(@1) outi @0+4, byte5(@1) outi @0+5, byte6(@1) .endm .macro outi56 ; @0 Ziel, @1 Data56, temp wird benutzt, outi @0, low(@1) ; 21c, 42b outi @0+1, high(@1) outi @0+2, byte3(@1) outi @0+3, byte4(@1) outi @0+4, byte5(@1) outi @0+5, byte6(@1) outi @0+6, byte7(@1) .endm .macro outi64 ; @0 Ziel, @1 Data64, temp wird benutzt, outi @0, low(@1) ; 24c, 48b outi @0+1, high(@1) outi @0+2, byte3(@1) outi @0+3, byte4(@1) outi @0+4, byte5(@1) outi @0+5, byte6(@1) outi @0+6, byte7(@1) outi @0+7, byte8(@1) .endm ;========================================================================= .macro xchreg ; @0, @1 reg @0 <-> @1 3c,6b eor @0, @1 eor @1, @0 eor @0, @1 .endm ;========================================================================= .macro ldireg ; @0 r0-r31, @1 Data8, 1-2c, 2-4b, wenn r0-r15, temp benutzt setr16 .set @0_mpr = 1 .if OBEREREG ldi @0,@1 .else ldi temp,@1 mov @0,temp .endif .endm .macro inreg ; @0 r0-r31, @1 IO-RAM, 1-2c, 2-4b .if @1<0x40 in @0, @1 .else lds @0, @1 .endif .endm .macro outreg ; @0 IO-RAM, @1 r0-r31, 1-2c, 2-4b .if @0<0x40 out @0, @1 .else sts @0, @1 .endif .endm .macro subireg ; @0 r0-r31, @1 Data8, @2 temp-Oberreg, 1-2c, 2-4b, setr16 ; wenn r0-r15, @2 benutzt .set @0_mpr = 1 .if OBEREREG subi @0,@1 .else ldi @2,@1 sub @0,@2 .endif .endm .macro sbcireg ; @0 r0-r31, @1 Data8, @2 temp-Oberreg, 1-2c, 2-4b, setr16 ; wenn r0-r15, @2 benutzt .set @0_mpr = 1 .if OBEREREG sbci @0,@1 .else ldi @2,@1 sbc @0,@2 .endif .endm .macro adireg ; @0 r0-r31, @1 Data8, @2 temp-Oberreg, 1-2c, 2-4b, subireg @0,-@1,@2 ; wenn r0-r15, @2 benutzt .endm .macro adcireg ; @0 r0-r31, @1 Data8, @2 temp-Oberreg, 1-2c, 2-4b, sbcireg @0,-@1,@2 ; wenn r0-r15, @2 benutzt .endm .macro cpireg ; @0 r0-r31, @1 Data8, @2 temp-Oberreg, 1-2c, 2-4b, setr16 ; wenn r0-r15, @2 benutzt .set @0_mpr = 1 .if OBEREREG cpi @0,@1 .else ldi @2,@1 cp @0,@2 .endif .endm .macro cpcireg ; @0 r0-r31, @1 Data8, @2 temp-Oberreg, 1-2c, 2-4b ldi @2,@1 cpc @0,@2 .endm ;========================================================================= .macro setcarry ; @0 Reg, @1 Bitnummer, C <- Bit, 3c, 6b clc sbrc @0,@1 sec .endm .macro rl ; @0 r0-r31 4c, 8b setcarry @0,7 rol @0 .endm .macro rr ; @0 r0-r31 4c, 8b setcarry @0,0 ror @0 .endm ;========================================================================= ;=== Bitarbeit =========================================================== ;========================================================================= ;=== Bits in SREG ===== ; Bitnummer (0...7): SREG_C, SREG_Z, SREG_N, SREG_V, ; SREG_S, SREG_H, SREG_T, SREG_I .macro set_sregb ; @0 Bitnummer 1c 2b .if @1 > 7 .error "Macro set_sregb Bitnummer zu gross" .else bset @0 .endif .endm .macro clr_sregb ; @0 Bitnummer 1c 2b .if @1 > 7 .error "Macro clr_sregb Bitnummer zu gross" .else bclr @0 .endif .endm .macro inv_sregb ; @0 Bitnummer 3-4c 8b .if @1 > 7 .error "Macro inv_sregb Bitnummer zu gross" .else brbc @0, PC+3 bclr @0 rjmp PC+2 bset @0 .endif .endm ;=== Bits in r0-r31 === .macro set_regbit ; @0 r0-r31, @1 Bitnummer (0...7) ; wenn r0-r15, temp benutzt .if @1 > 7 .error "Macro set_regbit Bitnummer zu gross" .else setr16 .set @0_mpr = 1 .if OBEREREG sbr @0, 1<<@1 .else ldi temp, 1<<@1 or @0, temp .endif .endif .endm .macro clr_regbit ; @0 r0-r31, @1 Bitnummer (0...7) ; wenn r0-r15, temp benutzt .if @1 > 7 .error "Macro clr_regbit Bitnummer zu gross" .else setr16 .set @0_mpr = 1 .if OBEREREG cbr @0, 1<<@1 .else ldi temp, ~(1<<@1) and @0, temp .endif .endif .endm .macro inv_regbit ; @0 r0-r31, @1 Bitnummer (0...7) ; wenn r0-r15, temp benutzt 4-5-5-6c 8-10b .if @1 > 7 .error "Macro inv_regbit Bitnummer zu gross" .else sbrs @0, @1 rjmp $m1 clr_regbit @0, @1 rjmp $m2 $m1: set_regbit @0, @1 $m2: .endif .endm .macro in_c ; @0 r0-r31, @1 Bitnummer (0...7) .if @ > 7 ; c <- Reg.bit .error "Macro in_c Bitnummer zu gross" .else sbrs @0, @1 rjmp PC+3 sec rjmp PC+2 clc .endif .endm .macro mov_tc ; T <- C brcc PC+3 set rjmp PC+2 clt .endm .macro andtreg ; @0 r0-r31, @1 Bitnummer (0...7) .if @ > 7 ; T &= Reg.bit .error "Macro andtreg Bitnummer zu gross" .else sbrs @0, @1 clt .endif .endm .macro nandtreg ; @0 r0-r31, @1 Bitnummer (0...7) .if @ > 7 ; T ~&= Reg.bit .error "Macro nandtreg Bitnummer zu gross" .else brtc PC+5 sbrs @0, @1 rjmp PC+3 clt rjmp PC+2 set .endif .endm .macro ortreg ; @0 r0-r31, @1 Bitnummer (0...7) .if @ > 7 ; T |= Reg.bit .error "Macro ortreg Bitnummer zu gross" .else sbrc @0, @1 set .endif .endm .macro nortreg ; @0 r0-r31, @1 Bitnummer (0...7) .if @ > 7 ; T ~|= Reg.bit .error "Macro nortreg Bitnummer zu gross" .else brts PC+5 sbrc @0, @1 rjmp PC+3 set rjmp PC+2 clt .endif .endm .macro exortreg ; @0 r0-r31, @1 Bitnummer (0...7) .if @ > 7 ; T ^= Reg.bit .error "Macro exortreg Bitnummer zu gross" .else sbrs @0, @1 rjmp PC+5 ; T lassen brtc PC+3 ; T inv clt rjmp PC+2 set @0 .endif .endm .macro exnortreg ; @0 r0-r31, @1 Bitnummer (0...7) .if @ > 7 ; T ~^= Reg.bit .error "Macro exnortreg Bitnummer zu gross" .else sbrc @0, @1 rjmp PC+5 ; T lassen brtc PC+3 ; T inv clt rjmp PC+2 set @0 .endif .endm ;=== Bits in IO-RAM === .macro set_membit ; @0 IO-MEM Adr, @1 Bitnummer (0...7) ; wenn @0>0x1f, temp benutzt 2-3-5c 2-6-10b .if @ > 7 .error "Macro set_membit Bitnummer zu gross" .else .if @0 < 0x20 sbi @0, @1 .else intemp @0 sbr temp, 1<<@1 outtemp @0 .endif .endif .endm .macro clr_membit ; @0 IO-MEM Adr, @1 Bitnummer (0...7) ; wenn @0>0x1f, temp benutzt 2-3-5c 2-6-10b .if @ > 7 .error "Macro clr_membit Bitnummer zu gross" .else .if @0 < 0x20 cbi @0, @1 .else intemp @0 cbr temp, 1<<@1 outtemp @0 .endif .endif .endm .macro inv_membit ; @0 IO-MEM Adr, @1 Bitnummer (0...7) ; wenn @0>0x1f, temp benutzt, 5-6-8-9c 10-18b .if @ > 7 .error "Macro inv_membit Bitnummer zu gross" .else .if @0 < 0x20 sbis @0, @1 rjmp PC+3 cbi @0, @1 rjmp PC+2 sbi @0, @1 .else intemp @0 sbrs temp, @1 rjmp PC+3 cbr temp, 1<<@1 rjmp PC+2 sbr temp, 1<<@1 outtemp @0 .endif .endif .endm ;=== Bits in-out === .macro inbitmem ; @0 Adr, @1 bit (0...7), temp benutzt 2-3c 4-6b ; bit -> T, weiter mit brts, brtc intemp @0 bst temp, @1 .endm .macro outbitmem ; @0 Adr, @1 bit (0...7), temp benutzt if Adr >= 0x20 ; T ->bit 3-5c 6-10b intemp @0 bld temp, @1 outtemp @0 .endm .macro movbitmem ; @0 Adr-Ziel, @1 bit-Ziel (0...7), ; @2 Adr-Quelle, @3 bit-Quelle (0...7), ; temp benutzt if Adr >= 0x20 ; bit ->T ->bit 5-8c 10-16b inbitmem @2,@3 outbitmem @0,@1 .endm .macro andtmem ; @0 Adr-Ziel, @1 bit-Ziel (0...7), T &= Bit .if @ > 7 .error "Macro andtmem Bitnummer zu gross" .else .if @0 < 0x20 sbis @0, @1 clt .else intemp @0 sbrs temp, @1 clt .endif .endif .endm .macro nandtmem ; @0 Adr-Ziel, @1 bit-Ziel (0...7), T ~&= Bit .if @ > 7 .error "Macro nandtmem Bitnummer zu gross" .else .if @0 < 0x20 brtc PC+5 sbis @0, @1 rjmp PC+3 clt rjmp PC+2 set .else brtc $m1 intemp @0 sbrs temp, @1 rjmp PC+3 clt rjmp PC+2 $m1: set .endif .endif .endm .macro ortmem ; @0 Adr-Ziel, @1 bit-Ziel (0...7), T |= Bit .if @ > 7 .error "Macro ortmem Bitnummer zu gross" .else .if @0 < 0x20 sbic @0, @1 set .else intemp @0 sbrc temp, @1 set .endif .endif .endm .macro nortmem ; @0 Adr-Ziel, @1 bit-Ziel (0...7), T ~|= Bit .if @ > 7 .error "Macro nortmem Bitnummer zu gross" .else .if @0 < 0x20 brts PC+5 sbic @0, @1 rjmp PC+3 set rjmp PC+2 clt .else brts $m1 intemp @0 sbrc temp, @1 rjmp PC+3 set rjmp PC+2 $m1: clt .endif .endif .endm .macro exortmem ; @0 Adr-Ziel, @1 bit-Ziel (0...7), T ^= Bit .if @ > 7 .error "Macro exortmem Bitnummer zu gross" .else .if @0 < 0x20 sbis @0, @1 rjmp PC+5 ; T lassen brtc PC+3 ; T inv clt rjmp PC+2 set @0 .else intemp @0 sbrs temp, @1 rjmp PC+5 ; T lassen brtc PC+3 ; T inv clt rjmp PC+2 set @0 .endif .endif .endm .macro exnortmem ; @0 Adr-Ziel, @1 bit-Ziel (0...7), T ~^= Bit .if @ > 7 .error "Macro exnortmem Bitnummer zu gross" .else .if @0 < 0x20 sbic @0, @1 rjmp PC+5 ; T lassen brtc PC+3 ; T inv clt rjmp PC+2 set @0 .else intemp @0 sbrc temp, @1 rjmp PC+5 ; T lassen brtc PC+3 ; T inv clt rjmp PC+2 set @0 .endif .endif .endm ;========================================================================= ;=== Spruenge ============================================================ ;========================================================================= ; Bitnummer (0...7): SREG_C, SREG_Z, SREG_N, SREG_V, ; SREG_S, SREG_H, SREG_T, SREG_I .macro jb ; @0 Bitnummer in SREG, @1 Label. Wenn Bit=1, springen 2-3c, 4b .if @0 > 7 .error "Macro jb Bitnummer zu gross" .else brbc @0,pc+2 rjmp @1 .endif .endm .macro jnb ; @0 Bitnummer in SREG, @1 Label. Wenn Bit=0, springen 2-3c, 4b .if @0 > 7 .error "Macro jnb Bitnummer zu gross" .else brbs @0,pc+2 rjmp @1 .endif .endm .macro jmpb ; @0 Bitnummer in SREG, @1 Label. Wenn Bit=1, springen 2-4c, 6b .if @0 > 7 .error "Macro jmpb Bitnummer zu gross" .else brbc @0,pc+2 jmp @1 .endif .endm .macro jmpnb ; @0 Bitnummer in SREG, @1 Label. Wenn Bit=0, springen 2-4c, 6b .if @0 > 7 .error "Macro jmpnb Bitnummer zu gross" .else brbs @0,pc+2 jmp @1 .endif .endm ;========================================================================= .macro jbr ; @0 r0-r31, @1 bit (0...7), @2 Label. Wenn Bit=1, springen .if @1 > 7 .error "Macro jb Bitnummer zu gross" .else sbrc @0, @1 ; 2-3c, 4b rjmp @2 .endif .endm .macro jnbr ; @0 r0-r31, @1 bit (0...7), @2 Label. Wenn Bit=0, springen .if @1 > 7 .error "Macro jb Bitnummer zu gross" .else sbrs @0, @1 ; 2-3c, 4b rjmp @2 .endif .endm .macro jmpbr ; @0 r0-r31, @1 bit (0...7), @2 Label. Wenn Bit=1, springen .if @1 > 7 .error "Macro jmpbr Bitnummer zu gross" .else sbrc @0, @1 ; 3-4c, 6b jmp @2 .endif .endm .macro jmpnbr ; @0 r0-r31, @1 bit (0...7), @2 Label. Wenn Bit=0, springen .if @1 > 7 .error "Macro jmpnbr Bitnummer zu gross" .else sbrs @0, @1 ; 3-4c, 6b jmp @2 .endif .endm ;========================================================================= .macro jbm ; @0 IO-RAM-Adr, @1 bit (0...7), @2 Label. Wenn Bit=1, springen ; bei @0>0x20 temp wird benutzt. 2-5c, 4-8b .if @1 > 7 .error "Macro jbm Bitnummer zu gross" .else .if @0 < 0x20 sbic @0, @1 .else intemp @0 sbrc temp, @1 .endif rjmp @2 .endif .endm .macro jnbm ; @0 IO-RAM-Adr, @1 bit (0...7), @2 Label. Wenn Bit=0, springen ; bei @0>0x20 temp wird benutzt. 2-5c, 4-8b .if @1 > 7 .error "Macro jnbm Bitnummer zu gross" .else .if @0 < 0x20 sbis @0, @1 .else intemp @0 sbrs temp, @1 .endif rjmp @2 .endif .endm .macro jmpbm ; @0 IO-RAM-Adr, @1 bit (0...7), @2 Label. Wenn Bit=1, springen ; bei @0>0x20 temp wird benutzt. 3-6c, 6-10b .if @1 > 7 .error "Macro jmpbm Bitnummer zu gross" .else .if @0 < 0x20 sbic @0, @1 .else intemp @0 sbrc temp, @1 .endif jmp @2 .endif .endm .macro jmpnbm ; @0 IO-RAM-Adr, @1 bit (0...7), @2 Label. Wenn Bit=0, springen ; bei @0>0x20 temp wird benutzt. 3-6c, 6-10b .if @1 > 7 .error "Macro jmpnbm Bitnummer zu gross" .else .if @0 < 0x20 sbis @0, @1 .else intemp @0 sbrs temp, @1 .endif jmp @2 .endif .endm ;========================================================================= .macro jmptabindex ; @0 Tab16 fuer jmp, Index in Z 13c, 16b, temp benutzt lsl zl rol zh subi zl,low(-@0*2) sbci zh, high(-@0*2) lpm temp, Z+ lpm r31, Z mov r30,temp ijmp .endm ;========================================================================= ;=== Call, Rcall ========================================================= ;========================================================================= ; Bitnummer (0...7): SREG_C, SREG_Z, SREG_N, SREG_V, ; SREG_S, SREG_H, SREG_T, SREG_I .macro rcallb ; @0 Bitnummer in SREG, @1 Label. Wenn Bit=1, springen 2-4c, 4b .if @0 > 7 .error "Macro rcallb Bitnummer zu gross" .else brbc @0,pc+2 rcall @1 .endif .endm .macro rcallnb ; @0 Bitnummer in SREG, @1 Label. Wenn Bit=0, springen 2-4c, 4b .if @0 > 7 .error "Macro rcallnb Bitnummer zu gross" .else brbs @0,pc+2 rcall @1 .endif .endm .macro callb ; @0 Bitnummer in SREG, @1 Label. Wenn Bit=1, springen 2-5c, 6b .if @0 > 7 .error "Macro callb Bitnummer zu gross" .else brbc @0,pc+2 call @1 .endif .endm .macro callnb ; @0 Bitnummer in SREG, @1 Label. Wenn Bit=0, springen 2-5c, 6b .if @0 > 7 .error "Macro callnb Bitnummer zu gross" .else brbs @0,pc+2 call @1 .endif .endm ;========================================================================= .macro rcallbr ; @0 r0-r31, @1 bit (0...7), @2 Label. Wenn Bit=1, springen 2-4c, 4b .if @1 > 7 .error "Macro rcallbr Bitnummer zu gross" .else sbrc @0, @1 ; 2-4c, 4b rcall @2 .endif .endm .macro rcallnbr ; @0 r0-r31, @1 bit (0...7), @2 Label. Wenn Bit=0, springen 2-4c, 4b .if @1 > 7 .error "Macro rcallnbr Bitnummer zu gross" .else sbrs @0, @1 ; 2-4c, 4b rcall @2 .endif .endm .macro callbr ; @0 r0-r31, @1 bit (0...7), @2 Label. Wenn Bit=1, springen 3-5c, 6b .if @1 > 7 .error "Macro callbr Bitnummer zu gross" .else sbrc @0, @1 ; 2-4c, 4b call @2 .endif .endm .macro callnbr ; @0 r0-r31, @1 bit (0...7), @2 Label. Wenn Bit=0, springen 3-5c, 6b .if @1 > 7 .error "Macro callnbr Bitnummer zu gross" .else sbrs @0, @1 ; 2-4c, 4b call @2 .endif .endm ;========================================================================= .macro rcallbm ; @0 IO-RAM-Adr, @1 bit (0...7), @2 Label. Wenn Bit=1, springen ; bei @0>0x20 temp wird benutzt. 2-6c, 4-8b .if @1 > 7 .error "Macro rcallbm Bitnummer zu gross" .else .if @0 < 0x20 sbic @0, @1 .else intemp @0 sbrc temp, @1 .endif rcall @2 .endif .endm .macro rcallnbm ; @0 IO-RAM-Adr, @1 bit (0...7), @2 Label. Wenn Bit=0, springen ; bei @0>0x20 temp wird benutzt. 2-6c, 4-8b .if @1 > 7 .error "Macro rcallnbm Bitnummer zu gross" .else .if @0 < 0x20 sbis @0, @1 .else intemp @0 sbrs temp, @1 .endif rcall @2 .endif .endm .macro callbm ; @0 IO-RAM-Adr, @1 bit (0...7), @2 Label. Wenn Bit=1, springen ; bei @0>0x20 temp wird benutzt. 3-7c, 6-10b .if @1 > 7 .error "Macro callbm Bitnummer zu gross" .else .if @0 < 0x20 sbic @0, @1 .else intemp @0 sbrc temp, @1 .endif call @2 .endif .endm .macro callnbm ; @0 IO-RAM-Adr, @1 bit (0...7), @2 Label. Wenn Bit=0, springen ; bei @0>0x20 temp wird benutzt. 3-7c, 6-10b .if @1 > 7 .error "Macro callnbm Bitnummer zu gross" .else .if @0 < 0x20 sbis @0, @1 .else intemp @0 sbrs temp, @1 .endif call @2 .endif .endm ;========================================================================= .macro calltabindex ; @0 Tab16 fuer jmp, Index in Z 14c, 16b, temp benutzt lsl zl rol zh subi zl,low(-@0*2) sbci zh, high(-@0*2) lpm temp, Z+ lpm r31, Z mov r30,temp icall .endm ;========================================================================= ;=== ldireg ============================================================== ;========================================================================= .macro ldireg16 ; @0 r0-r30, @1 Data16, 2-4c, 4-8b, wenn r0-r15, temp benutzt setr .set @0_mpr = 1 .if r0_mpr ldireg r0,low(@1) ldireg r1,high(@1) .elif r1_mpr ldireg r1,low(@1) ldireg r2,high(@1) .elif r2_mpr ldireg r2,low(@1) ldireg r3,high(@1) .elif r3_mpr ldireg r3,low(@1) ldireg r4,high(@1) .elif r4_mpr ldireg r4,low(@1) ldireg r5,high(@1) .elif r5_mpr ldireg r5,low(@1) ldireg r6,high(@1) .elif r6_mpr ldireg r6,low(@1) ldireg r7,high(@1) .elif r7_mpr ldireg r7,low(@1) ldireg r8,high(@1) .elif r8_mpr ldireg r8,low(@1) ldireg r9,high(@1) .elif r9_mpr ldireg r9,low(@1) ldireg r10,high(@1) .elif r10_mpr ldireg r10,low(@1) ldireg r11,high(@1) .elif r11_mpr ldireg r11,low(@1) ldireg r12,high(@1) .elif r12_mpr ldireg r12,low(@1) ldireg r13,high(@1) .elif r13_mpr ldireg r13,low(@1) ldireg r14,high(@1) .elif r14_mpr ldireg r14,low(@1) ldireg r15,high(@1) .elif r15_mpr ldireg r15,low(@1) ldireg r16,high(@1) .elif r16_mpr ldireg r16,low(@1) ldireg r17,high(@1) .elif r17_mpr ldireg r17,low(@1) ldireg r18,high(@1) .elif r18_mpr ldireg r18,low(@1) ldireg r19,high(@1) .elif r19_mpr ldireg r19,low(@1) ldireg r20,high(@1) .elif r20_mpr ldireg r20,low(@1) ldireg r21,high(@1) .elif r21_mpr ldireg r21,low(@1) ldireg r22,high(@1) .elif r22_mpr ldireg r22,low(@1) ldireg r23,high(@1) .elif r23_mpr ldireg r23,low(@1) ldireg r24,high(@1) .elif r24_mpr || temp_mpr || templ_mpr ldireg r24,low(@1) ldireg r25,high(@1) .elif r25_mpr || temph_mpr ldireg r25,low(@1) ldireg r26,high(@1) .elif r26_mpr || xl_mpr || X_mpr ldireg r26,low(@1) ldireg r27,high(@1) .elif r27_mpr || xh_mpr ldireg r27,low(@1) ldireg r28,high(@1) .elif r28_mpr || yl_mpr || Y_mpr ldireg r28,low(@1) ldireg r29,high(@1) .elif r29_mpr || yh_mpr ldireg r29,low(@1) ldireg r30,high(@1) .elif r30_mpr || zl_mpr || Z_mpr ldireg r30,low(@1) ldireg r31,high(@1) .else .error "Macro ldireg16 reg zu gross" .endif .endm .macro ldireg24 ; @0 r0-r29, @1 Data24, 3-6c, 6-12b, wenn r0-r15, temp benutzt setr .set @0_mpr = 1 .if r0_mpr ldireg r0,low(@1) ldireg r1,high(@1) ldireg r2,byte3(@1) .elif r1_mpr ldireg r1,low(@1) ldireg r2,high(@1) ldireg r3,byte3(@1) .elif r2_mpr ldireg r2,low(@1) ldireg r3,high(@1) ldireg r4,byte3(@1) .elif r3_mpr ldireg r3,low(@1) ldireg r4,high(@1) ldireg r5,byte3(@1) .elif r4_mpr ldireg r4,low(@1) ldireg r5,high(@1) ldireg r6,byte3(@1) .elif r5_mpr ldireg r5,low(@1) ldireg r6,high(@1) ldireg r7,byte3(@1) .elif r6_mpr ldireg r6,low(@1) ldireg r7,high(@1) ldireg r8,byte3(@1) .elif r7_mpr ldireg r7,low(@1) ldireg r8,high(@1) ldireg r9,byte3(@1) .elif r8_mpr ldireg r8,low(@1) ldireg r9,high(@1) ldireg r10,byte3(@1) .elif r9_mpr ldireg r9,low(@1) ldireg r10,high(@1) ldireg r11,byte3(@1) .elif r10_mpr ldireg r10,low(@1) ldireg r11,high(@1) ldireg r12,byte3(@1) .elif r11_mpr ldireg r11,low(@1) ldireg r12,high(@1) ldireg r13,byte3(@1) .elif r12_mpr ldireg r12,low(@1) ldireg r13,high(@1) ldireg r14,byte3(@1) .elif r13_mpr ldireg r13,low(@1) ldireg r14,high(@1) ldireg r15,byte3(@1) .elif r14_mpr ldireg r14,low(@1) ldireg r15,high(@1) ldireg r16,byte3(@1) .elif r15_mpr ldireg r15,low(@1) ldireg r16,high(@1) ldireg r17,byte3(@1) .elif r16_mpr ldireg r16,low(@1) ldireg r17,high(@1) ldireg r18,byte3(@1) .elif r17_mpr ldireg r17,low(@1) ldireg r18,high(@1) ldireg r19,byte3(@1) .elif r18_mpr ldireg r18,low(@1) ldireg r19,high(@1) ldireg r20,byte3(@1) .elif r19_mpr ldireg r19,low(@1) ldireg r20,high(@1) ldireg r21,byte3(@1) .elif r20_mpr ldireg r20,low(@1) ldireg r21,high(@1) ldireg r22,byte3(@1) .elif r21_mpr ldireg r21,low(@1) ldireg r22,high(@1) ldireg r23,byte3(@1) .elif r22_mpr ldireg r22,low(@1) ldireg r23,high(@1) ldireg r24,byte3(@1) .elif r23_mpr ldireg r23,low(@1) ldireg r24,high(@1) ldireg r25,byte3(@1) .elif r24_mpr ldireg r24,low(@1) ldireg r25,high(@1) ldireg r26,byte3(@1) .elif r25_mpr ldireg r25,low(@1) ldireg r26,high(@1) ldireg r27,byte3(@1) .elif r26_mpr ldireg r26,low(@1) ldireg r27,high(@1) ldireg r28,byte3(@1) .elif r27_mpr ldireg r27,low(@1) ldireg r28,high(@1) ldireg r29,byte3(@1) .elif r28_mpr ldireg r28,low(@1) ldireg r29,high(@1) ldireg r30,byte3(@1) .elif r29_mpr ldireg r29,low(@1) ldireg r30,high(@1) ldireg r31,byte3(@1) .else .error "Macro ldireg24 reg zu gross" .endif .endm .macro ldireg32 ; @0 r0-r28, @1 Data32, 4-8c, 8-16b, wenn r0-r15, temp benutzt setr .set @0_mpr = 1 .if r0_mpr ldireg r0,low(@1) ldireg r1,high(@1) ldireg r2,byte3(@1) ldireg r3,byte4(@1) .elif r1_mpr ldireg r1,low(@1) ldireg r2,high(@1) ldireg r3,byte3(@1) ldireg r4,byte4(@1) .elif r2_mpr ldireg r2,low(@1) ldireg r3,high(@1) ldireg r4,byte3(@1) ldireg r5,byte4(@1) .elif r3_mpr ldireg r3,low(@1) ldireg r4,high(@1) ldireg r5,byte3(@1) ldireg r6,byte4(@1) .elif r4_mpr ldireg r4,low(@1) ldireg r5,high(@1) ldireg r6,byte3(@1) ldireg r7,byte4(@1) .elif r5_mpr ldireg r5,low(@1) ldireg r6,high(@1) ldireg r7,byte3(@1) ldireg r8,byte4(@1) .elif r6_mpr ldireg r6,low(@1) ldireg r7,high(@1) ldireg r8,byte3(@1) ldireg r9,byte4(@1) .elif r7_mpr ldireg r7,low(@1) ldireg r8,high(@1) ldireg r9,byte3(@1) ldireg r10,byte4(@1) .elif r8_mpr ldireg r8,low(@1) ldireg r9,high(@1) ldireg r10,byte3(@1) ldireg r11,byte4(@1) .elif r9_mpr ldireg r9,low(@1) ldireg r10,high(@1) ldireg r11,byte3(@1) ldireg r12,byte4(@1) .elif r10_mpr ldireg r10,low(@1) ldireg r11,high(@1) ldireg r12,byte3(@1) ldireg r13,byte4(@1) .elif r11_mpr ldireg r11,low(@1) ldireg r12,high(@1) ldireg r13,byte3(@1) ldireg r14,byte4(@1) .elif r12_mpr ldireg r12,low(@1) ldireg r13,high(@1) ldireg r14,byte3(@1) ldireg r15,byte4(@1) .elif r13_mpr ldireg r13,low(@1) ldireg r14,high(@1) ldireg r15,byte3(@1) ldireg r16,byte4(@1) .elif r14_mpr ldireg r14,low(@1) ldireg r15,high(@1) ldireg r16,byte3(@1) ldireg r17,byte4(@1) .elif r15_mpr ldireg r15,low(@1) ldireg r16,high(@1) ldireg r17,byte3(@1) ldireg r18,byte4(@1) .elif r16_mpr ldireg r16,low(@1) ldireg r17,high(@1) ldireg r18,byte3(@1) ldireg r19,byte4(@1) .elif r17_mpr ldireg r17,low(@1) ldireg r18,high(@1) ldireg r19,byte3(@1) ldireg r20,byte4(@1) .elif r18_mpr ldireg r18,low(@1) ldireg r19,high(@1) ldireg r20,byte3(@1) ldireg r21,byte4(@1) .elif r19_mpr ldireg r19,low(@1) ldireg r20,high(@1) ldireg r21,byte3(@1) ldireg r22,byte4(@1) .elif r20_mpr ldireg r20,low(@1) ldireg r21,high(@1) ldireg r22,byte3(@1) ldireg r23,byte4(@1) .elif r21_mpr ldireg r21,low(@1) ldireg r22,high(@1) ldireg r23,byte3(@1) ldireg r24,byte4(@1) .elif r22_mpr ldireg r22,low(@1) ldireg r23,high(@1) ldireg r24,byte3(@1) ldireg r25,byte4(@1) .elif r23_mpr ldireg r23,low(@1) ldireg r24,high(@1) ldireg r25,byte3(@1) ldireg r26,byte4(@1) .elif r24_mpr ldireg r24,low(@1) ldireg r25,high(@1) ldireg r26,byte3(@1) ldireg r27,byte4(@1) .elif r25_mpr ldireg r25,low(@1) ldireg r26,high(@1) ldireg r27,byte3(@1) ldireg r28,byte4(@1) .elif r26_mpr ldireg r26,low(@1) ldireg r27,high(@1) ldireg r28,byte3(@1) ldireg r29,byte4(@1) .elif r27_mpr ldireg r27,low(@1) ldireg r28,high(@1) ldireg r29,byte3(@1) ldireg r30,byte4(@1) .elif r28_mpr ldireg r28,low(@1) ldireg r29,high(@1) ldireg r30,byte3(@1) ldireg r31,byte4(@1) .else .error "Macro ldireg32 reg zu gross" .endif .endm .macro ldireg40 ; @0 r0-r27, @1 Data40, 5-10c, 10-20b, wenn r0-r15, temp benutzt setr .set @0_mpr = 1 .if r0_mpr ldireg r0,low(@1) ldireg r1,high(@1) ldireg r2,byte3(@1) ldireg r3,byte4(@1) ldireg r4,byte5(@1) .elif r1_mpr ldireg r1,low(@1) ldireg r2,high(@1) ldireg r3,byte3(@1) ldireg r4,byte4(@1) ldireg r5,byte5(@1) .elif r2_mpr ldireg r2,low(@1) ldireg r3,high(@1) ldireg r4,byte3(@1) ldireg r5,byte4(@1) ldireg r6,byte5(@1) .elif r3_mpr ldireg r3,low(@1) ldireg r4,high(@1) ldireg r5,byte3(@1) ldireg r6,byte4(@1) ldireg r7,byte5(@1) .elif r4_mpr ldireg r4,low(@1) ldireg r5,high(@1) ldireg r6,byte3(@1) ldireg r7,byte4(@1) ldireg r8,byte5(@1) .elif r5_mpr ldireg r5,low(@1) ldireg r6,high(@1) ldireg r7,byte3(@1) ldireg r8,byte4(@1) ldireg r9,byte5(@1) .elif r6_mpr ldireg r6,low(@1) ldireg r7,high(@1) ldireg r8,byte3(@1) ldireg r9,byte4(@1) ldireg r10,byte5(@1) .elif r7_mpr ldireg r7,low(@1) ldireg r8,high(@1) ldireg r9,byte3(@1) ldireg r10,byte4(@1) ldireg r11,byte5(@1) .elif r8_mpr ldireg r8,low(@1) ldireg r9,high(@1) ldireg r10,byte3(@1) ldireg r11,byte4(@1) ldireg r12,byte5(@1) .elif r9_mpr ldireg r9,low(@1) ldireg r10,high(@1) ldireg r11,byte3(@1) ldireg r12,byte4(@1) ldireg r13,byte5(@1) .elif r10_mpr ldireg r10,low(@1) ldireg r11,high(@1) ldireg r12,byte3(@1) ldireg r13,byte4(@1) ldireg r14,byte5(@1) .elif r11_mpr ldireg r11,low(@1) ldireg r12,high(@1) ldireg r13,byte3(@1) ldireg r14,byte4(@1) ldireg r15,byte5(@1) .elif r12_mpr ldireg r12,low(@1) ldireg r13,high(@1) ldireg r14,byte3(@1) ldireg r15,byte4(@1) ldireg r16,byte5(@1) .elif r13_mpr ldireg r13,low(@1) ldireg r14,high(@1) ldireg r15,byte3(@1) ldireg r16,byte4(@1) ldireg r17,byte5(@1) .elif r14_mpr ldireg r14,low(@1) ldireg r15,high(@1) ldireg r16,byte3(@1) ldireg r17,byte4(@1) ldireg r18,byte5(@1) .elif r15_mpr ldireg r15,low(@1) ldireg r16,high(@1) ldireg r17,byte3(@1) ldireg r18,byte4(@1) ldireg r19,byte5(@1) .elif r16_mpr ldireg r16,low(@1) ldireg r17,high(@1) ldireg r18,byte3(@1) ldireg r19,byte4(@1) ldireg r20,byte5(@1) .elif r17_mpr ldireg r17,low(@1) ldireg r18,high(@1) ldireg r19,byte3(@1) ldireg r20,byte4(@1) ldireg r21,byte5(@1) .elif r18_mpr ldireg r18,low(@1) ldireg r19,high(@1) ldireg r20,byte3(@1) ldireg r21,byte4(@1) ldireg r22,byte5(@1) .elif r19_mpr ldireg r19,low(@1) ldireg r20,high(@1) ldireg r21,byte3(@1) ldireg r22,byte4(@1) ldireg r23,byte5(@1) .elif r20_mpr ldireg r20,low(@1) ldireg r21,high(@1) ldireg r22,byte3(@1) ldireg r23,byte4(@1) ldireg r24,byte5(@1) .elif r21_mpr ldireg r21,low(@1) ldireg r22,high(@1) ldireg r23,byte3(@1) ldireg r24,byte4(@1) ldireg r25,byte5(@1) .elif r22_mpr ldireg r22,low(@1) ldireg r23,high(@1) ldireg r24,byte3(@1) ldireg r25,byte4(@1) ldireg r26,byte5(@1) .elif r23_mpr ldireg r23,low(@1) ldireg r24,high(@1) ldireg r25,byte3(@1) ldireg r26,byte4(@1) ldireg r27,byte5(@1) .elif r24_mpr ldireg r24,low(@1) ldireg r25,high(@1) ldireg r26,byte3(@1) ldireg r27,byte4(@1) ldireg r28,byte5(@1) .elif r25_mpr ldireg r25,low(@1) ldireg r26,high(@1) ldireg r27,byte3(@1) ldireg r28,byte4(@1) ldireg r29,byte5(@1) .elif r26_mpr ldireg r26,low(@1) ldireg r27,high(@1) ldireg r28,byte3(@1) ldireg r29,byte4(@1) ldireg r30,byte5(@1) .elif r27_mpr ldireg r27,low(@1) ldireg r28,high(@1) ldireg r29,byte3(@1) ldireg r30,byte4(@1) ldireg r31,byte5(@1) .else .error "Macro ldireg40 reg zu gross" .endif .endm .macro ldireg48 ; @0 r0-r26, @1 Data48, 6-12c, 12-24b, wenn r0-r15, temp benutzt setr .set @0_mpr = 1 .if r0_mpr ldireg r0,low(@1) ldireg r1,high(@1) ldireg r2,byte3(@1) ldireg r3,byte4(@1) ldireg r4,byte5(@1) ldireg r5,byte6(@1) .elif r1_mpr ldireg r1,low(@1) ldireg r2,high(@1) ldireg r3,byte3(@1) ldireg r4,byte4(@1) ldireg r5,byte5(@1) ldireg r6,byte6(@1) .elif r2_mpr ldireg r2,low(@1) ldireg r3,high(@1) ldireg r4,byte3(@1) ldireg r5,byte4(@1) ldireg r6,byte5(@1) ldireg r7,byte6(@1) .elif r3_mpr ldireg r3,low(@1) ldireg r4,high(@1) ldireg r5,byte3(@1) ldireg r6,byte4(@1) ldireg r7,byte5(@1) ldireg r8,byte6(@1) .elif r4_mpr ldireg r4,low(@1) ldireg r5,high(@1) ldireg r6,byte3(@1) ldireg r7,byte4(@1) ldireg r8,byte5(@1) ldireg r9,byte6(@1) .elif r5_mpr ldireg r5,low(@1) ldireg r6,high(@1) ldireg r7,byte3(@1) ldireg r8,byte4(@1) ldireg r9,byte5(@1) ldireg r10,byte6(@1) .elif r6_mpr ldireg r6,low(@1) ldireg r7,high(@1) ldireg r8,byte3(@1) ldireg r9,byte4(@1) ldireg r10,byte5(@1) ldireg r11,byte6(@1) .elif r7_mpr ldireg r7,low(@1) ldireg r8,high(@1) ldireg r9,byte3(@1) ldireg r10,byte4(@1) ldireg r11,byte5(@1) ldireg r12,byte6(@1) .elif r8_mpr ldireg r8,low(@1) ldireg r9,high(@1) ldireg r10,byte3(@1) ldireg r11,byte4(@1) ldireg r12,byte5(@1) ldireg r13,byte6(@1) .elif r9_mpr ldireg r9,low(@1) ldireg r10,high(@1) ldireg r11,byte3(@1) ldireg r12,byte4(@1) ldireg r13,byte5(@1) ldireg r14,byte6(@1) .elif r10_mpr ldireg r10,low(@1) ldireg r11,high(@1) ldireg r12,byte3(@1) ldireg r13,byte4(@1) ldireg r14,byte5(@1) ldireg r15,byte6(@1) .elif r11_mpr ldireg r11,low(@1) ldireg r12,high(@1) ldireg r13,byte3(@1) ldireg r14,byte4(@1) ldireg r15,byte5(@1) ldireg r16,byte6(@1) .elif r12_mpr ldireg r12,low(@1) ldireg r13,high(@1) ldireg r14,byte3(@1) ldireg r15,byte4(@1) ldireg r16,byte5(@1) ldireg r17,byte6(@1) .elif r13_mpr ldireg r13,low(@1) ldireg r14,high(@1) ldireg r15,byte3(@1) ldireg r16,byte4(@1) ldireg r17,byte5(@1) ldireg r18,byte6(@1) .elif r14_mpr ldireg r14,low(@1) ldireg r15,high(@1) ldireg r16,byte3(@1) ldireg r17,byte4(@1) ldireg r18,byte5(@1) ldireg r19,byte6(@1) .elif r15_mpr ldireg r15,low(@1) ldireg r16,high(@1) ldireg r17,byte3(@1) ldireg r18,byte4(@1) ldireg r19,byte5(@1) ldireg r20,byte6(@1) .elif r16_mpr ldireg r16,low(@1) ldireg r17,high(@1) ldireg r18,byte3(@1) ldireg r19,byte4(@1) ldireg r20,byte5(@1) ldireg r21,byte6(@1) .elif r17_mpr ldireg r17,low(@1) ldireg r18,high(@1) ldireg r19,byte3(@1) ldireg r20,byte4(@1) ldireg r21,byte5(@1) ldireg r22,byte6(@1) .elif r18_mpr ldireg r18,low(@1) ldireg r19,high(@1) ldireg r20,byte3(@1) ldireg r21,byte4(@1) ldireg r22,byte5(@1) ldireg r23,byte6(@1) .elif r19_mpr ldireg r19,low(@1) ldireg r20,high(@1) ldireg r21,byte3(@1) ldireg r22,byte4(@1) ldireg r23,byte5(@1) ldireg r24,byte6(@1) .elif r20_mpr ldireg r20,low(@1) ldireg r21,high(@1) ldireg r22,byte3(@1) ldireg r23,byte4(@1) ldireg r24,byte5(@1) ldireg r25,byte6(@1) .elif r21_mpr ldireg r21,low(@1) ldireg r22,high(@1) ldireg r23,byte3(@1) ldireg r24,byte4(@1) ldireg r25,byte5(@1) ldireg r26,byte6(@1) .elif r22_mpr ldireg r22,low(@1) ldireg r23,high(@1) ldireg r24,byte3(@1) ldireg r25,byte4(@1) ldireg r26,byte5(@1) ldireg r27,byte6(@1) .elif r23_mpr ldireg r23,low(@1) ldireg r24,high(@1) ldireg r25,byte3(@1) ldireg r26,byte4(@1) ldireg r27,byte5(@1) ldireg r28,byte6(@1) .elif r24_mpr ldireg r24,low(@1) ldireg r25,high(@1) ldireg r26,byte3(@1) ldireg r27,byte4(@1) ldireg r28,byte5(@1) ldireg r29,byte6(@1) .elif r25_mpr ldireg r25,low(@1) ldireg r26,high(@1) ldireg r27,byte3(@1) ldireg r28,byte4(@1) ldireg r29,byte5(@1) ldireg r30,byte6(@1) .elif r26_mpr ldireg r26,low(@1) ldireg r27,high(@1) ldireg r28,byte3(@1) ldireg r29,byte4(@1) ldireg r30,byte5(@1) ldireg r31,byte6(@1) .else .error "Macro ldireg48 reg zu gross" .endif .endm .macro ldireg56 ; @0 r0-r25, @1 Data56, 7-14c, 14-28b, wenn r0-r15, temp benutzt setr .set @0_mpr = 1 .if r0_mpr ldireg r0,low(@1) ldireg r1,high(@1) ldireg r2,byte3(@1) ldireg r3,byte4(@1) ldireg r4,byte5(@1) ldireg r5,byte6(@1) ldireg r6,byte7(@1) .elif r1_mpr ldireg r1,low(@1) ldireg r2,high(@1) ldireg r3,byte3(@1) ldireg r4,byte4(@1) ldireg r5,byte5(@1) ldireg r6,byte6(@1) ldireg r7,byte7(@1) .elif r2_mpr ldireg r2,low(@1) ldireg r3,high(@1) ldireg r4,byte3(@1) ldireg r5,byte4(@1) ldireg r6,byte5(@1) ldireg r7,byte6(@1) ldireg r8,byte7(@1) .elif r3_mpr ldireg r3,low(@1) ldireg r4,high(@1) ldireg r5,byte3(@1) ldireg r6,byte4(@1) ldireg r7,byte5(@1) ldireg r8,byte6(@1) ldireg r9,byte7(@1) .elif r4_mpr ldireg r4,low(@1) ldireg r5,high(@1) ldireg r6,byte3(@1) ldireg r7,byte4(@1) ldireg r8,byte5(@1) ldireg r9,byte6(@1) ldireg r10,byte7(@1) .elif r5_mpr ldireg r5,low(@1) ldireg r6,high(@1) ldireg r7,byte3(@1) ldireg r8,byte4(@1) ldireg r9,byte5(@1) ldireg r10,byte6(@1) ldireg r11,byte7(@1) .elif r6_mpr ldireg r6,low(@1) ldireg r7,high(@1) ldireg r8,byte3(@1) ldireg r9,byte4(@1) ldireg r10,byte5(@1) ldireg r11,byte6(@1) ldireg r12,byte7(@1) .elif r7_mpr ldireg r7,low(@1) ldireg r8,high(@1) ldireg r9,byte3(@1) ldireg r10,byte4(@1) ldireg r11,byte5(@1) ldireg r12,byte6(@1) ldireg r13,byte7(@1) .elif r8_mpr ldireg r8,low(@1) ldireg r9,high(@1) ldireg r10,byte3(@1) ldireg r11,byte4(@1) ldireg r12,byte5(@1) ldireg r13,byte6(@1) ldireg r14,byte7(@1) .elif r9_mpr ldireg r9,low(@1) ldireg r10,high(@1) ldireg r11,byte3(@1) ldireg r12,byte4(@1) ldireg r13,byte5(@1) ldireg r14,byte6(@1) ldireg r15,byte7(@1) .elif r10_mpr ldireg r10,low(@1) ldireg r11,high(@1) ldireg r12,byte3(@1) ldireg r13,byte4(@1) ldireg r14,byte5(@1) ldireg r15,byte6(@1) ldireg r16,byte7(@1) .elif r11_mpr ldireg r11,low(@1) ldireg r12,high(@1) ldireg r13,byte3(@1) ldireg r14,byte4(@1) ldireg r15,byte5(@1) ldireg r16,byte6(@1) ldireg r17,byte7(@1) .elif r12_mpr ldireg r12,low(@1) ldireg r13,high(@1) ldireg r14,byte3(@1) ldireg r15,byte4(@1) ldireg r16,byte5(@1) ldireg r17,byte6(@1) ldireg r18,byte7(@1) .elif r13_mpr ldireg r13,low(@1) ldireg r14,high(@1) ldireg r15,byte3(@1) ldireg r16,byte4(@1) ldireg r17,byte5(@1) ldireg r18,byte6(@1) ldireg r19,byte7(@1) .elif r14_mpr ldireg r14,low(@1) ldireg r15,high(@1) ldireg r16,byte3(@1) ldireg r17,byte4(@1) ldireg r18,byte5(@1) ldireg r19,byte6(@1) ldireg r20,byte7(@1) .elif r15_mpr ldireg r15,low(@1) ldireg r16,high(@1) ldireg r17,byte3(@1) ldireg r18,byte4(@1) ldireg r19,byte5(@1) ldireg r20,byte6(@1) ldireg r21,byte7(@1) .elif r16_mpr ldireg r16,low(@1) ldireg r17,high(@1) ldireg r18,byte3(@1) ldireg r19,byte4(@1) ldireg r20,byte5(@1) ldireg r21,byte6(@1) ldireg r22,byte7(@1) .elif r17_mpr ldireg r17,low(@1) ldireg r18,high(@1) ldireg r19,byte3(@1) ldireg r20,byte4(@1) ldireg r21,byte5(@1) ldireg r22,byte6(@1) ldireg r23,byte7(@1) .elif r18_mpr ldireg r18,low(@1) ldireg r19,high(@1) ldireg r20,byte3(@1) ldireg r21,byte4(@1) ldireg r22,byte5(@1) ldireg r23,byte6(@1) ldireg r24,byte7(@1) .elif r19_mpr ldireg r19,low(@1) ldireg r20,high(@1) ldireg r21,byte3(@1) ldireg r22,byte4(@1) ldireg r23,byte5(@1) ldireg r24,byte6(@1) ldireg r25,byte7(@1) .elif r20_mpr ldireg r20,low(@1) ldireg r21,high(@1) ldireg r22,byte3(@1) ldireg r23,byte4(@1) ldireg r24,byte5(@1) ldireg r25,byte6(@1) ldireg r26,byte7(@1) .elif r21_mpr ldireg r21,low(@1) ldireg r22,high(@1) ldireg r23,byte3(@1) ldireg r24,byte4(@1) ldireg r25,byte5(@1) ldireg r26,byte6(@1) ldireg r27,byte7(@1) .elif r22_mpr ldireg r22,low(@1) ldireg r23,high(@1) ldireg r24,byte3(@1) ldireg r25,byte4(@1) ldireg r26,byte5(@1) ldireg r27,byte6(@1) ldireg r28,byte7(@1) .elif r23_mpr ldireg r23,low(@1) ldireg r24,high(@1) ldireg r25,byte3(@1) ldireg r26,byte4(@1) ldireg r27,byte5(@1) ldireg r28,byte6(@1) ldireg r29,byte7(@1) .elif r24_mpr ldireg r24,low(@1) ldireg r25,high(@1) ldireg r26,byte3(@1) ldireg r27,byte4(@1) ldireg r28,byte5(@1) ldireg r29,byte6(@1) ldireg r30,byte7(@1) .elif r25_mpr ldireg r25,low(@1) ldireg r26,high(@1) ldireg r27,byte3(@1) ldireg r28,byte4(@1) ldireg r29,byte5(@1) ldireg r30,byte6(@1) ldireg r31,byte7(@1) .else .error "Macro ldireg56 reg zu gross" .endif .endm .macro ldireg64 ; @0 r0-r24, @1 Data64, 8-16c, 16-32b, wenn r0-r15, temp benutzt setr .set @0_mpr = 1 .if r0_mpr ldireg r0,low(@1) ldireg r1,high(@1) ldireg r2,byte3(@1) ldireg r3,byte4(@1) ldireg r4,byte5(@1) ldireg r5,byte6(@1) ldireg r6,byte7(@1) ldireg r7,byte8(@1) .elif r1_mpr ldireg r1,low(@1) ldireg r2,high(@1) ldireg r3,byte3(@1) ldireg r4,byte4(@1) ldireg r5,byte5(@1) ldireg r6,byte6(@1) ldireg r7,byte7(@1) ldireg r8,byte8(@1) .elif r2_mpr ldireg r2,low(@1) ldireg r3,high(@1) ldireg r4,byte3(@1) ldireg r5,byte4(@1) ldireg r6,byte5(@1) ldireg r7,byte6(@1) ldireg r8,byte7(@1) ldireg r9,byte8(@1) .elif r3_mpr ldireg r3,low(@1) ldireg r4,high(@1) ldireg r5,byte3(@1) ldireg r6,byte4(@1) ldireg r7,byte5(@1) ldireg r8,byte6(@1) ldireg r9,byte7(@1) ldireg r10,byte8(@1) .elif r4_mpr ldireg r4,low(@1) ldireg r5,high(@1) ldireg r6,byte3(@1) ldireg r7,byte4(@1) ldireg r8,byte5(@1) ldireg r9,byte6(@1) ldireg r10,byte7(@1) ldireg r11,byte8(@1) .elif r5_mpr ldireg r5,low(@1) ldireg r6,high(@1) ldireg r7,byte3(@1) ldireg r8,byte4(@1) ldireg r9,byte5(@1) ldireg r10,byte6(@1) ldireg r11,byte7(@1) ldireg r12,byte8(@1) .elif r6_mpr ldireg r6,low(@1) ldireg r7,high(@1) ldireg r8,byte3(@1) ldireg r9,byte4(@1) ldireg r10,byte5(@1) ldireg r11,byte6(@1) ldireg r12,byte7(@1) ldireg r13,byte8(@1) .elif r7_mpr ldireg r7,low(@1) ldireg r8,high(@1) ldireg r9,byte3(@1) ldireg r10,byte4(@1) ldireg r11,byte5(@1) ldireg r12,byte6(@1) ldireg r13,byte7(@1) ldireg r14,byte8(@1) .elif r8_mpr ldireg r8,low(@1) ldireg r9,high(@1) ldireg r10,byte3(@1) ldireg r11,byte4(@1) ldireg r12,byte5(@1) ldireg r13,byte6(@1) ldireg r14,byte7(@1) ldireg r15,byte8(@1) .elif r9_mpr ldireg r9,low(@1) ldireg r10,high(@1) ldireg r11,byte3(@1) ldireg r12,byte4(@1) ldireg r13,byte5(@1) ldireg r14,byte6(@1) ldireg r15,byte7(@1) ldireg r16,byte8(@1) .elif r10_mpr ldireg r10,low(@1) ldireg r11,high(@1) ldireg r12,byte3(@1) ldireg r13,byte4(@1) ldireg r14,byte5(@1) ldireg r15,byte6(@1) ldireg r16,byte7(@1) ldireg r17,byte8(@1) .elif r11_mpr ldireg r11,low(@1) ldireg r12,high(@1) ldireg r13,byte3(@1) ldireg r14,byte4(@1) ldireg r15,byte5(@1) ldireg r16,byte6(@1) ldireg r17,byte7(@1) ldireg r18,byte8(@1) .elif r12_mpr ldireg r12,low(@1) ldireg r13,high(@1) ldireg r14,byte3(@1) ldireg r15,byte4(@1) ldireg r16,byte5(@1) ldireg r17,byte6(@1) ldireg r18,byte7(@1) ldireg r19,byte8(@1) .elif r13_mpr ldireg r13,low(@1) ldireg r14,high(@1) ldireg r15,byte3(@1) ldireg r16,byte4(@1) ldireg r17,byte5(@1) ldireg r18,byte6(@1) ldireg r19,byte7(@1) ldireg r20,byte8(@1) .elif r14_mpr ldireg r14,low(@1) ldireg r15,high(@1) ldireg r16,byte3(@1) ldireg r17,byte4(@1) ldireg r18,byte5(@1) ldireg r19,byte6(@1) ldireg r20,byte7(@1) ldireg r21,byte8(@1) .elif r15_mpr ldireg r15,low(@1) ldireg r16,high(@1) ldireg r17,byte3(@1) ldireg r18,byte4(@1) ldireg r19,byte5(@1) ldireg r20,byte6(@1) ldireg r21,byte7(@1) ldireg r22,byte8(@1) .elif r16_mpr ldireg r16,low(@1) ldireg r17,high(@1) ldireg r18,byte3(@1) ldireg r19,byte4(@1) ldireg r20,byte5(@1) ldireg r21,byte6(@1) ldireg r22,byte7(@1) ldireg r23,byte8(@1) .elif r17_mpr ldireg r17,low(@1) ldireg r18,high(@1) ldireg r19,byte3(@1) ldireg r20,byte4(@1) ldireg r21,byte5(@1) ldireg r22,byte6(@1) ldireg r23,byte7(@1) ldireg r24,byte8(@1) .elif r18_mpr ldireg r18,low(@1) ldireg r19,high(@1) ldireg r20,byte3(@1) ldireg r21,byte4(@1) ldireg r22,byte5(@1) ldireg r23,byte6(@1) ldireg r24,byte7(@1) ldireg r25,byte8(@1) .elif r19_mpr ldireg r19,low(@1) ldireg r20,high(@1) ldireg r21,byte3(@1) ldireg r22,byte4(@1) ldireg r23,byte5(@1) ldireg r24,byte6(@1) ldireg r25,byte7(@1) ldireg r26,byte8(@1) .elif r20_mpr ldireg r20,low(@1) ldireg r21,high(@1) ldireg r22,byte3(@1) ldireg r23,byte4(@1) ldireg r24,byte5(@1) ldireg r25,byte6(@1) ldireg r26,byte7(@1) ldireg r27,byte8(@1) .elif r21_mpr ldireg r21,low(@1) ldireg r22,high(@1) ldireg r23,byte3(@1) ldireg r24,byte4(@1) ldireg r25,byte5(@1) ldireg r26,byte6(@1) ldireg r27,byte7(@1) ldireg r28,byte8(@1) .elif r22_mpr ldireg r22,low(@1) ldireg r23,high(@1) ldireg r24,byte3(@1) ldireg r25,byte4(@1) ldireg r26,byte5(@1) ldireg r27,byte6(@1) ldireg r28,byte7(@1) ldireg r29,byte8(@1) .elif r23_mpr ldireg r23,low(@1) ldireg r24,high(@1) ldireg r25,byte3(@1) ldireg r26,byte4(@1) ldireg r27,byte5(@1) ldireg r28,byte6(@1) ldireg r29,byte7(@1) ldireg r30,byte8(@1) .elif r24_mpr ldireg r24,low(@1) ldireg r25,high(@1) ldireg r26,byte3(@1) ldireg r27,byte4(@1) ldireg r28,byte5(@1) ldireg r29,byte6(@1) ldireg r30,byte7(@1) ldireg r31,byte8(@1) .else .error "Macro ldireg64 reg zu gross" .endif .endm ;========================================================================= ;=== adireg ============================================================== ;========================================================================= .macro subireg16 ; @0 r0-r30, @1 Data16, @2 temp-Oberreg, 2-4c, 4-8b setr ; wenn r0-r15, @2 benutzt .set @0_mpr = 1 .if r0_mpr subireg r0,low(@1),@2 sbcireg r1,high(@1),@2 .elif r1_mpr subireg r1,low(@1),@2 sbcireg r2,high(@1),@2 .elif r2_mpr subireg r2,low(@1),@2 sbcireg r3,high(@1),@2 .elif r3_mpr subireg r3,low(@1),@2 sbcireg r4,high(@1),@2 .elif r4_mpr subireg r4,low(@1),@2 sbcireg r5,high(@1),@2 .elif r5_mpr subireg r5,low(@1),@2 sbcireg r6,high(@1),@2 .elif r6_mpr subireg r6,low(@1),@2 sbcireg r7,high(@1),@2 .elif r7_mpr subireg r7,low(@1),@2 sbcireg r8,high(@1),@2 .elif r8_mpr subireg r8,low(@1),@2 sbcireg r9,high(@1),@2 .elif r9_mpr subireg r9,low(@1),@2 sbcireg r10,high(@1),@2 .elif r10_mpr subireg r10,low(@1),@2 sbcireg r11,high(@1),@2 .elif r11_mpr subireg r11,low(@1),@2 sbcireg r12,high(@1),@2 .elif r12_mpr subireg r12,low(@1),@2 sbcireg r13,high(@1),@2 .elif r13_mpr subireg r13,low(@1),@2 sbcireg r14,high(@1),@2 .elif r14_mpr subireg r14,low(@1),@2 sbcireg r15,high(@1),@2 .elif r15_mpr subireg r15,low(@1),@2 sbci r16,high(@1) .elif r16_mpr subi r16,low(@1) sbci r17,high(@1) .elif r17_mpr subi r17,low(@1) sbci r18,high(@1) .elif r18_mpr subi r18,low(@1) sbci r19,high(@1) .elif r19_mpr subi r19,low(@1) sbci r20,high(@1) .elif r20_mpr subi r20,low(@1) sbci r21,high(@1) .elif r21_mpr subi r21,low(@1) sbci r22,high(@1) .elif r22_mpr subi r22,low(@1) sbci r23,high(@1) .elif r23_mpr subi r23,low(@1) sbci r24,high(@1) .elif r24_mpr || temp_mpr || templ_mpr subi r24,low(@1) sbci r25,high(@1) .elif r25_mpr || temph_mpr subi r25,low(@1) sbci r26,high(@1) .elif r26_mpr || xl_mpr || X_mpr subi r26,low(@1) sbci r27,high(@1) .elif r27_mpr || xh_mpr subi r27,low(@1) sbci r28,high(@1) .elif r28_mpr || yl_mpr || Y_mpr subi r28,low(@1) sbci r29,high(@1) .elif r29_mpr || yh_mpr subi r29,low(@1) sbci r30,high(@1) .elif r30_mpr || zl_mpr || Z_mpr subi r30,low(@1) sbci r31,high(@1) .else .error "Macro subireg16 reg zu gross" .endif .endm .macro sbcireg16 ; @0 r0-r30, @1 Data16, @2 temp-Oberreg, 2-4c, 4-8b setr ; wenn r0-r15, @2 benutzt .set @0_mpr = 1 .if r0_mpr sbcireg r0,low(@1-1),@2 sbcireg r1,high(@1-1),@2 .elif r1_mpr sbcireg r1,low(@1-1),@2 sbcireg r2,high(@1-1),@2 .elif r2_mpr sbcireg r2,low(@1-1),@2 sbcireg r3,high(@1-1),@2 .elif r3_mpr sbcireg r3,low(@1-1),@2 sbcireg r4,high(@1-1),@2 .elif r4_mpr sbcireg r4,low(@1-1),@2 sbcireg r5,high(@1-1),@2 .elif r5_mpr sbcireg r5,low(@1-1),@2 sbcireg r6,high(@1-1),@2 .elif r6_mpr sbcireg r6,low(@1-1),@2 sbcireg r7,high(@1-1),@2 .elif r7_mpr sbcireg r7,low(@1-1),@2 sbcireg r8,high(@1-1),@2 .elif r8_mpr sbcireg r8,low(@1-1),@2 sbcireg r9,high(@1-1),@2 .elif r9_mpr sbcireg r9,low(@1-1),@2 sbcireg r10,high(@1-1),@2 .elif r10_mpr sbcireg r10,low(@1-1),@2 sbcireg r11,high(@1-1),@2 .elif r11_mpr sbcireg r11,low(@1-1),@2 sbcireg r12,high(@1-1),@2 .elif r12_mpr sbcireg r12,low(@1-1),@2 sbcireg r13,high(@1-1),@2 .elif r13_mpr sbcireg r13,low(@1-1),@2 sbcireg r14,high(@1-1),@2 .elif r14_mpr sbcireg r14,low(@1-1),@2 sbcireg r15,high(@1-1),@2 .elif r15_mpr sbcireg r15,low(@1-1),@2 sbci r16,high(@1-1) .elif r16_mpr sbci r16,low(@1-1) sbci r17,high(@1-1) .elif r17_mpr sbci r17,low(@1-1) sbci r18,high(@1-1) .elif r18_mpr sbci r18,low(@1-1) sbci r19,high(@1-1) .elif r19_mpr sbci r19,low(@1-1) sbci r20,high(@1-1) .elif r20_mpr sbci r20,low(@1-1) sbci r21,high(@1-1) .elif r21_mpr sbci r21,low(@1-1) sbci r22,high(@1-1) .elif r22_mpr sbci r22,low(@1-1) sbci r23,high(@1-1) .elif r23_mpr sbci r23,low(@1-1) sbci r24,high(@1-1) .elif r24_mpr || temp_mpr || templ_mpr sbci r24,low(@1-1) sbci r25,high(@1-1) .elif r25_mpr || temph_mpr sbci r25,low(@1-1) sbci r26,high(@1-1) .elif r26_mpr || xl_mpr || X_mpr sbci r26,low(@1-1) sbci r27,high(@1-1) .elif r27_mpr || xh_mpr sbci r27,low(@1-1) sbci r28,high(@1-1) .elif r28_mpr || yl_mpr || Y_mpr sbci r28,low(@1-1) sbci r29,high(@1-1) .elif r29_mpr || yh_mpr sbci r29,low(@1-1) sbci r30,high(@1-1) .elif r30_mpr || zl_mpr || Z_mpr sbci r30,low(@1-1) sbci r31,high(@1-1) .else .error "Macro sbcireg16 reg zu gross" .endif .endm .macro adireg16 ; @0 r0-r30, @1 Data16, @2 temp-Oberreg, 2-4c, 4-8b subireg16 @0,-@1,@2 ; wenn r0-r15, @2 benutzt .endm .macro adcireg16 ; @0 r0-r30, @1 Data16, @2 temp-Oberreg, 2-4c, 4-8b sbcireg16 @0,-@1,@2 ; wenn r0-r15, @2 benutzt .endm .macro cpireg16 ; @0 r0-r30, @1 Data16, @2 temp-Oberreg, 3-4c, 6-8b setr .set @0_mpr = 1 .if r0_mpr cpireg r0,low(@1),@2 cpcireg r1,high(@1),@2 .elif r1_mpr cpireg r1,low(@1),@2 cpcireg r2,high(@1),@2 .elif r2_mpr cpireg r2,low(@1),@2 cpcireg r3,high(@1),@2 .elif r3_mpr cpireg r3,low(@1),@2 cpcireg r4,high(@1),@2 .elif r4_mpr cpireg r4,low(@1),@2 cpcireg r5,high(@1),@2 .elif r5_mpr cpireg r5,low(@1),@2 cpcireg r6,high(@1),@2 .elif r6_mpr cpireg r6,low(@1),@2 cpcireg r7,high(@1),@2 .elif r7_mpr cpireg r7,low(@1),@2 cpcireg r8,high(@1),@2 .elif r8_mpr cpireg r8,low(@1),@2 cpcireg r9,high(@1),@2 .elif r9_mpr cpireg r9,low(@1),@2 cpcireg r10,high(@1),@2 .elif r10_mpr cpireg r10,low(@1),@2 cpcireg r11,high(@1),@2 .elif r11_mpr cpireg r11,low(@1),@2 cpcireg r12,high(@1),@2 .elif r12_mpr cpireg r12,low(@1),@2 cpcireg r13,high(@1),@2 .elif r13_mpr cpireg r13,low(@1),@2 cpcireg r14,high(@1),@2 .elif r14_mpr cpireg r14,low(@1),@2 cpcireg r15,high(@1),@2 .elif r15_mpr cpireg r15,low(@1),@2 cpcireg r16,high(@1),@2 .elif r16_mpr cpi r16,low(@1) cpcireg r17,high(@1),@2 .elif r17_mpr cpi r17,low(@1) cpcireg r18,high(@1),@2 .elif r18_mpr cpi r18,low(@1) cpcireg r19,high(@1),@2 .elif r19_mpr cpi r19,low(@1) cpcireg r20,high(@1),@2 .elif r20_mpr cpi r20,low(@1) cpcireg r21,high(@1),@2 .elif r21_mpr cpi r21,low(@1) cpcireg r22,high(@1),@2 .elif r22_mpr cpi r22,low(@1) cpcireg r23,high(@1),@2 .elif r23_mpr cpi r23,low(@1) cpcireg r24,high(@1),@2 .elif r24_mpr || temp_mpr || templ_mpr cpi r24,low(@1) cpcireg r25,high(@1),@2 .elif r25_mpr || temph_mpr cpi r25,low(@1) cpcireg r26,high(@1),@2 .elif r26_mpr || xl_mpr || X_mpr cpi r26,low(@1) cpcireg r27,high(@1),@2 .elif r27_mpr || xh_mpr cpi r27,low(@1) cpcireg r28,high(@1),@2 .elif r28_mpr || yl_mpr || Y_mpr cpi r28,low(@1) cpcireg r29,high(@1),@2 .elif r29_mpr || yh_mpr cpi r29,low(@1) cpcireg r30,high(@1),@2 .elif r30_mpr || zl_mpr || Z_mpr cpi r30,low(@1) cpcireg r31,high(@1),@2 .else .error "Macro cpireg16 reg zu gross" .endif .endm ;========================================================================= ;=== subireg ============================================================= ;========================================================================= ;========================================================================= ;=== cpireg ============================================================== ;========================================================================= ;========================================================================= ;=== inreg =============================================================== ;========================================================================= .macro inreg16 ; @0 r0-r30, @1 IO-RAM, 2-4c, 4-8b setr .set @0_mpr = 1 .if r0_mpr inreg r0,@1 inreg r1,@1+1 .elif r1_mpr inreg r1,@1 inreg r2,@1+1 .elif r2_mpr inreg r2,@1 inreg r3,@1+1 .elif r3_mpr inreg r3,@1 inreg r4,@1+1 .elif r4_mpr inreg r4,@1 inreg r5,@1+1 .elif r5_mpr inreg r5,@1 inreg r6,@1+1 .elif r6_mpr inreg r6,@1 inreg r7,@1+1 .elif r7_mpr inreg r7,@1 inreg r8,@1+1 .elif r8_mpr inreg r8,@1 inreg r9,@1+1 .elif r9_mpr inreg r9,@1 inreg r10,@1+1 .elif r10_mpr inreg r10,@1 inreg r11,@1+1 .elif r11_mpr inreg r11,@1 inreg r12,@1+1 .elif r12_mpr inreg r12,@1 inreg r13,@1+1 .elif r13_mpr inreg r13,@1 inreg r14,@1+1 .elif r14_mpr inreg r14,@1 inreg r15,@1+1 .elif r15_mpr inreg r15,@1 inreg r16,@1+1 .elif r16_mpr inreg r16,@1 inreg r17,@1+1 .elif r17_mpr inreg r17,@1 inreg r18,@1+1 .elif r18_mpr inreg r18,@1 inreg r19,@1+1 .elif r19_mpr inreg r19,@1 inreg r20,@1+1 .elif r20_mpr inreg r20,@1 inreg r21,@1+1 .elif r21_mpr inreg r21,@1 inreg r22,@1+1 .elif r22_mpr inreg r22,@1 inreg r23,@1+1 .elif r23_mpr inreg r23,@1 inreg r24,@1+1 .elif r24_mpr || temp_mpr || templ_mpr inreg r24,@1 inreg r25,@1+1 .elif r25_mpr || temph_mpr inreg r25,@1 inreg r26,@1+1 .elif r26_mpr || xl_mpr || X_mpr inreg r26,@1 inreg r27,@1+1 .elif r27_mpr || xh_mpr inreg r27,@1 inreg r28,@1+1 .elif r28_mpr || yl_mpr || Y_mpr inreg r28,@1 inreg r29,@1+1 .elif r29_mpr || yh_mpr inreg r29,@1 inreg r30,@1+1 .elif r30_mpr || zl_mpr || Z_mpr inreg r30,@1 inreg r31,@1+1 .else .error "Macro inreg16 reg zu gross" .endif .endm .macro inreg24 ; @0 r0-r29, @1 IO-RAM, 3-6c, 6-12b setr .set @0_mpr = 1 .if r0_mpr inreg r0,@1 inreg r1,@1+1 inreg r2,@1+2 .elif r1_mpr inreg r1,@1 inreg r2,@1+1 inreg r3,@1+2 .elif r2_mpr inreg r2,@1 inreg r3,@1+1 inreg r4,@1+2 .elif r3_mpr inreg r3,@1 inreg r4,@1+1 inreg r5,@1+2 .elif r4_mpr inreg r4,@1 inreg r5,@1+1 inreg r6,@1+2 .elif r5_mpr inreg r5,@1 inreg r6,@1+1 inreg r7,@1+2 .elif r6_mpr inreg r6,@1 inreg r7,@1+1 inreg r8,@1+2 .elif r7_mpr inreg r7,@1 inreg r8,@1+1 inreg r9,@1+2 .elif r8_mpr inreg r8,@1 inreg r9,@1+1 inreg r10,@1+2 .elif r9_mpr inreg r9,@1 inreg r10,@1+1 inreg r11,@1+2 .elif r10_mpr inreg r10,@1 inreg r11,@1+1 inreg r12,@1+2 .elif r11_mpr inreg r11,@1 inreg r12,@1+1 inreg r13,@1+2 .elif r12_mpr inreg r12,@1 inreg r13,@1+1 inreg r14,@1+2 .elif r13_mpr inreg r13,@1 inreg r14,@1+1 inreg r15,@1+2 .elif r14_mpr inreg r14,@1 inreg r15,@1+1 inreg r16,@1+2 .elif r15_mpr inreg r15,@1 inreg r16,@1+1 inreg r17,@1+2 .elif r16_mpr inreg r16,@1 inreg r17,@1+1 inreg r18,@1+2 .elif r17_mpr inreg r17,@1 inreg r18,@1+1 inreg r19,@1+2 .elif r18_mpr inreg r18,@1 inreg r19,@1+1 inreg r20,@1+2 .elif r19_mpr inreg r19,@1 inreg r20,@1+1 inreg r21,@1+2 .elif r20_mpr inreg r20,@1 inreg r21,@1+1 inreg r22,@1+2 .elif r21_mpr inreg r21,@1 inreg r22,@1+1 inreg r23,@1+2 .elif r22_mpr inreg r22,@1 inreg r23,@1+1 inreg r24,@1+2 .elif r23_mpr inreg r23,@1 inreg r24,@1+1 inreg r25,@1+2 .elif r24_mpr inreg r24,@1 inreg r25,@1+1 inreg r26,@1+2 .elif r25_mpr inreg r25,@1 inreg r26,@1+1 inreg r27,@1+2 .elif r26_mpr inreg r26,@1 inreg r27,@1+1 inreg r28,@1+2 .elif r27_mpr inreg r27,@1 inreg r28,@1+1 inreg r29,@1+2 .elif r28_mpr inreg r28,@1 inreg r29,@1+1 inreg r30,@1+2 .elif r29_mpr inreg r29,@1 inreg r30,@1+1 inreg r31,@1+2 .else .error "Macro inreg24 reg zu gross" .endif .endm .macro inreg32 ; @0 r0-r28, @1 IO-RAM, 8c, 16b setr .set @0_mpr = 1 .if r0_mpr inreg r0,@1 inreg r1,@1+1 inreg r2,@1+2 inreg r3,@1+3 .elif r1_mpr inreg r1,@1 inreg r2,@1+1 inreg r3,@1+2 inreg r4,@1+3 .elif r2_mpr inreg r2,@1 inreg r3,@1+1 inreg r4,@1+2 inreg r5,@1+3 .elif r3_mpr inreg r3,@1 inreg r4,@1+1 inreg r5,@1+2 inreg r6,@1+3 .elif r4_mpr inreg r4,@1 inreg r5,@1+1 inreg r6,@1+2 inreg r7,@1+3 .elif r5_mpr inreg r5,@1 inreg r6,@1+1 inreg r7,@1+2 inreg r8,@1+3 .elif r6_mpr inreg r6,@1 inreg r7,@1+1 inreg r8,@1+2 inreg r9,@1+3 .elif r7_mpr inreg r7,@1 inreg r8,@1+1 inreg r9,@1+2 inreg r10,@1+3 .elif r8_mpr inreg r8,@1 inreg r9,@1+1 inreg r10,@1+2 inreg r11,@1+3 .elif r9_mpr inreg r9,@1 inreg r10,@1+1 inreg r11,@1+2 inreg r12,@1+3 .elif r10_mpr inreg r10,@1 inreg r11,@1+1 inreg r12,@1+2 inreg r13,@1+3 .elif r11_mpr inreg r11,@1 inreg r12,@1+1 inreg r13,@1+2 inreg r14,@1+3 .elif r12_mpr inreg r12,@1 inreg r13,@1+1 inreg r14,@1+2 inreg r15,@1+3 .elif r13_mpr inreg r13,@1 inreg r14,@1+1 inreg r15,@1+2 inreg r16,@1+3 .elif r14_mpr inreg r14,@1 inreg r15,@1+1 inreg r16,@1+2 inreg r17,@1+3 .elif r15_mpr inreg r15,@1 inreg r16,@1+1 inreg r17,@1+2 inreg r18,@1+3 .elif r16_mpr inreg r16,@1 inreg r17,@1+1 inreg r18,@1+2 inreg r19,@1+3 .elif r17_mpr inreg r17,@1 inreg r18,@1+1 inreg r19,@1+2 inreg r20,@1+3 .elif r18_mpr inreg r18,@1 inreg r19,@1+1 inreg r20,@1+2 inreg r21,@1+3 .elif r19_mpr inreg r19,@1 inreg r20,@1+1 inreg r21,@1+2 inreg r22,@1+3 .elif r20_mpr inreg r20,@1 inreg r21,@1+1 inreg r22,@1+2 inreg r23,@1+3 .elif r21_mpr inreg r21,@1 inreg r22,@1+1 inreg r23,@1+2 inreg r24,@1+3 .elif r22_mpr inreg r22,@1 inreg r23,@1+1 inreg r24,@1+2 inreg r25,@1+3 .elif r23_mpr inreg r23,@1 inreg r24,@1+1 inreg r25,@1+2 inreg r26,@1+3 .elif r24_mpr inreg r24,@1 inreg r25,@1+1 inreg r26,@1+2 inreg r27,@1+3 .elif r25_mpr inreg r25,@1 inreg r26,@1+1 inreg r27,@1+2 inreg r28,@1+3 .elif r26_mpr inreg r26,@1 inreg r27,@1+1 inreg r28,@1+2 inreg r29,@1+3 .elif r27_mpr inreg r27,@1 inreg r28,@1+1 inreg r29,@1+2 inreg r30,@1+3 .elif r28_mpr inreg r28,@1 inreg r29,@1+1 inreg r30,@1+2 inreg r31,@1+3 .else .error "Macro inreg32 reg zu gross" .endif .endm .macro inreg40 ; @0 r0-r27, @1 IO-RAM, 10c, 20b setr .set @0_mpr = 1 .if r0_mpr inreg r0,@1 inreg r1,@1+1 inreg r2,@1+2 inreg r3,@1+3 inreg r4,@1+4 .elif r1_mpr inreg r1,@1 inreg r2,@1+1 inreg r3,@1+2 inreg r4,@1+3 inreg r5,@1+4 .elif r2_mpr inreg r2,@1 inreg r3,@1+1 inreg r4,@1+2 inreg r5,@1+3 inreg r6,@1+4 .elif r3_mpr inreg r3,@1 inreg r4,@1+1 inreg r5,@1+2 inreg r6,@1+3 inreg r7,@1+4 .elif r4_mpr inreg r4,@1 inreg r5,@1+1 inreg r6,@1+2 inreg r7,@1+3 inreg r8,@1+4 .elif r5_mpr inreg r5,@1 inreg r6,@1+1 inreg r7,@1+2 inreg r8,@1+3 inreg r9,@1+4 .elif r6_mpr inreg r6,@1 inreg r7,@1+1 inreg r8,@1+2 inreg r9,@1+3 inreg r10,@1+4 .elif r7_mpr inreg r7,@1 inreg r8,@1+1 inreg r9,@1+2 inreg r10,@1+3 inreg r11,@1+4 .elif r8_mpr inreg r8,@1 inreg r9,@1+1 inreg r10,@1+2 inreg r11,@1+3 inreg r12,@1+4 .elif r9_mpr inreg r9,@1 inreg r10,@1+1 inreg r11,@1+2 inreg r12,@1+3 inreg r13,@1+4 .elif r10_mpr inreg r10,@1 inreg r11,@1+1 inreg r12,@1+2 inreg r13,@1+3 inreg r14,@1+4 .elif r11_mpr inreg r11,@1 inreg r12,@1+1 inreg r13,@1+2 inreg r14,@1+3 inreg r15,@1+4 .elif r12_mpr inreg r12,@1 inreg r13,@1+1 inreg r14,@1+2 inreg r15,@1+3 inreg r16,@1+4 .elif r13_mpr inreg r13,@1 inreg r14,@1+1 inreg r15,@1+2 inreg r16,@1+3 inreg r17,@1+4 .elif r14_mpr inreg r14,@1 inreg r15,@1+1 inreg r16,@1+2 inreg r17,@1+3 inreg r18,@1+4 .elif r15_mpr inreg r15,@1 inreg r16,@1+1 inreg r17,@1+2 inreg r18,@1+3 inreg r19,@1+4 .elif r16_mpr inreg r16,@1 inreg r17,@1+1 inreg r18,@1+2 inreg r19,@1+3 inreg r20,@1+4 .elif r17_mpr inreg r17,@1 inreg r18,@1+1 inreg r19,@1+2 inreg r20,@1+3 inreg r21,@1+4 .elif r18_mpr inreg r18,@1 inreg r19,@1+1 inreg r20,@1+2 inreg r21,@1+3 inreg r22,@1+4 .elif r19_mpr inreg r19,@1 inreg r20,@1+1 inreg r21,@1+2 inreg r22,@1+3 inreg r23,@1+4 .elif r20_mpr inreg r20,@1 inreg r21,@1+1 inreg r22,@1+2 inreg r23,@1+3 inreg r24,@1+4 .elif r21_mpr inreg r21,@1 inreg r22,@1+1 inreg r23,@1+2 inreg r24,@1+3 inreg r25,@1+4 .elif r22_mpr inreg r22,@1 inreg r23,@1+1 inreg r24,@1+2 inreg r25,@1+3 inreg r26,@1+4 .elif r23_mpr inreg r23,@1 inreg r24,@1+1 inreg r25,@1+2 inreg r26,@1+3 inreg r27,@1+4 .elif r24_mpr inreg r24,@1 inreg r25,@1+1 inreg r26,@1+2 inreg r27,@1+3 inreg r28,@1+4 .elif r25_mpr inreg r25,@1 inreg r26,@1+1 inreg r27,@1+2 inreg r28,@1+3 inreg r29,@1+4 .elif r26_mpr inreg r26,@1 inreg r27,@1+1 inreg r28,@1+2 inreg r29,@1+3 inreg r30,@1+4 .elif r27_mpr inreg r27,@1 inreg r28,@1+1 inreg r29,@1+2 inreg r30,@1+3 inreg r31,@1+4 .else .error "Macro inreg40 reg zu gross" .endif .endm .macro inreg48 ; @0 r0-r26, @1 IO-RAM, 12c, 24b setr .set @0_mpr = 1 .if r0_mpr inreg r0,@1 inreg r1,@1+1 inreg r2,@1+2 inreg r3,@1+3 inreg r4,@1+4 inreg r5,@1+5 .elif r1_mpr inreg r1,@1 inreg r2,@1+1 inreg r3,@1+2 inreg r4,@1+3 inreg r5,@1+4 inreg r6,@1+5 .elif r2_mpr inreg r2,@1 inreg r3,@1+1 inreg r4,@1+2 inreg r5,@1+3 inreg r6,@1+4 inreg r7,@1+5 .elif r3_mpr inreg r3,@1 inreg r4,@1+1 inreg r5,@1+2 inreg r6,@1+3 inreg r7,@1+4 inreg r8,@1+5 .elif r4_mpr inreg r4,@1 inreg r5,@1+1 inreg r6,@1+2 inreg r7,@1+3 inreg r8,@1+4 inreg r9,@1+5 .elif r5_mpr inreg r5,@1 inreg r6,@1+1 inreg r7,@1+2 inreg r8,@1+3 inreg r9,@1+4 inreg r10,@1+5 .elif r6_mpr inreg r6,@1 inreg r7,@1+1 inreg r8,@1+2 inreg r9,@1+3 inreg r10,@1+4 inreg r11,@1+5 .elif r7_mpr inreg r7,@1 inreg r8,@1+1 inreg r9,@1+2 inreg r10,@1+3 inreg r11,@1+4 inreg r12,@1+5 .elif r8_mpr inreg r8,@1 inreg r9,@1+1 inreg r10,@1+2 inreg r11,@1+3 inreg r12,@1+4 inreg r13,@1+5 .elif r9_mpr inreg r9,@1 inreg r10,@1+1 inreg r11,@1+2 inreg r12,@1+3 inreg r13,@1+4 inreg r14,@1+5 .elif r10_mpr inreg r10,@1 inreg r11,@1+1 inreg r12,@1+2 inreg r13,@1+3 inreg r14,@1+4 inreg r15,@1+5 .elif r11_mpr inreg r11,@1 inreg r12,@1+1 inreg r13,@1+2 inreg r14,@1+3 inreg r15,@1+4 inreg r16,@1+5 .elif r12_mpr inreg r12,@1 inreg r13,@1+1 inreg r14,@1+2 inreg r15,@1+3 inreg r16,@1+4 inreg r17,@1+5 .elif r13_mpr inreg r13,@1 inreg r14,@1+1 inreg r15,@1+2 inreg r16,@1+3 inreg r17,@1+4 inreg r18,@1+5 .elif r14_mpr inreg r14,@1 inreg r15,@1+1 inreg r16,@1+2 inreg r17,@1+3 inreg r18,@1+4 inreg r19,@1+5 .elif r15_mpr inreg r15,@1 inreg r16,@1+1 inreg r17,@1+2 inreg r18,@1+3 inreg r19,@1+4 inreg r20,@1+5 .elif r16_mpr inreg r16,@1 inreg r17,@1+1 inreg r18,@1+2 inreg r19,@1+3 inreg r20,@1+4 inreg r21,@1+5 .elif r17_mpr inreg r17,@1 inreg r18,@1+1 inreg r19,@1+2 inreg r20,@1+3 inreg r21,@1+4 inreg r22,@1+5 .elif r18_mpr inreg r18,@1 inreg r19,@1+1 inreg r20,@1+2 inreg r21,@1+3 inreg r22,@1+4 inreg r23,@1+5 .elif r19_mpr inreg r19,@1 inreg r20,@1+1 inreg r21,@1+2 inreg r22,@1+3 inreg r23,@1+4 inreg r24,@1+5 .elif r20_mpr inreg r20,@1 inreg r21,@1+1 inreg r22,@1+2 inreg r23,@1+3 inreg r24,@1+4 inreg r25,@1+5 .elif r21_mpr inreg r21,@1 inreg r22,@1+1 inreg r23,@1+2 inreg r24,@1+3 inreg r25,@1+4 inreg r26,@1+5 .elif r22_mpr inreg r22,@1 inreg r23,@1+1 inreg r24,@1+2 inreg r25,@1+3 inreg r26,@1+4 inreg r27,@1+5 .elif r23_mpr inreg r23,@1 inreg r24,@1+1 inreg r25,@1+2 inreg r26,@1+3 inreg r27,@1+4 inreg r28,@1+5 .elif r24_mpr inreg r24,@1 inreg r25,@1+1 inreg r26,@1+2 inreg r27,@1+3 inreg r28,@1+4 inreg r29,@1+5 .elif r25_mpr inreg r25,@1 inreg r26,@1+1 inreg r27,@1+2 inreg r28,@1+3 inreg r29,@1+4 inreg r30,@1+5 .elif r26_mpr inreg r26,@1 inreg r27,@1+1 inreg r28,@1+2 inreg r29,@1+3 inreg r30,@1+4 inreg r31,@1+5 .else .error "Macro inreg48 reg zu gross" .endif .endm .macro inreg56 ; @0 r0-r25, @1 IO-RAM, 14c, 28b setr .set @0_mpr = 1 .if r0_mpr inreg r0,@1 inreg r1,@1+1 inreg r2,@1+2 inreg r3,@1+3 inreg r4,@1+4 inreg r5,@1+5 inreg r6,@1+6 .elif r1_mpr inreg r1,@1 inreg r2,@1+1 inreg r3,@1+2 inreg r4,@1+3 inreg r5,@1+4 inreg r6,@1+5 inreg r7,@1+6 .elif r2_mpr inreg r2,@1 inreg r3,@1+1 inreg r4,@1+2 inreg r5,@1+3 inreg r6,@1+4 inreg r7,@1+5 inreg r8,@1+6 .elif r3_mpr inreg r3,@1 inreg r4,@1+1 inreg r5,@1+2 inreg r6,@1+3 inreg r7,@1+4 inreg r8,@1+5 inreg r9,@1+6 .elif r4_mpr inreg r4,@1 inreg r5,@1+1 inreg r6,@1+2 inreg r7,@1+3 inreg r8,@1+4 inreg r9,@1+5 inreg r10,@1+6 .elif r5_mpr inreg r5,@1 inreg r6,@1+1 inreg r7,@1+2 inreg r8,@1+3 inreg r9,@1+4 inreg r10,@1+5 inreg r11,@1+6 .elif r6_mpr inreg r6,@1 inreg r7,@1+1 inreg r8,@1+2 inreg r9,@1+3 inreg r10,@1+4 inreg r11,@1+5 inreg r12,@1+6 .elif r7_mpr inreg r7,@1 inreg r8,@1+1 inreg r9,@1+2 inreg r10,@1+3 inreg r11,@1+4 inreg r12,@1+5 inreg r13,@1+6 .elif r8_mpr inreg r8,@1 inreg r9,@1+1 inreg r10,@1+2 inreg r11,@1+3 inreg r12,@1+4 inreg r13,@1+5 inreg r14,@1+6 .elif r9_mpr inreg r9,@1 inreg r10,@1+1 inreg r11,@1+2 inreg r12,@1+3 inreg r13,@1+4 inreg r14,@1+5 inreg r15,@1+6 .elif r10_mpr inreg r10,@1 inreg r11,@1+1 inreg r12,@1+2 inreg r13,@1+3 inreg r14,@1+4 inreg r15,@1+5 inreg r16,@1+6 .elif r11_mpr inreg r11,@1 inreg r12,@1+1 inreg r13,@1+2 inreg r14,@1+3 inreg r15,@1+4 inreg r16,@1+5 inreg r17,@1+6 .elif r12_mpr inreg r12,@1 inreg r13,@1+1 inreg r14,@1+2 inreg r15,@1+3 inreg r16,@1+4 inreg r17,@1+5 inreg r18,@1+6 .elif r13_mpr inreg r13,@1 inreg r14,@1+1 inreg r15,@1+2 inreg r16,@1+3 inreg r17,@1+4 inreg r18,@1+5 inreg r19,@1+6 .elif r14_mpr inreg r14,@1 inreg r15,@1+1 inreg r16,@1+2 inreg r17,@1+3 inreg r18,@1+4 inreg r19,@1+5 inreg r20,@1+6 .elif r15_mpr inreg r15,@1 inreg r16,@1+1 inreg r17,@1+2 inreg r18,@1+3 inreg r19,@1+4 inreg r20,@1+5 inreg r21,@1+6 .elif r16_mpr inreg r16,@1 inreg r17,@1+1 inreg r18,@1+2 inreg r19,@1+3 inreg r20,@1+4 inreg r21,@1+5 inreg r22,@1+6 .elif r17_mpr inreg r17,@1 inreg r18,@1+1 inreg r19,@1+2 inreg r20,@1+3 inreg r21,@1+4 inreg r22,@1+5 inreg r23,@1+6 .elif r18_mpr inreg r18,@1 inreg r19,@1+1 inreg r20,@1+2 inreg r21,@1+3 inreg r22,@1+4 inreg r23,@1+5 inreg r24,@1+6 .elif r19_mpr inreg r19,@1 inreg r20,@1+1 inreg r21,@1+2 inreg r22,@1+3 inreg r23,@1+4 inreg r24,@1+5 inreg r25,@1+6 .elif r20_mpr inreg r20,@1 inreg r21,@1+1 inreg r22,@1+2 inreg r23,@1+3 inreg r24,@1+4 inreg r25,@1+5 inreg r26,@1+6 .elif r21_mpr inreg r21,@1 inreg r22,@1+1 inreg r23,@1+2 inreg r24,@1+3 inreg r25,@1+4 inreg r26,@1+5 inreg r27,@1+6 .elif r22_mpr inreg r22,@1 inreg r23,@1+1 inreg r24,@1+2 inreg r25,@1+3 inreg r26,@1+4 inreg r27,@1+5 inreg r28,@1+6 .elif r23_mpr inreg r23,@1 inreg r24,@1+1 inreg r25,@1+2 inreg r26,@1+3 inreg r27,@1+4 inreg r28,@1+5 inreg r29,@1+6 .elif r24_mpr inreg r24,@1 inreg r25,@1+1 inreg r26,@1+2 inreg r27,@1+3 inreg r28,@1+4 inreg r29,@1+5 inreg r30,@1+6 .elif r25_mpr inreg r25,@1 inreg r26,@1+1 inreg r27,@1+2 inreg r28,@1+3 inreg r29,@1+4 inreg r30,@1+5 inreg r31,@1+6 .else .error "Macro inreg56 reg zu gross" .endif .endm .macro inreg64 ; @0 r0-r24, @1 IO-RAM, 16c, 32b setr .set @0_mpr = 1 .if r0_mpr inreg r0,@1 inreg r1,@1+1 inreg r2,@1+2 inreg r3,@1+3 inreg r4,@1+4 inreg r5,@1+5 inreg r6,@1+6 inreg r7,@1+7 .elif r1_mpr inreg r1,@1 inreg r2,@1+1 inreg r3,@1+2 inreg r4,@1+3 inreg r5,@1+4 inreg r6,@1+5 inreg r7,@1+6 inreg r8,@1+7 .elif r2_mpr inreg r2,@1 inreg r3,@1+1 inreg r4,@1+2 inreg r5,@1+3 inreg r6,@1+4 inreg r7,@1+5 inreg r8,@1+6 inreg r9,@1+7 .elif r3_mpr inreg r3,@1 inreg r4,@1+1 inreg r5,@1+2 inreg r6,@1+3 inreg r7,@1+4 inreg r8,@1+5 inreg r9,@1+6 inreg r10,@1+7 .elif r4_mpr inreg r4,@1 inreg r5,@1+1 inreg r6,@1+2 inreg r7,@1+3 inreg r8,@1+4 inreg r9,@1+5 inreg r10,@1+6 inreg r11,@1+7 .elif r5_mpr inreg r5,@1 inreg r6,@1+1 inreg r7,@1+2 inreg r8,@1+3 inreg r9,@1+4 inreg r10,@1+5 inreg r11,@1+6 inreg r12,@1+7 .elif r6_mpr inreg r6,@1 inreg r7,@1+1 inreg r8,@1+2 inreg r9,@1+3 inreg r10,@1+4 inreg r11,@1+5 inreg r12,@1+6 inreg r13,@1+7 .elif r7_mpr inreg r7,@1 inreg r8,@1+1 inreg r9,@1+2 inreg r10,@1+3 inreg r11,@1+4 inreg r12,@1+5 inreg r13,@1+6 inreg r14,@1+7 .elif r8_mpr inreg r8,@1 inreg r9,@1+1 inreg r10,@1+2 inreg r11,@1+3 inreg r12,@1+4 inreg r13,@1+5 inreg r14,@1+6 inreg r15,@1+7 .elif r9_mpr inreg r9,@1 inreg r10,@1+1 inreg r11,@1+2 inreg r12,@1+3 inreg r13,@1+4 inreg r14,@1+5 inreg r15,@1+6 inreg r16,@1+7 .elif r10_mpr inreg r10,@1 inreg r11,@1+1 inreg r12,@1+2 inreg r13,@1+3 inreg r14,@1+4 inreg r15,@1+5 inreg r16,@1+6 inreg r17,@1+7 .elif r11_mpr inreg r11,@1 inreg r12,@1+1 inreg r13,@1+2 inreg r14,@1+3 inreg r15,@1+4 inreg r16,@1+5 inreg r17,@1+6 inreg r18,@1+7 .elif r12_mpr inreg r12,@1 inreg r13,@1+1 inreg r14,@1+2 inreg r15,@1+3 inreg r16,@1+4 inreg r17,@1+5 inreg r18,@1+6 inreg r19,@1+7 .elif r13_mpr inreg r13,@1 inreg r14,@1+1 inreg r15,@1+2 inreg r16,@1+3 inreg r17,@1+4 inreg r18,@1+5 inreg r19,@1+6 inreg r20,@1+7 .elif r14_mpr inreg r14,@1 inreg r15,@1+1 inreg r16,@1+2 inreg r17,@1+3 inreg r18,@1+4 inreg r19,@1+5 inreg r20,@1+6 inreg r21,@1+7 .elif r15_mpr inreg r15,@1 inreg r16,@1+1 inreg r17,@1+2 inreg r18,@1+3 inreg r19,@1+4 inreg r20,@1+5 inreg r21,@1+6 inreg r22,@1+7 .elif r16_mpr inreg r16,@1 inreg r17,@1+1 inreg r18,@1+2 inreg r19,@1+3 inreg r20,@1+4 inreg r21,@1+5 inreg r22,@1+6 inreg r23,@1+7 .elif r17_mpr inreg r17,@1 inreg r18,@1+1 inreg r19,@1+2 inreg r20,@1+3 inreg r21,@1+4 inreg r22,@1+5 inreg r23,@1+6 inreg r24,@1+7 .elif r18_mpr inreg r18,@1 inreg r19,@1+1 inreg r20,@1+2 inreg r21,@1+3 inreg r22,@1+4 inreg r23,@1+5 inreg r24,@1+6 inreg r25,@1+7 .elif r19_mpr inreg r19,@1 inreg r20,@1+1 inreg r21,@1+2 inreg r22,@1+3 inreg r23,@1+4 inreg r24,@1+5 inreg r25,@1+6 inreg r26,@1+7 .elif r20_mpr inreg r20,@1 inreg r21,@1+1 inreg r22,@1+2 inreg r23,@1+3 inreg r24,@1+4 inreg r25,@1+5 inreg r26,@1+6 inreg r27,@1+7 .elif r21_mpr inreg r21,@1 inreg r22,@1+1 inreg r23,@1+2 inreg r24,@1+3 inreg r25,@1+4 inreg r26,@1+5 inreg r27,@1+6 inreg r28,@1+7 .elif r22_mpr inreg r22,@1 inreg r23,@1+1 inreg r24,@1+2 inreg r25,@1+3 inreg r26,@1+4 inreg r27,@1+5 inreg r28,@1+6 inreg r29,@1+7 .elif r23_mpr inreg r23,@1 inreg r24,@1+1 inreg r25,@1+2 inreg r26,@1+3 inreg r27,@1+4 inreg r28,@1+5 inreg r29,@1+6 inreg r30,@1+7 .elif r24_mpr inreg r24,@1 inreg r25,@1+1 inreg r26,@1+2 inreg r27,@1+3 inreg r28,@1+4 inreg r29,@1+5 inreg r30,@1+6 inreg r31,@1+7 .else .error "Macro inreg64 reg zu gross" .endif .endm ;========================================================================= ;=== outreg ============================================================== ;========================================================================= .macro outreg16 ; @0 IO-RAM, @1 r0-r30, 2-4c, 4-8b setr .set @1_mpr = 1 .if r0_mpr outreg @0,r0 outreg @0+1,r1 .elif r1_mpr outreg @0,r1 outreg @0+1,r2 .elif r2_mpr outreg @0,r2 outreg @0+1,r3 .elif r3_mpr outreg @0,r3 outreg @0+1,r4 .elif r4_mpr outreg @0,r4 outreg @0+1,r5 .elif r5_mpr outreg @0,r5 outreg @0+1,r6 .elif r6_mpr outreg @0,r6 outreg @0+1,r7 .elif r7_mpr outreg @0,r7 outreg @0+1,r8 .elif r8_mpr outreg @0,r8 outreg @0+1,r9 .elif r9_mpr outreg @0,r9 outreg @0+1,r10 .elif r10_mpr outreg @0,r10 outreg @0+1,r11 .elif r11_mpr outreg @0,r11 outreg @0+1,r12 .elif r12_mpr outreg @0,r12 outreg @0+1,r13 .elif r13_mpr outreg @0,r13 outreg @0+1,r14 .elif r14_mpr outreg @0,r14 outreg @0+1,r15 .elif r15_mpr outreg @0,r15 outreg @0+1,r16 .elif r16_mpr outreg @0,r16 outreg @0+1,r17 .elif r17_mpr outreg @0,r17 outreg @0+1,r18 .elif r18_mpr outreg @0,r18 outreg @0+1,r19 .elif r19_mpr outreg @0,r19 outreg @0+1,r20 .elif r20_mpr outreg @0,r20 outreg @0+1,r21 .elif r21_mpr outreg @0,r21 outreg @0+1,r22 .elif r22_mpr outreg @0,r22 outreg @0+1,r23 .elif r23_mpr outreg @0,r23 outreg @0+1,r24 .elif r24_mpr || temp_mpr || templ_mpr outreg @0,r24 outreg @0+1,r25 .elif r25_mpr || temph_mpr outreg @0,r25 outreg @0+1,r26 .elif r26_mpr || xl_mpr || X_mpr outreg @0,r26 outreg @0+1,r27 .elif r27_mpr || xh_mpr outreg @0,r27 outreg @0+1,r28 .elif r28_mpr || yl_mpr || Y_mpr outreg @0,r28 outreg @0+1,r29 .elif r29_mpr || yh_mpr outreg @0,r29 outreg @0+1,r30 .elif r30_mpr || zl_mpr || Z_mpr outreg @0,r30 outreg @0+1,r31 .else .error "Macro outreg16 reg zu gross" .endif .endm .macro outreg24 ; @0 IO-RAM, @1 r0-r29, 3-6c, 6-12b setr .set @1_mpr = 1 .if r0_mpr outreg @0,r0 outreg @0+1,r1 outreg @0+2,r2 .elif r1_mpr outreg @0,r1 outreg @0+1,r2 outreg @0+2,r3 .elif r2_mpr outreg @0,r2 outreg @0+1,r3 outreg @0+2,r4 .elif r3_mpr outreg @0,r3 outreg @0+1,r4 outreg @0+2,r5 .elif r4_mpr outreg @0,r4 outreg @0+1,r5 outreg @0+2,r6 .elif r5_mpr outreg @0,r5 outreg @0+1,r6 outreg @0+2,r7 .elif r6_mpr outreg @0,r6 outreg @0+1,r7 outreg @0+2,r8 .elif r7_mpr outreg @0,r7 outreg @0+1,r8 outreg @0+2,r9 .elif r8_mpr outreg @0,r8 outreg @0+1,r9 outreg @0+2,r10 .elif r9_mpr outreg @0,r9 outreg @0+1,r10 outreg @0+2,r11 .elif r10_mpr outreg @0,r10 outreg @0+1,r11 outreg @0+2,r12 .elif r11_mpr outreg @0,r11 outreg @0+1,r12 outreg @0+2,r13 .elif r12_mpr outreg @0,r12 outreg @0+1,r13 outreg @0+2,r14 .elif r13_mpr outreg @0,r13 outreg @0+1,r14 outreg @0+2,r15 .elif r14_mpr outreg @0,r14 outreg @0+1,r15 outreg @0+2,r16 .elif r15_mpr outreg @0,r15 outreg @0+1,r16 outreg @0+2,r17 .elif r16_mpr outreg @0,r16 outreg @0+1,r17 outreg @0+2,r18 .elif r17_mpr outreg @0,r17 outreg @0+1,r18 outreg @0+2,r19 .elif r18_mpr outreg @0,r18 outreg @0+1,r19 outreg @0+2,r20 .elif r19_mpr outreg @0,r19 outreg @0+1,r20 outreg @0+2,r21 .elif r20_mpr outreg @0,r20 outreg @0+1,r21 outreg @0+2,r22 .elif r21_mpr outreg @0,r21 outreg @0+1,r22 outreg @0+2,r23 .elif r22_mpr outreg @0,r22 outreg @0+1,r23 outreg @0+2,r24 .elif r23_mpr outreg @0,r23 outreg @0+1,r24 outreg @0+2,r25 .elif r24_mpr outreg @0,r24 outreg @0+1,r25 outreg @0+2,r26 .elif r25_mpr outreg @0,r25 outreg @0+1,r26 outreg @0+2,r27 .elif r26_mpr outreg @0,r26 outreg @0+1,r27 outreg @0+2,r28 .elif r27_mpr outreg @0,r27 outreg @0+1,r28 outreg @0+2,r29 .elif r28_mpr outreg @0,r28 outreg @0+1,r29 outreg @0+2,r30 .elif r29_mpr outreg @0,r29 outreg @0+1,r30 outreg @0+2,r31 .else .error "Macro outreg24 reg zu gross" .endif .endm .macro outreg32 ; @0 IO-RAM, @1 r0-r28, 8c, 16b setr .set @1_mpr = 1 .if r0_mpr outreg @0,r0 outreg @0+1,r1 outreg @0+2,r2 outreg @0+3,r3 .elif r1_mpr outreg @0,r1 outreg @0+1,r2 outreg @0+2,r3 outreg @0+3,r4 .elif r2_mpr outreg @0,r2 outreg @0+1,r3 outreg @0+2,r4 outreg @0+3,r5 .elif r3_mpr outreg @0,r3 outreg @0+1,r4 outreg @0+2,r5 outreg @0+3,r6 .elif r4_mpr outreg @0,r4 outreg @0+1,r5 outreg @0+2,r6 outreg @0+3,r7 .elif r5_mpr outreg @0,r5 outreg @0+1,r6 outreg @0+2,r7 outreg @0+3,r8 .elif r6_mpr outreg @0,r6 outreg @0+1,r7 outreg @0+2,r8 outreg @0+3,r9 .elif r7_mpr outreg @0,r7 outreg @0+1,r8 outreg @0+2,r9 outreg @0+3,r10 .elif r8_mpr outreg @0,r8 outreg @0+1,r9 outreg @0+2,r10 outreg @0+3,r11 .elif r9_mpr outreg @0,r9 outreg @0+1,r10 outreg @0+2,r11 outreg @0+3,r12 .elif r10_mpr outreg @0,r10 outreg @0+1,r11 outreg @0+2,r12 outreg @0+3,r13 .elif r11_mpr outreg @0,r11 outreg @0+1,r12 outreg @0+2,r13 outreg @0+3,r14 .elif r12_mpr outreg @0,r12 outreg @0+1,r13 outreg @0+2,r14 outreg @0+3,r15 .elif r13_mpr outreg @0,r13 outreg @0+1,r14 outreg @0+2,r15 outreg @0+3,r16 .elif r14_mpr outreg @0,r14 outreg @0+1,r15 outreg @0+2,r16 outreg @0+3,r17 .elif r15_mpr outreg @0,r15 outreg @0+1,r16 outreg @0+2,r17 outreg @0+3,r18 .elif r16_mpr outreg @0,r16 outreg @0+1,r17 outreg @0+2,r18 outreg @0+3,r19 .elif r17_mpr outreg @0,r17 outreg @0+1,r18 outreg @0+2,r19 outreg @0+3,r20 .elif r18_mpr outreg @0,r18 outreg @0+1,r19 outreg @0+2,r20 outreg @0+3,r21 .elif r19_mpr outreg @0,r19 outreg @0+1,r20 outreg @0+2,r21 outreg @0+3,r22 .elif r20_mpr outreg @0,r20 outreg @0+1,r21 outreg @0+2,r22 outreg @0+3,r23 .elif r21_mpr outreg @0,r21 outreg @0+1,r22 outreg @0+2,r23 outreg @0+3,r24 .elif r22_mpr outreg @0,r22 outreg @0+1,r23 outreg @0+2,r24 outreg @0+3,r25 .elif r23_mpr outreg @0,r23 outreg @0+1,r24 outreg @0+2,r25 outreg @0+3,r26 .elif r24_mpr outreg @0,r24 outreg @0+1,r25 outreg @0+2,r26 outreg @0+3,r27 .elif r25_mpr outreg @0,r25 outreg @0+1,r26 outreg @0+2,r27 outreg @0+3,r28 .elif r26_mpr outreg @0,r26 outreg @0+1,r27 outreg @0+2,r28 outreg @0+3,r29 .elif r27_mpr outreg @0,r27 outreg @0+1,r28 outreg @0+2,r29 outreg @0+3,r30 .elif r28_mpr outreg @0,r28 outreg @0+1,r29 outreg @0+2,r30 outreg @0+3,r31 .else .error "Macro outreg32 reg zu gross" .endif .endm .macro outreg40 ; @0 IO-RAM, @1 r0-r27, 10c, 20b setr .set @1_mpr = 1 .if r0_mpr outreg @0,r0 outreg @0+1,r1 outreg @0+2,r2 outreg @0+3,r3 outreg @0+4,r4 .elif r1_mpr outreg @0,r1 outreg @0+1,r2 outreg @0+2,r3 outreg @0+3,r4 outreg @0+4,r5 .elif r2_mpr outreg @0,r2 outreg @0+1,r3 outreg @0+2,r4 outreg @0+3,r5 outreg @0+4,r6 .elif r3_mpr outreg @0,r3 outreg @0+1,r4 outreg @0+2,r5 outreg @0+3,r6 outreg @0+4,r7 .elif r4_mpr outreg @0,r4 outreg @0+1,r5 outreg @0+2,r6 outreg @0+3,r7 outreg @0+4,r8 .elif r5_mpr outreg @0,r5 outreg @0+1,r6 outreg @0+2,r7 outreg @0+3,r8 outreg @0+4,r9 .elif r6_mpr outreg @0,r6 outreg @0+1,r7 outreg @0+2,r8 outreg @0+3,r9 outreg @0+4,r10 .elif r7_mpr outreg @0,r7 outreg @0+1,r8 outreg @0+2,r9 outreg @0+3,r10 outreg @0+4,r11 .elif r8_mpr outreg @0,r8 outreg @0+1,r9 outreg @0+2,r10 outreg @0+3,r11 outreg @0+4,r12 .elif r9_mpr outreg @0,r9 outreg @0+1,r10 outreg @0+2,r11 outreg @0+3,r12 outreg @0+4,r13 .elif r10_mpr outreg @0,r10 outreg @0+1,r11 outreg @0+2,r12 outreg @0+3,r13 outreg @0+4,r14 .elif r11_mpr outreg @0,r11 outreg @0+1,r12 outreg @0+2,r13 outreg @0+3,r14 outreg @0+4,r15 .elif r12_mpr outreg @0,r12 outreg @0+1,r13 outreg @0+2,r14 outreg @0+3,r15 outreg @0+4,r16 .elif r13_mpr outreg @0,r13 outreg @0+1,r14 outreg @0+2,r15 outreg @0+3,r16 outreg @0+4,r17 .elif r14_mpr outreg @0,r14 outreg @0+1,r15 outreg @0+2,r16 outreg @0+3,r17 outreg @0+4,r18 .elif r15_mpr outreg @0,r15 outreg @0+1,r16 outreg @0+2,r17 outreg @0+3,r18 outreg @0+4,r19 .elif r16_mpr outreg @0,r16 outreg @0+1,r17 outreg @0+2,r18 outreg @0+3,r19 outreg @0+4,r20 .elif r17_mpr outreg @0,r17 outreg @0+1,r18 outreg @0+2,r19 outreg @0+3,r20 outreg @0+4,r21 .elif r18_mpr outreg @0,r18 outreg @0+1,r19 outreg @0+2,r20 outreg @0+3,r21 outreg @0+4,r22 .elif r19_mpr outreg @0,r19 outreg @0+1,r20 outreg @0+2,r21 outreg @0+3,r22 outreg @0+4,r23 .elif r20_mpr outreg @0,r20 outreg @0+1,r21 outreg @0+2,r22 outreg @0+3,r23 outreg @0+4,r24 .elif r21_mpr outreg @0,r21 outreg @0+1,r22 outreg @0+2,r23 outreg @0+3,r24 outreg @0+4,r25 .elif r22_mpr outreg @0,r22 outreg @0+1,r23 outreg @0+2,r24 outreg @0+3,r25 outreg @0+4,r26 .elif r23_mpr outreg @0,r23 outreg @0+1,r24 outreg @0+2,r25 outreg @0+3,r26 outreg @0+4,r27 .elif r24_mpr outreg @0,r24 outreg @0+1,r25 outreg @0+2,r26 outreg @0+3,r27 outreg @0+4,r28 .elif r25_mpr outreg @0,r25 outreg @0+1,r26 outreg @0+2,r27 outreg @0+3,r28 outreg @0+4,r29 .elif r26_mpr outreg @0,r26 outreg @0+1,r27 outreg @0+2,r28 outreg @0+3,r29 outreg @0+4,r30 .elif r27_mpr outreg @0,r27 outreg @0+1,r28 outreg @0+2,r29 outreg @0+3,r30 outreg @0+4,r31 .else .error "Macro outreg40 reg zu gross" .endif .endm .macro outreg48 ; @0 IO-RAM, @1 r0-r26. 12c, 24b setr .set @1_mpr = 1 .if r0_mpr outreg @0,r0 outreg @0+1,r1 outreg @0+2,r2 outreg @0+3,r3 outreg @0+4,r4 outreg @0+5,r5 .elif r1_mpr outreg @0,r1 outreg @0+1,r2 outreg @0+2,r3 outreg @0+3,r4 outreg @0+4,r5 outreg @0+5,r6 .elif r2_mpr outreg @0,r2 outreg @0+1,r3 outreg @0+2,r4 outreg @0+3,r5 outreg @0+4,r6 outreg @0+5,r7 .elif r3_mpr outreg @0,r3 outreg @0+1,r4 outreg @0+2,r5 outreg @0+3,r6 outreg @0+4,r7 outreg @0+5,r8 .elif r4_mpr outreg @0,r4 outreg @0+1,r5 outreg @0+2,r6 outreg @0+3,r7 outreg @0+4,r8 outreg @0+5,r9 .elif r5_mpr outreg @0,r5 outreg @0+1,r6 outreg @0+2,r7 outreg @0+3,r8 outreg @0+4,r9 outreg @0+5,r10 .elif r6_mpr outreg @0,r6 outreg @0+1,r7 outreg @0+2,r8 outreg @0+3,r9 outreg @0+4,r10 outreg @0+5,r11 .elif r7_mpr outreg @0,r7 outreg @0+1,r8 outreg @0+2,r9 outreg @0+3,r10 outreg @0+4,r11 outreg @0+5,r12 .elif r8_mpr outreg @0,r8 outreg @0+1,r9 outreg @0+2,r10 outreg @0+3,r11 outreg @0+4,r12 outreg @0+5,r13 .elif r9_mpr outreg @0,r9 outreg @0+1,r10 outreg @0+2,r11 outreg @0+3,r12 outreg @0+4,r13 outreg @0+5,r14 .elif r10_mpr outreg @0,r10 outreg @0+1,r11 outreg @0+2,r12 outreg @0+3,r13 outreg @0+4,r14 outreg @0+5,r15 .elif r11_mpr outreg @0,r11 outreg @0+1,r12 outreg @0+2,r13 outreg @0+3,r14 outreg @0+4,r15 outreg @0+5,r16 .elif r12_mpr outreg @0,r12 outreg @0+1,r13 outreg @0+2,r14 outreg @0+3,r15 outreg @0+4,r16 outreg @0+5,r17 .elif r13_mpr outreg @0,r13 outreg @0+1,r14 outreg @0+2,r15 outreg @0+3,r16 outreg @0+4,r17 outreg @0+5,r18 .elif r14_mpr outreg @0,r14 outreg @0+1,r15 outreg @0+2,r16 outreg @0+3,r17 outreg @0+4,r18 outreg @0+5,r19 .elif r15_mpr outreg @0,r15 outreg @0+1,r16 outreg @0+2,r17 outreg @0+3,r18 outreg @0+4,r19 outreg @0+5,r20 .elif r16_mpr outreg @0,r16 outreg @0+1,r17 outreg @0+2,r18 outreg @0+3,r19 outreg @0+4,r20 outreg @0+5,r21 .elif r17_mpr outreg @0,r17 outreg @0+1,r18 outreg @0+2,r19 outreg @0+3,r20 outreg @0+4,r21 outreg @0+5,r22 .elif r18_mpr outreg @0,r18 outreg @0+1,r19 outreg @0+2,r20 outreg @0+3,r21 outreg @0+4,r22 outreg @0+5,r23 .elif r19_mpr outreg @0,r19 outreg @0+1,r20 outreg @0+2,r21 outreg @0+3,r22 outreg @0+4,r23 outreg @0+5,r24 .elif r20_mpr outreg @0,r20 outreg @0+1,r21 outreg @0+2,r22 outreg @0+3,r23 outreg @0+4,r24 outreg @0+5,r25 .elif r21_mpr outreg @0,r21 outreg @0+1,r22 outreg @0+2,r23 outreg @0+3,r24 outreg @0+4,r25 outreg @0+5,r26 .elif r22_mpr outreg @0,r22 outreg @0+1,r23 outreg @0+2,r24 outreg @0+3,r25 outreg @0+4,r26 outreg @0+5,r27 .elif r23_mpr outreg @0,r23 outreg @0+1,r24 outreg @0+2,r25 outreg @0+3,r26 outreg @0+4,r27 outreg @0+5,r28 .elif r24_mpr outreg @0,r24 outreg @0+1,r25 outreg @0+2,r26 outreg @0+3,r27 outreg @0+4,r28 outreg @0+5,r29 .elif r25_mpr outreg @0,r25 outreg @0+1,r26 outreg @0+2,r27 outreg @0+3,r28 outreg @0+4,r29 outreg @0+5,r30 .elif r26_mpr outreg @0,r26 outreg @0+1,r27 outreg @0+2,r28 outreg @0+3,r29 outreg @0+4,r30 outreg @0+5,r31 .else .error "Macro outreg48 reg zu gross" .endif .endm .macro outreg56 ; @0 IO-RAM, @1 r0-r25. 14c, 28b setr .set @1_mpr = 1 .if r0_mpr outreg @0,r0 outreg @0+1,r1 outreg @0+2,r2 outreg @0+3,r3 outreg @0+4,r4 outreg @0+5,r5 outreg @0+6,r6 .elif r1_mpr outreg @0,r1 outreg @0+1,r2 outreg @0+2,r3 outreg @0+3,r4 outreg @0+4,r5 outreg @0+5,r6 outreg @0+6,r7 .elif r2_mpr outreg @0,r2 outreg @0+1,r3 outreg @0+2,r4 outreg @0+3,r5 outreg @0+4,r6 outreg @0+5,r7 outreg @0+6,r8 .elif r3_mpr outreg @0,r3 outreg @0+1,r4 outreg @0+2,r5 outreg @0+3,r6 outreg @0+4,r7 outreg @0+5,r8 outreg @0+6,r9 .elif r4_mpr outreg @0,r4 outreg @0+1,r5 outreg @0+2,r6 outreg @0+3,r7 outreg @0+4,r8 outreg @0+5,r9 outreg @0+6,r10 .elif r5_mpr outreg @0,r5 outreg @0+1,r6 outreg @0+2,r7 outreg @0+3,r8 outreg @0+4,r9 outreg @0+5,r10 outreg @0+6,r11 .elif r6_mpr outreg @0,r6 outreg @0+1,r7 outreg @0+2,r8 outreg @0+3,r9 outreg @0+4,r10 outreg @0+5,r11 outreg @0+6,r12 .elif r7_mpr outreg @0,r7 outreg @0+1,r8 outreg @0+2,r9 outreg @0+3,r10 outreg @0+4,r11 outreg @0+5,r12 outreg @0+6,r13 .elif r8_mpr outreg @0,r8 outreg @0+1,r9 outreg @0+2,r10 outreg @0+3,r11 outreg @0+4,r12 outreg @0+5,r13 outreg @0+6,r14 .elif r9_mpr outreg @0,r9 outreg @0+1,r10 outreg @0+2,r11 outreg @0+3,r12 outreg @0+4,r13 outreg @0+5,r14 outreg @0+6,r15 .elif r10_mpr outreg @0,r10 outreg @0+1,r11 outreg @0+2,r12 outreg @0+3,r13 outreg @0+4,r14 outreg @0+5,r15 outreg @0+6,r16 .elif r11_mpr outreg @0,r11 outreg @0+1,r12 outreg @0+2,r13 outreg @0+3,r14 outreg @0+4,r15 outreg @0+5,r16 outreg @0+6,r17 .elif r12_mpr outreg @0,r12 outreg @0+1,r13 outreg @0+2,r14 outreg @0+3,r15 outreg @0+4,r16 outreg @0+5,r17 outreg @0+6,r18 .elif r13_mpr outreg @0,r13 outreg @0+1,r14 outreg @0+2,r15 outreg @0+3,r16 outreg @0+4,r17 outreg @0+5,r18 outreg @0+6,r19 .elif r14_mpr outreg @0,r14 outreg @0+1,r15 outreg @0+2,r16 outreg @0+3,r17 outreg @0+4,r18 outreg @0+5,r19 outreg @0+6,r20 .elif r15_mpr outreg @0,r15 outreg @0+1,r16 outreg @0+2,r17 outreg @0+3,r18 outreg @0+4,r19 outreg @0+5,r20 outreg @0+6,r21 .elif r16_mpr outreg @0,r16 outreg @0+1,r17 outreg @0+2,r18 outreg @0+3,r19 outreg @0+4,r20 outreg @0+5,r21 outreg @0+6,r22 .elif r17_mpr outreg @0,r17 outreg @0+1,r18 outreg @0+2,r19 outreg @0+3,r20 outreg @0+4,r21 outreg @0+5,r22 outreg @0+6,r23 .elif r18_mpr outreg @0,r18 outreg @0+1,r19 outreg @0+2,r20 outreg @0+3,r21 outreg @0+4,r22 outreg @0+5,r23 outreg @0+6,r24 .elif r19_mpr outreg @0,r19 outreg @0+1,r20 outreg @0+2,r21 outreg @0+3,r22 outreg @0+4,r23 outreg @0+5,r24 outreg @0+6,r25 .elif r20_mpr outreg @0,r20 outreg @0+1,r21 outreg @0+2,r22 outreg @0+3,r23 outreg @0+4,r24 outreg @0+5,r25 outreg @0+6,r26 .elif r21_mpr outreg @0,r21 outreg @0+1,r22 outreg @0+2,r23 outreg @0+3,r24 outreg @0+4,r25 outreg @0+5,r26 outreg @0+6,r27 .elif r22_mpr outreg @0,r22 outreg @0+1,r23 outreg @0+2,r24 outreg @0+3,r25 outreg @0+4,r26 outreg @0+5,r27 outreg @0+6,r28 .elif r23_mpr outreg @0,r23 outreg @0+1,r24 outreg @0+2,r25 outreg @0+3,r26 outreg @0+4,r27 outreg @0+5,r28 outreg @0+6,r29 .elif r24_mpr outreg @0,r24 outreg @0+1,r25 outreg @0+2,r26 outreg @0+3,r27 outreg @0+4,r28 outreg @0+5,r29 outreg @0+6,r30 .elif r25_mpr outreg @0,r25 outreg @0+1,r26 outreg @0+2,r27 outreg @0+3,r28 outreg @0+4,r29 outreg @0+5,r30 outreg @0+6,r31 .else .error "Macro outreg56 reg zu gross" .endif .endm .macro outreg64 ; @0 IO-RAM, @1 r0-r24, 16c, 32b setr .set @1_mpr = 1 .if r0_mpr outreg @0,r0 outreg @0+1,r1 outreg @0+2,r2 outreg @0+3,r3 outreg @0+4,r4 outreg @0+5,r5 outreg @0+6,r6 outreg @0+7,r7 .elif r1_mpr outreg @0,r1 outreg @0+1,r2 outreg @0+2,r3 outreg @0+3,r4 outreg @0+4,r5 outreg @0+5,r6 outreg @0+6,r7 outreg @0+7,r8 .elif r2_mpr outreg @0,r2 outreg @0+1,r3 outreg @0+2,r4 outreg @0+3,r5 outreg @0+4,r6 outreg @0+5,r7 outreg @0+6,r8 outreg @0+7,r9 .elif r3_mpr outreg @0,r3 outreg @0+1,r4 outreg @0+2,r5 outreg @0+3,r6 outreg @0+4,r7 outreg @0+5,r8 outreg @0+6,r9 outreg @0+7,r10 .elif r4_mpr outreg @0,r4 outreg @0+1,r5 outreg @0+2,r6 outreg @0+3,r7 outreg @0+4,r8 outreg @0+5,r9 outreg @0+6,r10 outreg @0+7,r11 .elif r5_mpr outreg @0,r5 outreg @0+1,r6 outreg @0+2,r7 outreg @0+3,r8 outreg @0+4,r9 outreg @0+5,r10 outreg @0+6,r11 outreg @0+7,r12 .elif r6_mpr outreg @0,r6 outreg @0+1,r7 outreg @0+2,r8 outreg @0+3,r9 outreg @0+4,r10 outreg @0+5,r11 outreg @0+6,r12 outreg @0+7,r13 .elif r7_mpr outreg @0,r7 outreg @0+1,r8 outreg @0+2,r9 outreg @0+3,r10 outreg @0+4,r11 outreg @0+5,r12 outreg @0+6,r13 outreg @0+7,r14 .elif r8_mpr outreg @0,r8 outreg @0+1,r9 outreg @0+2,r10 outreg @0+3,r11 outreg @0+4,r12 outreg @0+5,r13 outreg @0+6,r14 outreg @0+7,r15 .elif r9_mpr outreg @0,r9 outreg @0+1,r10 outreg @0+2,r11 outreg @0+3,r12 outreg @0+4,r13 outreg @0+5,r14 outreg @0+6,r15 outreg @0+7,r16 .elif r10_mpr outreg @0,r10 outreg @0+1,r11 outreg @0+2,r12 outreg @0+3,r13 outreg @0+4,r14 outreg @0+5,r15 outreg @0+6,r16 outreg @0+7,r17 .elif r11_mpr outreg @0,r11 outreg @0+1,r12 outreg @0+2,r13 outreg @0+3,r14 outreg @0+4,r15 outreg @0+5,r16 outreg @0+6,r17 outreg @0+7,r18 .elif r12_mpr outreg @0,r12 outreg @0+1,r13 outreg @0+2,r14 outreg @0+3,r15 outreg @0+4,r16 outreg @0+5,r17 outreg @0+6,r18 outreg @0+7,r19 .elif r13_mpr outreg @0,r13 outreg @0+1,r14 outreg @0+2,r15 outreg @0+3,r16 outreg @0+4,r17 outreg @0+5,r18 outreg @0+6,r19 outreg @0+7,r20 .elif r14_mpr outreg @0,r14 outreg @0+1,r15 outreg @0+2,r16 outreg @0+3,r17 outreg @0+4,r18 outreg @0+5,r19 outreg @0+6,r20 outreg @0+7,r21 .elif r15_mpr outreg @0,r15 outreg @0+1,r16 outreg @0+2,r17 outreg @0+3,r18 outreg @0+4,r19 outreg @0+5,r20 outreg @0+6,r21 outreg @0+7,r22 .elif r16_mpr outreg @0,r16 outreg @0+1,r17 outreg @0+2,r18 outreg @0+3,r19 outreg @0+4,r20 outreg @0+5,r21 outreg @0+6,r22 outreg @0+7,r23 .elif r17_mpr outreg @0,r17 outreg @0+1,r18 outreg @0+2,r19 outreg @0+3,r20 outreg @0+4,r21 outreg @0+5,r22 outreg @0+6,r23 outreg @0+7,r24 .elif r18_mpr outreg @0,r18 outreg @0+1,r19 outreg @0+2,r20 outreg @0+3,r21 outreg @0+4,r22 outreg @0+5,r23 outreg @0+6,r24 outreg @0+7,r25 .elif r19_mpr outreg @0,r19 outreg @0+1,r20 outreg @0+2,r21 outreg @0+3,r22 outreg @0+4,r23 outreg @0+5,r24 outreg @0+6,r25 outreg @0+7,r26 .elif r20_mpr outreg @0,r20 outreg @0+1,r21 outreg @0+2,r22 outreg @0+3,r23 outreg @0+4,r24 outreg @0+5,r25 outreg @0+6,r26 outreg @0+7,r27 .elif r21_mpr outreg @0,r21 outreg @0+1,r22 outreg @0+2,r23 outreg @0+3,r24 outreg @0+4,r25 outreg @0+5,r26 outreg @0+6,r27 outreg @0+7,r28 .elif r22_mpr outreg @0,r22 outreg @0+1,r23 outreg @0+2,r24 outreg @0+3,r25 outreg @0+4,r26 outreg @0+5,r27 outreg @0+6,r28 outreg @0+7,r29 .elif r23_mpr outreg @0,r23 outreg @0+1,r24 outreg @0+2,r25 outreg @0+3,r26 outreg @0+4,r27 outreg @0+5,r28 outreg @0+6,r29 outreg @0+7,r30 .elif r24_mpr outreg @0,r24 outreg @0+1,r25 outreg @0+2,r26 outreg @0+3,r27 outreg @0+4,r28 outreg @0+5,r29 outreg @0+6,r30 outreg @0+7,r31 .else .error "Macro outreg64 reg zu gross" .endif .endm ;========================================================================= ;=== Rotieren ============================================================ ;========================================================================= .macro rol16 ; @0 r0-r30 2c, 4b setr .set @0_mpr = 1 .if r0_mpr rol r0 rol r1 .elif r1_mpr rol r1 rol r2 .elif r2_mpr rol r2 rol r3 .elif r3_mpr rol r3 rol r4 .elif r4_mpr rol r4 rol r5 .elif r5_mpr rol r5 rol r6 .elif r6_mpr rol r6 rol r7 .elif r7_mpr rol r7 rol r8 .elif r8_mpr rol r8 rol r9 .elif r9_mpr rol r9 rol r10 .elif r10_mpr rol r10 rol r11 .elif r11_mpr rol r11 rol r12 .elif r12_mpr rol r12 rol r13 .elif r13_mpr rol r13 rol r14 .elif r14_mpr rol r14 rol r15 .elif r15_mpr rol r15 rol r16 .elif r16_mpr rol r16 rol r17 .elif r17_mpr rol r17 rol r18 .elif r18_mpr rol r18 rol r19 .elif r19_mpr rol r19 rol r20 .elif r20_mpr rol r20 rol r21 .elif r21_mpr rol r21 rol r22 .elif r22_mpr rol r22 rol r23 .elif r23_mpr rol r23 rol r24 .elif r24_mpr || temp_mpr || templ_mpr rol r24 rol r25 .elif r25_mpr || temph_mpr rol r25 rol r26 .elif r26_mpr || xl_mpr || X_mpr rol r26 rol r27 .elif r27_mpr || xh_mpr rol r27 rol r28 .elif r28_mpr || yl_mpr || Y_mpr rol r28 rol r29 .elif r29_mpr || yh_mpr rol r29 rol r30 .elif r30_mpr || zl_mpr || Z_mpr rol r30 rol r31 .else .error "Macro rol16 reg zu gross" .endif .endm .macro rol24 ; @0 r0-r29 3c, 6b setr .set @0_mpr = 1 .if r0_mpr rol r0 rol r1 rol r2 .elif r1_mpr rol r1 rol r2 rol r3 .elif r2_mpr rol r2 rol r3 rol r4 .elif r3_mpr rol r3 rol r4 rol r5 .elif r4_mpr rol r4 rol r5 rol r6 .elif r5_mpr rol r5 rol r6 rol r7 .elif r6_mpr rol r6 rol r7 rol r8 .elif r7_mpr rol r7 rol r8 rol r9 .elif r8_mpr rol r8 rol r9 rol r10 .elif r9_mpr rol r9 rol r10 rol r11 .elif r10_mpr rol r10 rol r11 rol r12 .elif r11_mpr rol r11 rol r12 rol r13 .elif r12_mpr rol r12 rol r13 rol r14 .elif r13_mpr rol r13 rol r14 rol r15 .elif r14_mpr rol r14 rol r15 rol r16 .elif r15_mpr rol r15 rol r16 rol r17 .elif r16_mpr rol r16 rol r17 rol r18 .elif r17_mpr rol r17 rol r18 rol r19 .elif r18_mpr rol r18 rol r19 rol r20 .elif r19_mpr rol r19 rol r20 rol r21 .elif r20_mpr rol r20 rol r21 rol r22 .elif r21_mpr rol r21 rol r22 rol r23 .elif r22_mpr rol r22 rol r23 rol r24 .elif r23_mpr rol r23 rol r24 rol r25 .elif r24_mpr rol r24 rol r25 rol r26 .elif r25_mpr rol r25 rol r26 rol r27 .elif r26_mpr rol r26 rol r27 rol r28 .elif r27_mpr rol r27 rol r28 rol r29 .elif r28_mpr rol r28 rol r29 rol r30 .elif r29_mpr rol r29 rol r30 rol r31 .else .error "Macro rol24 reg zu gross" .endif .endm .macro rol32 ; @0 r0-r28 4c, 8b setr .set @0_mpr = 1 .if r0_mpr rol r0 rol r1 rol r2 rol r3 .elif r1_mpr rol r1 rol r2 rol r3 rol r4 .elif r2_mpr rol r2 rol r3 rol r4 rol r5 .elif r3_mpr rol r3 rol r4 rol r5 rol r6 .elif r4_mpr rol r4 rol r5 rol r6 rol r7 .elif r5_mpr rol r5 rol r6 rol r7 rol r8 .elif r6_mpr rol r6 rol r7 rol r8 rol r9 .elif r7_mpr rol r7 rol r8 rol r9 rol r10 .elif r8_mpr rol r8 rol r9 rol r10 rol r11 .elif r9_mpr rol r9 rol r10 rol r11 rol r12 .elif r10_mpr rol r10 rol r11 rol r12 rol r13 .elif r11_mpr rol r11 rol r12 rol r13 rol r14 .elif r12_mpr rol r12 rol r13 rol r14 rol r15 .elif r13_mpr rol r13 rol r14 rol r15 rol r16 .elif r14_mpr rol r14 rol r15 rol r16 rol r17 .elif r15_mpr rol r15 rol r16 rol r17 rol r18 .elif r16_mpr rol r16 rol r17 rol r18 rol r19 .elif r17_mpr rol r17 rol r18 rol r19 rol r20 .elif r18_mpr rol r18 rol r19 rol r20 rol r21 .elif r19_mpr rol r19 rol r20 rol r21 rol r22 .elif r20_mpr rol r20 rol r21 rol r22 rol r23 .elif r21_mpr rol r21 rol r22 rol r23 rol r24 .elif r22_mpr rol r22 rol r23 rol r24 rol r25 .elif r23_mpr rol r23 rol r24 rol r25 rol r26 .elif r24_mpr rol r24 rol r25 rol r26 rol r27 .elif r25_mpr rol r25 rol r26 rol r27 rol r28 .elif r26_mpr rol r26 rol r27 rol r28 rol r29 .elif r27_mpr rol r27 rol r28 rol r29 rol r30 .elif r28_mpr rol r28 rol r29 rol r30 rol r31 .else .error "Macro rol32 reg zu gross" .endif .endm .macro rol40 ; @0 r0-r27 5c, 10b setr .set @0_mpr = 1 .if r0_mpr rol r0 rol r1 rol r2 rol r3 rol r4 .elif r1_mpr rol r1 rol r2 rol r3 rol r4 rol r5 .elif r2_mpr rol r2 rol r3 rol r4 rol r5 rol r6 .elif r3_mpr rol r3 rol r4 rol r5 rol r6 rol r7 .elif r4_mpr rol r4 rol r5 rol r6 rol r7 rol r8 .elif r5_mpr rol r5 rol r6 rol r7 rol r8 rol r9 .elif r6_mpr rol r6 rol r7 rol r8 rol r9 rol r10 .elif r7_mpr rol r7 rol r8 rol r9 rol r10 rol r11 .elif r8_mpr rol r8 rol r9 rol r10 rol r11 rol r12 .elif r9_mpr rol r9 rol r10 rol r11 rol r12 rol r13 .elif r10_mpr rol r10 rol r11 rol r12 rol r13 rol r14 .elif r11_mpr rol r11 rol r12 rol r13 rol r14 rol r15 .elif r12_mpr rol r12 rol r13 rol r14 rol r15 rol r16 .elif r13_mpr rol r13 rol r14 rol r15 rol r16 rol r17 .elif r14_mpr rol r14 rol r15 rol r16 rol r17 rol r18 .elif r15_mpr rol r15 rol r16 rol r17 rol r18 rol r19 .elif r16_mpr rol r16 rol r17 rol r18 rol r19 rol r20 .elif r17_mpr rol r17 rol r18 rol r19 rol r20 rol r21 .elif r18_mpr rol r18 rol r19 rol r20 rol r21 rol r22 .elif r19_mpr rol r19 rol r20 rol r21 rol r22 rol r23 .elif r20_mpr rol r20 rol r21 rol r22 rol r23 rol r24 .elif r21_mpr rol r21 rol r22 rol r23 rol r24 rol r25 .elif r22_mpr rol r22 rol r23 rol r24 rol r25 rol r26 .elif r23_mpr rol r23 rol r24 rol r25 rol r26 rol r27 .elif r24_mpr rol r24 rol r25 rol r26 rol r27 rol r28 .elif r25_mpr rol r25 rol r26 rol r27 rol r28 rol r29 .elif r26_mpr rol r26 rol r27 rol r28 rol r29 rol r30 .elif r27_mpr rol r27 rol r28 rol r29 rol r30 rol r31 .else .error "Macro rol40 reg zu gross" .endif .endm .macro rol48 ; @0 r0-r26 6c, 12b setr .set @0_mpr = 1 .if r0_mpr rol r0 rol r1 rol r2 rol r3 rol r4 rol r5 .elif r1_mpr rol r1 rol r2 rol r3 rol r4 rol r5 rol r6 .elif r2_mpr rol r2 rol r3 rol r4 rol r5 rol r6 rol r7 .elif r3_mpr rol r3 rol r4 rol r5 rol r6 rol r7 rol r8 .elif r4_mpr rol r4 rol r5 rol r6 rol r7 rol r8 rol r9 .elif r5_mpr rol r5 rol r6 rol r7 rol r8 rol r9 rol r10 .elif r6_mpr rol r6 rol r7 rol r8 rol r9 rol r10 rol r11 .elif r7_mpr rol r7 rol r8 rol r9 rol r10 rol r11 rol r12 .elif r8_mpr rol r8 rol r9 rol r10 rol r11 rol r12 rol r13 .elif r9_mpr rol r9 rol r10 rol r11 rol r12 rol r13 rol r14 .elif r10_mpr rol r10 rol r11 rol r12 rol r13 rol r14 rol r15 .elif r11_mpr rol r11 rol r12 rol r13 rol r14 rol r15 rol r16 .elif r12_mpr rol r12 rol r13 rol r14 rol r15 rol r16 rol r17 .elif r13_mpr rol r13 rol r14 rol r15 rol r16 rol r17 rol r18 .elif r14_mpr rol r14 rol r15 rol r16 rol r17 rol r18 rol r19 .elif r15_mpr rol r15 rol r16 rol r17 rol r18 rol r19 rol r20 .elif r16_mpr rol r16 rol r17 rol r18 rol r19 rol r20 rol r21 .elif r17_mpr rol r17 rol r18 rol r19 rol r20 rol r21 rol r22 .elif r18_mpr rol r18 rol r19 rol r20 rol r21 rol r22 rol r23 .elif r19_mpr rol r19 rol r20 rol r21 rol r22 rol r23 rol r24 .elif r20_mpr rol r20 rol r21 rol r22 rol r23 rol r24 rol r25 .elif r21_mpr rol r21 rol r22 rol r23 rol r24 rol r25 rol r26 .elif r22_mpr rol r22 rol r23 rol r24 rol r25 rol r26 rol r27 .elif r23_mpr rol r23 rol r24 rol r25 rol r26 rol r27 rol r28 .elif r24_mpr rol r24 rol r25 rol r26 rol r27 rol r28 rol r29 .elif r25_mpr rol r25 rol r26 rol r27 rol r28 rol r29 rol r30 .elif r26_mpr rol r26 rol r27 rol r28 rol r29 rol r30 rol r31 .else .error "Macro rol48 reg zu gross" .endif .endm .macro rol56 ; @0 r0-r25 7c, 14b setr .set @0_mpr = 1 .if r0_mpr rol r0 rol r1 rol r2 rol r3 rol r4 rol r5 rol r6 .elif r1_mpr rol r1 rol r2 rol r3 rol r4 rol r5 rol r6 rol r7 .elif r2_mpr rol r2 rol r3 rol r4 rol r5 rol r6 rol r7 rol r8 .elif r3_mpr rol r3 rol r4 rol r5 rol r6 rol r7 rol r8 rol r9 .elif r4_mpr rol r4 rol r5 rol r6 rol r7 rol r8 rol r9 rol r10 .elif r5_mpr rol r5 rol r6 rol r7 rol r8 rol r9 rol r10 rol r11 .elif r6_mpr rol r6 rol r7 rol r8 rol r9 rol r10 rol r11 rol r12 .elif r7_mpr rol r7 rol r8 rol r9 rol r10 rol r11 rol r12 rol r13 .elif r8_mpr rol r8 rol r9 rol r10 rol r11 rol r12 rol r13 rol r14 .elif r9_mpr rol r9 rol r10 rol r11 rol r12 rol r13 rol r14 rol r15 .elif r10_mpr rol r10 rol r11 rol r12 rol r13 rol r14 rol r15 rol r16 .elif r11_mpr rol r11 rol r12 rol r13 rol r14 rol r15 rol r16 rol r17 .elif r12_mpr rol r12 rol r13 rol r14 rol r15 rol r16 rol r17 rol r18 .elif r13_mpr rol r13 rol r14 rol r15 rol r16 rol r17 rol r18 rol r19 .elif r14_mpr rol r14 rol r15 rol r16 rol r17 rol r18 rol r19 rol r20 .elif r15_mpr rol r15 rol r16 rol r17 rol r18 rol r19 rol r20 rol r21 .elif r16_mpr rol r16 rol r17 rol r18 rol r19 rol r20 rol r21 rol r22 .elif r17_mpr rol r17 rol r18 rol r19 rol r20 rol r21 rol r22 rol r23 .elif r18_mpr rol r18 rol r19 rol r20 rol r21 rol r22 rol r23 rol r24 .elif r19_mpr rol r19 rol r20 rol r21 rol r22 rol r23 rol r24 rol r25 .elif r20_mpr rol r20 rol r21 rol r22 rol r23 rol r24 rol r25 rol r26 .elif r21_mpr rol r21 rol r22 rol r23 rol r24 rol r25 rol r26 rol r27 .elif r22_mpr rol r22 rol r23 rol r24 rol r25 rol r26 rol r27 rol r28 .elif r23_mpr rol r23 rol r24 rol r25 rol r26 rol r27 rol r28 rol r29 .elif r24_mpr rol r24 rol r25 rol r26 rol r27 rol r28 rol r29 rol r30 .elif r25_mpr rol r25 rol r26 rol r27 rol r28 rol r29 rol r30 rol r31 .else .error "Macro rol56 reg zu gross" .endif .endm .macro rol64 ; @0 r0-r24 8c, 16b setr .set @0_mpr = 1 .if r0_mpr rol r0 rol r1 rol r2 rol r3 rol r4 rol r5 rol r6 rol r7 .elif r1_mpr rol r1 rol r2 rol r3 rol r4 rol r5 rol r6 rol r7 rol r8 .elif r2_mpr rol r2 rol r3 rol r4 rol r5 rol r6 rol r7 rol r8 rol r9 .elif r3_mpr rol r3 rol r4 rol r5 rol r6 rol r7 rol r8 rol r9 rol r10 .elif r4_mpr rol r4 rol r5 rol r6 rol r7 rol r8 rol r9 rol r10 rol r11 .elif r5_mpr rol r5 rol r6 rol r7 rol r8 rol r9 rol r10 rol r11 rol r12 .elif r6_mpr rol r6 rol r7 rol r8 rol r9 rol r10 rol r11 rol r12 rol r13 .elif r7_mpr rol r7 rol r8 rol r9 rol r10 rol r11 rol r12 rol r13 rol r14 .elif r8_mpr rol r8 rol r9 rol r10 rol r11 rol r12 rol r13 rol r14 rol r15 .elif r9_mpr rol r9 rol r10 rol r11 rol r12 rol r13 rol r14 rol r15 rol r16 .elif r10_mpr rol r10 rol r11 rol r12 rol r13 rol r14 rol r15 rol r16 rol r17 .elif r11_mpr rol r11 rol r12 rol r13 rol r14 rol r15 rol r16 rol r17 rol r18 .elif r12_mpr rol r12 rol r13 rol r14 rol r15 rol r16 rol r17 rol r18 rol r19 .elif r13_mpr rol r13 rol r14 rol r15 rol r16 rol r17 rol r18 rol r19 rol r20 .elif r14_mpr rol r14 rol r15 rol r16 rol r17 rol r18 rol r19 rol r20 rol r21 .elif r15_mpr rol r15 rol r16 rol r17 rol r18 rol r19 rol r20 rol r21 rol r22 .elif r16_mpr rol r16 rol r17 rol r18 rol r19 rol r20 rol r21 rol r22 rol r23 .elif r17_mpr rol r17 rol r18 rol r19 rol r20 rol r21 rol r22 rol r23 rol r24 .elif r18_mpr rol r18 rol r19 rol r20 rol r21 rol r22 rol r23 rol r24 rol r25 .elif r19_mpr rol r19 rol r20 rol r21 rol r22 rol r23 rol r24 rol r25 rol r26 .elif r20_mpr rol r20 rol r21 rol r22 rol r23 rol r24 rol r25 rol r26 rol r27 .elif r21_mpr rol r21 rol r22 rol r23 rol r24 rol r25 rol r26 rol r27 rol r28 .elif r22_mpr rol r22 rol r23 rol r24 rol r25 rol r26 rol r27 rol r28 rol r29 .elif r23_mpr rol r23 rol r24 rol r25 rol r26 rol r27 rol r28 rol r29 rol r30 .elif r24_mpr rol r24 rol r25 rol r26 rol r27 rol r28 rol r29 rol r30 rol r31 .else .error "Macro rol64 reg zu gross" .endif .endm .macro ror16 ; @0 r0-r30 2c, 4b setr .set @0_mpr = 1 .if r0_mpr ror r1 ror r0 .elif r1_mpr ror r2 ror r1 .elif r2_mpr ror r3 ror r2 .elif r3_mpr ror r4 ror r3 .elif r4_mpr ror r5 ror r4 .elif r5_mpr ror r6 ror r5 .elif r6_mpr ror r7 ror r6 .elif r7_mpr ror r8 ror r7 .elif r8_mpr ror r9 ror r8 .elif r9_mpr ror r10 ror r9 .elif r10_mpr ror r11 ror r10 .elif r11_mpr ror r12 ror r11 .elif r12_mpr ror r13 ror r12 .elif r13_mpr ror r14 ror r13 .elif r14_mpr ror r15 ror r14 .elif r15_mpr ror r16 ror r15 .elif r16_mpr ror r17 ror r16 .elif r17_mpr ror r18 ror r17 .elif r18_mpr ror r19 ror r18 .elif r19_mpr ror r20 ror r19 .elif r20_mpr ror r21 ror r20 .elif r21_mpr ror r22 ror r21 .elif r22_mpr ror r23 ror r22 .elif r23_mpr ror r24 ror r23 .elif r24_mpr || temp_mpr || templ_mpr ror r25 ror r24 .elif r25_mpr || temph_mpr ror r26 ror r25 .elif r26_mpr || xl_mpr || X_mpr ror r27 ror r26 .elif r27_mpr || xh_mpr ror r28 ror r27 .elif r28_mpr || yl_mpr || Y_mpr ror r29 ror r28 .elif r29_mpr || yh_mpr ror r30 ror r29 .elif r30_mpr || zl_mpr || Z_mpr ror r31 ror r30 .else .error "Macro ror16 reg zu gross" .endif .endm .macro ror24 ; @0 r0-r29 3c, 6b setr .set @0_mpr = 1 .if r0_mpr ror r2 ror r1 ror r0 .elif r1_mpr ror r3 ror r2 ror r1 .elif r2_mpr ror r4 ror r3 ror r2 .elif r3_mpr ror r5 ror r4 ror r3 .elif r4_mpr ror r6 ror r5 ror r4 .elif r5_mpr ror r7 ror r6 ror r5 .elif r6_mpr ror r8 ror r7 ror r6 .elif r7_mpr ror r9 ror r8 ror r7 .elif r8_mpr ror r10 ror r9 ror r8 .elif r9_mpr ror r11 ror r10 ror r9 .elif r10_mpr ror r12 ror r11 ror r10 .elif r11_mpr ror r13 ror r12 ror r11 .elif r12_mpr ror r14 ror r13 ror r12 .elif r13_mpr ror r15 ror r14 ror r13 .elif r14_mpr ror r16 ror r15 ror r14 .elif r15_mpr ror r17 ror r16 ror r15 .elif r16_mpr ror r18 ror r17 ror r16 .elif r17_mpr ror r19 ror r18 ror r17 .elif r18_mpr ror r20 ror r19 ror r18 .elif r19_mpr ror r21 ror r20 ror r19 .elif r20_mpr ror r22 ror r21 ror r20 .elif r21_mpr ror r23 ror r22 ror r21 .elif r22_mpr ror r24 ror r23 ror r22 .elif r23_mpr ror r25 ror r24 ror r23 .elif r24_mpr ror r26 ror r25 ror r24 .elif r25_mpr ror r27 ror r26 ror r25 .elif r26_mpr ror r28 ror r27 ror r26 .elif r27_mpr ror r29 ror r28 ror r27 .elif r28_mpr ror r30 ror r29 ror r28 .elif r29_mpr ror r31 ror r30 ror r29 .else .error "Macro ror24 reg zu gross" .endif .endm .macro ror32 ; @0 r0-r28 4c, 8b setr .set @0_mpr = 1 .if r0_mpr ror r3 ror r2 ror r1 ror r0 .elif r1_mpr ror r4 ror r3 ror r2 ror r1 .elif r2_mpr ror r5 ror r4 ror r3 ror r2 .elif r3_mpr ror r6 ror r5 ror r4 ror r3 .elif r4_mpr ror r7 ror r6 ror r5 ror r4 .elif r5_mpr ror r8 ror r7 ror r6 ror r5 .elif r6_mpr ror r9 ror r8 ror r7 ror r6 .elif r7_mpr ror r10 ror r9 ror r8 ror r7 .elif r8_mpr ror r11 ror r10 ror r9 ror r8 .elif r9_mpr ror r12 ror r11 ror r10 ror r9 .elif r10_mpr ror r13 ror r12 ror r11 ror r10 .elif r11_mpr ror r14 ror r13 ror r12 ror r11 .elif r12_mpr ror r15 ror r14 ror r13 ror r12 .elif r13_mpr ror r16 ror r15 ror r14 ror r13 .elif r14_mpr ror r17 ror r16 ror r15 ror r14 .elif r15_mpr ror r18 ror r17 ror r16 ror r15 .elif r16_mpr ror r19 ror r18 ror r17 ror r16 .elif r17_mpr ror r20 ror r19 ror r18 ror r17 .elif r18_mpr ror r21 ror r20 ror r19 ror r18 .elif r19_mpr ror r22 ror r21 ror r20 ror r19 .elif r20_mpr ror r23 ror r22 ror r21 ror r20 .elif r21_mpr ror r24 ror r23 ror r22 ror r21 .elif r22_mpr ror r25 ror r24 ror r23 ror r22 .elif r23_mpr ror r26 ror r25 ror r24 ror r23 .elif r24_mpr ror r27 ror r26 ror r25 ror r24 .elif r25_mpr ror r28 ror r27 ror r26 ror r25 .elif r26_mpr ror r29 ror r28 ror r27 ror r26 .elif r27_mpr ror r30 ror r29 ror r28 ror r27 .elif r28_mpr ror r31 ror r30 ror r29 ror r28 .else .error "Macro ror32 reg zu gross" .endif .endm .macro ror40 ; @0 r0-r27 5c, 10b setr .set @0_mpr = 1 .if r0_mpr ror r4 ror r3 ror r2 ror r1 ror r0 .elif r1_mpr ror r5 ror r4 ror r3 ror r2 ror r1 .elif r2_mpr ror r6 ror r5 ror r4 ror r3 ror r2 .elif r3_mpr ror r7 ror r6 ror r5 ror r4 ror r3 .elif r4_mpr ror r8 ror r7 ror r6 ror r5 ror r4 .elif r5_mpr ror r9 ror r8 ror r7 ror r6 ror r5 .elif r6_mpr ror r10 ror r9 ror r8 ror r7 ror r6 .elif r7_mpr ror r11 ror r10 ror r9 ror r8 ror r7 .elif r8_mpr ror r12 ror r11 ror r10 ror r9 ror r8 .elif r9_mpr ror r13 ror r12 ror r11 ror r10 ror r9 .elif r10_mpr ror r14 ror r13 ror r12 ror r11 ror r10 .elif r11_mpr ror r15 ror r14 ror r13 ror r12 ror r11 .elif r12_mpr ror r16 ror r15 ror r14 ror r13 ror r12 .elif r13_mpr ror r17 ror r16 ror r15 ror r14 ror r13 .elif r14_mpr ror r18 ror r17 ror r16 ror r15 ror r14 .elif r15_mpr ror r19 ror r18 ror r17 ror r16 ror r15 .elif r16_mpr ror r20 ror r19 ror r18 ror r17 ror r16 .elif r17_mpr ror r21 ror r20 ror r19 ror r18 ror r17 .elif r18_mpr ror r22 ror r21 ror r20 ror r19 ror r18 .elif r19_mpr ror r23 ror r22 ror r21 ror r20 ror r19 .elif r20_mpr ror r24 ror r23 ror r22 ror r21 ror r20 .elif r21_mpr ror r25 ror r24 ror r23 ror r22 ror r21 .elif r22_mpr ror r26 ror r25 ror r24 ror r23 ror r22 .elif r23_mpr ror r27 ror r26 ror r25 ror r24 ror r23 .elif r24_mpr ror r28 ror r27 ror r26 ror r25 ror r24 .elif r25_mpr ror r29 ror r28 ror r27 ror r26 ror r25 .elif r26_mpr ror r30 ror r29 ror r28 ror r27 ror r26 .elif r27_mpr ror r31 ror r30 ror r29 ror r28 ror r27 .else .error "Macro ror40 reg zu gross" .endif .endm .macro ror48 ; @0 r0-r26 6c, 12b setr .set @0_mpr = 1 .if r0_mpr ror r5 ror r4 ror r3 ror r2 ror r1 ror r0 .elif r1_mpr ror r6 ror r5 ror r4 ror r3 ror r2 ror r1 .elif r2_mpr ror r7 ror r6 ror r5 ror r4 ror r3 ror r2 .elif r3_mpr ror r8 ror r7 ror r6 ror r5 ror r4 ror r3 .elif r4_mpr ror r9 ror r8 ror r7 ror r6 ror r5 ror r4 .elif r5_mpr ror r10 ror r9 ror r8 ror r7 ror r6 ror r5 .elif r6_mpr ror r11 ror r10 ror r9 ror r8 ror r7 ror r6 .elif r7_mpr ror r12 ror r11 ror r10 ror r9 ror r8 ror r7 .elif r8_mpr ror r13 ror r12 ror r11 ror r10 ror r9 ror r8 .elif r9_mpr ror r14 ror r13 ror r12 ror r11 ror r10 ror r9 .elif r10_mpr ror r15 ror r14 ror r13 ror r12 ror r11 ror r10 .elif r11_mpr ror r16 ror r15 ror r14 ror r13 ror r12 ror r11 .elif r12_mpr ror r17 ror r16 ror r15 ror r14 ror r13 ror r12 .elif r13_mpr ror r18 ror r17 ror r16 ror r15 ror r14 ror r13 .elif r14_mpr ror r19 ror r18 ror r17 ror r16 ror r15 ror r14 .elif r15_mpr ror r20 ror r19 ror r18 ror r17 ror r16 ror r15 .elif r16_mpr ror r21 ror r20 ror r19 ror r18 ror r17 ror r16 .elif r17_mpr ror r22 ror r21 ror r20 ror r19 ror r18 ror r17 .elif r18_mpr ror r23 ror r22 ror r21 ror r20 ror r19 ror r18 .elif r19_mpr ror r24 ror r23 ror r22 ror r21 ror r20 ror r19 .elif r20_mpr ror r25 ror r24 ror r23 ror r22 ror r21 ror r20 .elif r21_mpr ror r26 ror r25 ror r24 ror r23 ror r22 ror r21 .elif r22_mpr ror r27 ror r26 ror r25 ror r24 ror r23 ror r22 .elif r23_mpr ror r28 ror r27 ror r26 ror r25 ror r24 ror r23 .elif r24_mpr ror r29 ror r28 ror r27 ror r26 ror r25 ror r24 .elif r25_mpr ror r30 ror r29 ror r28 ror r27 ror r26 ror r25 .elif r26_mpr ror r31 ror r30 ror r29 ror r28 ror r27 ror r26 .else .error "Macro ror48 reg zu gross" .endif .endm .macro ror56 ; @0 r0-r25 7c, 14b setr .set @0_mpr = 1 .if r0_mpr ror r6 ror r5 ror r4 ror r3 ror r2 ror r1 ror r0 .elif r1_mpr ror r7 ror r6 ror r5 ror r4 ror r3 ror r2 ror r1 .elif r2_mpr ror r8 ror r7 ror r6 ror r5 ror r4 ror r3 ror r2 .elif r3_mpr ror r9 ror r8 ror r7 ror r6 ror r5 ror r4 ror r3 .elif r4_mpr ror r10 ror r9 ror r8 ror r7 ror r6 ror r5 ror r4 .elif r5_mpr ror r11 ror r10 ror r9 ror r8 ror r7 ror r6 ror r5 .elif r6_mpr ror r12 ror r11 ror r10 ror r9 ror r8 ror r7 ror r6 .elif r7_mpr ror r13 ror r12 ror r11 ror r10 ror r9 ror r8 ror r7 .elif r8_mpr ror r14 ror r13 ror r12 ror r11 ror r10 ror r9 ror r8 .elif r9_mpr ror r15 ror r14 ror r13 ror r12 ror r11 ror r10 ror r9 .elif r10_mpr ror r16 ror r15 ror r14 ror r13 ror r12 ror r11 ror r10 .elif r11_mpr ror r17 ror r16 ror r15 ror r14 ror r13 ror r12 ror r11 .elif r12_mpr ror r18 ror r17 ror r16 ror r15 ror r14 ror r13 ror r12 .elif r13_mpr ror r19 ror r18 ror r17 ror r16 ror r15 ror r14 ror r13 .elif r14_mpr ror r20 ror r19 ror r18 ror r17 ror r16 ror r15 ror r14 .elif r15_mpr ror r21 ror r20 ror r19 ror r18 ror r17 ror r16 ror r15 .elif r16_mpr ror r22 ror r21 ror r20 ror r19 ror r18 ror r17 ror r16 .elif r17_mpr ror r23 ror r22 ror r21 ror r20 ror r19 ror r18 ror r17 .elif r18_mpr ror r24 ror r23 ror r22 ror r21 ror r20 ror r19 ror r18 .elif r19_mpr ror r25 ror r24 ror r23 ror r22 ror r21 ror r20 ror r19 .elif r20_mpr ror r26 ror r25 ror r24 ror r23 ror r22 ror r21 ror r20 .elif r21_mpr ror r27 ror r26 ror r25 ror r24 ror r23 ror r22 ror r21 .elif r22_mpr ror r28 ror r27 ror r26 ror r25 ror r24 ror r23 ror r22 .elif r23_mpr ror r29 ror r28 ror r27 ror r26 ror r25 ror r24 ror r23 .elif r24_mpr ror r30 ror r29 ror r28 ror r27 ror r26 ror r25 ror r24 .elif r25_mpr ror r31 ror r30 ror r29 ror r28 ror r27 ror r26 ror r25 .else .error "Macro ror56 reg zu gross" .endif .endm .macro ror64 ; @0 r0-r24 8c, 16b setr .set @0_mpr = 1 .if r0_mpr ror r7 ror r6 ror r5 ror r4 ror r3 ror r2 ror r1 ror r0 .elif r1_mpr ror r8 ror r7 ror r6 ror r5 ror r4 ror r3 ror r2 ror r1 .elif r2_mpr ror r9 ror r8 ror r7 ror r6 ror r5 ror r4 ror r3 ror r2 .elif r3_mpr ror r10 ror r9 ror r8 ror r7 ror r6 ror r5 ror r4 ror r3 .elif r4_mpr ror r11 ror r10 ror r9 ror r8 ror r7 ror r6 ror r5 ror r4 .elif r5_mpr ror r12 ror r11 ror r10 ror r9 ror r8 ror r7 ror r6 ror r5 .elif r6_mpr ror r13 ror r12 ror r11 ror r10 ror r9 ror r8 ror r7 ror r6 .elif r7_mpr ror r14 ror r13 ror r12 ror r11 ror r10 ror r9 ror r8 ror r7 .elif r8_mpr ror r15 ror r14 ror r13 ror r12 ror r11 ror r10 ror r9 ror r8 .elif r9_mpr ror r16 ror r15 ror r14 ror r13 ror r12 ror r11 ror r10 ror r9 .elif r10_mpr ror r17 ror r16 ror r15 ror r14 ror r13 ror r12 ror r11 ror r10 .elif r11_mpr ror r18 ror r17 ror r16 ror r15 ror r14 ror r13 ror r12 ror r11 .elif r12_mpr ror r19 ror r18 ror r17 ror r16 ror r15 ror r14 ror r13 ror r12 .elif r13_mpr ror r20 ror r19 ror r18 ror r17 ror r16 ror r15 ror r14 ror r13 .elif r14_mpr ror r21 ror r20 ror r19 ror r18 ror r17 ror r16 ror r15 ror r14 .elif r15_mpr ror r22 ror r21 ror r20 ror r19 ror r18 ror r17 ror r16 ror r15 .elif r16_mpr ror r23 ror r22 ror r21 ror r20 ror r19 ror r18 ror r17 ror r16 .elif r17_mpr ror r24 ror r23 ror r22 ror r21 ror r20 ror r19 ror r18 ror r17 .elif r18_mpr ror r25 ror r24 ror r23 ror r22 ror r21 ror r20 ror r19 ror r18 .elif r19_mpr ror r26 ror r25 ror r24 ror r23 ror r22 ror r21 ror r20 ror r19 .elif r20_mpr ror r27 ror r26 ror r25 ror r24 ror r23 ror r22 ror r21 ror r20 .elif r21_mpr ror r28 ror r27 ror r26 ror r25 ror r24 ror r23 ror r22 ror r21 .elif r22_mpr ror r29 ror r28 ror r27 ror r26 ror r25 ror r24 ror r23 ror r22 .elif r23_mpr ror r30 ror r29 ror r28 ror r27 ror r26 ror r25 ror r24 ror r23 .elif r24_mpr ror r31 ror r30 ror r29 ror r28 ror r27 ror r26 ror r25 ror r24 .else .error "Macro ror64 reg zu gross" .endif .endm .macro lsl16 ; @0 r0-r30 2c, 4b setr .set @0_mpr = 1 .if r0_mpr lsl r0 rol r1 .elif r1_mpr lsl r1 rol r2 .elif r2_mpr lsl r2 rol r3 .elif r3_mpr lsl r3 rol r4 .elif r4_mpr lsl r4 rol r5 .elif r5_mpr lsl r5 rol r6 .elif r6_mpr lsl r6 rol r7 .elif r7_mpr lsl r7 rol r8 .elif r8_mpr lsl r8 rol r9 .elif r9_mpr lsl r9 rol r10 .elif r10_mpr lsl r10 rol r11 .elif r11_mpr lsl r11 rol r12 .elif r12_mpr lsl r12 rol r13 .elif r13_mpr lsl r13 rol r14 .elif r14_mpr lsl r14 rol r15 .elif r15_mpr lsl r15 rol r16 .elif r16_mpr lsl r16 rol r17 .elif r17_mpr lsl r17 rol r18 .elif r18_mpr lsl r18 rol r19 .elif r19_mpr lsl r19 rol r20 .elif r20_mpr lsl r20 rol r21 .elif r21_mpr lsl r21 rol r22 .elif r22_mpr lsl r22 rol r23 .elif r23_mpr lsl r23 rol r24 .elif r24_mpr || temp_mpr || templ_mpr lsl r24 rol r25 .elif r25_mpr || temph_mpr lsl r25 rol r26 .elif r26_mpr || xl_mpr || X_mpr lsl r26 rol r27 .elif r27_mpr || xh_mpr lsl r27 rol r28 .elif r28_mpr || yl_mpr || Y_mpr lsl r28 rol r29 .elif r29_mpr || yh_mpr lsl r29 rol r30 .elif r30_mpr || zl_mpr || Z_mpr lsl r30 rol r31 .else .error "Macro lsl16 reg zu gross" .endif .endm .macro lsl24 ; @0 r0-r29 3c, 6b setr .set @0_mpr = 1 .if r0_mpr lsl r0 rol16 r1 .elif r1_mpr lsl r1 rol16 r2 .elif r2_mpr lsl r2 rol16 r3 .elif r3_mpr lsl r3 rol16 r4 .elif r4_mpr lsl r4 rol16 r5 .elif r5_mpr lsl r5 rol16 r6 .elif r6_mpr lsl r6 rol16 r7 .elif r7_mpr lsl r7 rol16 r8 .elif r8_mpr lsl r8 rol16 r9 .elif r9_mpr lsl r9 rol16 r10 .elif r10_mpr lsl r10 rol16 r11 .elif r11_mpr lsl r11 rol16 r12 .elif r12_mpr lsl r12 rol16 r13 .elif r13_mpr lsl r13 rol16 r14 .elif r14_mpr lsl r14 rol16 r15 .elif r15_mpr lsl r15 rol16 r16 .elif r16_mpr lsl r16 rol16 r17 .elif r17_mpr lsl r17 rol16 r18 .elif r18_mpr lsl r18 rol16 r19 .elif r19_mpr lsl r19 rol16 r20 .elif r20_mpr lsl r20 rol16 r21 .elif r21_mpr lsl r21 rol16 r22 .elif r22_mpr lsl r22 rol16 r23 .elif r23_mpr lsl r23 rol16 r24 .elif r24_mpr lsl r24 rol16 r25 .elif r25_mpr lsl r25 rol16 r26 .elif r26_mpr lsl r26 rol16 r27 .elif r27_mpr lsl r27 rol16 r28 .elif r28_mpr lsl r28 rol16 r29 .elif r29_mpr lsl r29 rol16 r30 .else .error "Macro lsl24 reg zu gross" .endif .endm .macro lsl32 ; @0 r0-r28 4c, 8b setr .set @0_mpr = 1 .if r0_mpr lsl r0 rol24 r1 .elif r1_mpr lsl r1 rol24 r2 .elif r2_mpr lsl r2 rol24 r3 .elif r3_mpr lsl r3 rol24 r4 .elif r4_mpr lsl r4 rol24 r5 .elif r5_mpr lsl r5 rol24 r6 .elif r6_mpr lsl r6 rol24 r7 .elif r7_mpr lsl r7 rol24 r8 .elif r8_mpr lsl r8 rol24 r9 .elif r9_mpr lsl r9 rol24 r10 .elif r10_mpr lsl r10 rol24 r11 .elif r11_mpr lsl r11 rol24 r12 .elif r12_mpr lsl r12 rol24 r13 .elif r13_mpr lsl r13 rol24 r14 .elif r14_mpr lsl r14 rol24 r15 .elif r15_mpr lsl r15 rol24 r16 .elif r16_mpr lsl r16 rol24 r17 .elif r17_mpr lsl r17 rol24 r18 .elif r18_mpr lsl r18 rol24 r19 .elif r19_mpr lsl r19 rol24 r20 .elif r20_mpr lsl r20 rol24 r21 .elif r21_mpr lsl r21 rol24 r22 .elif r22_mpr lsl r22 rol24 r23 .elif r23_mpr lsl r23 rol24 r24 .elif r24_mpr lsl r24 rol24 r25 .elif r25_mpr lsl r25 rol24 r26 .elif r26_mpr lsl r26 rol24 r27 .elif r27_mpr lsl r27 rol24 r28 .elif r28_mpr lsl r28 rol24 r29 .else .error "Macro lsl32 reg zu gross" .endif .endm .macro lsl40 ; @0 r0-r27 5c, 10b setr .set @0_mpr = 1 .if r0_mpr lsl r0 rol32 r1 .elif r1_mpr lsl r1 rol32 r2 .elif r2_mpr lsl r2 rol32 r3 .elif r3_mpr lsl r3 rol32 r4 .elif r4_mpr lsl r4 rol32 r5 .elif r5_mpr lsl r5 rol32 r6 .elif r6_mpr lsl r6 rol32 r7 .elif r7_mpr lsl r7 rol32 r8 .elif r8_mpr lsl r8 rol32 r9 .elif r9_mpr lsl r9 rol32 r10 .elif r10_mpr lsl r10 rol32 r11 .elif r11_mpr lsl r11 rol32 r12 .elif r12_mpr lsl r12 rol32 r13 .elif r13_mpr lsl r13 rol32 r14 .elif r14_mpr lsl r14 rol32 r15 .elif r15_mpr lsl r15 rol32 r16 .elif r16_mpr lsl r16 rol32 r17 .elif r17_mpr lsl r17 rol32 r18 .elif r18_mpr lsl r18 rol32 r19 .elif r19_mpr lsl r19 rol32 r20 .elif r20_mpr lsl r20 rol32 r21 .elif r21_mpr lsl r21 rol32 r22 .elif r22_mpr lsl r22 rol32 r23 .elif r23_mpr lsl r23 rol32 r24 .elif r24_mpr lsl r24 rol32 r25 .elif r25_mpr lsl r25 rol32 r26 .elif r26_mpr lsl r26 rol32 r27 .elif r27_mpr lsl r27 rol32 r28 .else .error "Macro lsl40 reg zu gross" .endif .endm .macro lsl48 ; @0 r0-r26 6c, 12b setr .set @0_mpr = 1 .if r0_mpr lsl r0 rol40 r1 .elif r1_mpr lsl r1 rol40 r2 .elif r2_mpr lsl r2 rol40 r3 .elif r3_mpr lsl r3 rol40 r4 .elif r4_mpr lsl r4 rol40 r5 .elif r5_mpr lsl r5 rol40 r6 .elif r6_mpr lsl r6 rol40 r7 .elif r7_mpr lsl r7 rol40 r8 .elif r8_mpr lsl r8 rol40 r9 .elif r9_mpr lsl r9 rol40 r10 .elif r10_mpr lsl r10 rol40 r11 .elif r11_mpr lsl r11 rol40 r12 .elif r12_mpr lsl r12 rol40 r13 .elif r13_mpr lsl r13 rol40 r14 .elif r14_mpr lsl r14 rol40 r15 .elif r15_mpr lsl r15 rol40 r16 .elif r16_mpr lsl r16 rol40 r17 .elif r17_mpr lsl r17 rol40 r18 .elif r18_mpr lsl r18 rol40 r19 .elif r19_mpr lsl r19 rol40 r20 .elif r20_mpr lsl r20 rol40 r21 .elif r21_mpr lsl r21 rol40 r22 .elif r22_mpr lsl r22 rol40 r23 .elif r23_mpr lsl r23 rol40 r24 .elif r24_mpr lsl r24 rol40 r25 .elif r25_mpr lsl r25 rol40 r26 .elif r26_mpr lsl r26 rol40 r27 .else .error "Macro lsl48 reg zu gross" .endif .endm .macro lsl56 ; @0 r0-r25 7c, 14b setr .set @0_mpr = 1 .if r0_mpr lsl r0 rol48 r1 .elif r1_mpr lsl r1 rol48 r2 .elif r2_mpr lsl r2 rol48 r3 .elif r3_mpr lsl r3 rol48 r4 .elif r4_mpr lsl r4 rol48 r5 .elif r5_mpr lsl r5 rol48 r6 .elif r6_mpr lsl r6 rol48 r7 .elif r7_mpr lsl r7 rol48 r8 .elif r8_mpr lsl r8 rol48 r9 .elif r9_mpr lsl r9 rol48 r10 .elif r10_mpr lsl r10 rol48 r11 .elif r11_mpr lsl r11 rol48 r12 .elif r12_mpr lsl r12 rol48 r13 .elif r13_mpr lsl r13 rol48 r14 .elif r14_mpr lsl r14 rol48 r15 .elif r15_mpr lsl r15 rol48 r16 .elif r16_mpr lsl r16 rol48 r17 .elif r17_mpr lsl r17 rol48 r18 .elif r18_mpr lsl r18 rol48 r19 .elif r19_mpr lsl r19 rol48 r20 .elif r20_mpr lsl r20 rol48 r21 .elif r21_mpr lsl r21 rol48 r22 .elif r22_mpr lsl r22 rol48 r23 .elif r23_mpr lsl r23 rol48 r24 .elif r24_mpr lsl r24 rol48 r25 .elif r25_mpr lsl r25 rol48 r26 .else .error "Macro lsl56reg zu gross" .endif .endm .macro lsl64 ; @0 r0-r24 8c, 16b setr .set @0_mpr = 1 .if r0_mpr lsl r0 rol56 r1 .elif r1_mpr lsl r1 rol56 r2 .elif r2_mpr lsl r2 rol56 r3 .elif r3_mpr lsl r3 rol56 r4 .elif r4_mpr lsl r4 rol56 r5 .elif r5_mpr lsl r5 rol56 r6 .elif r6_mpr lsl r6 rol56 r7 .elif r7_mpr lsl r7 rol56 r8 .elif r8_mpr lsl r8 rol56 r9 .elif r9_mpr lsl r9 rol56 r10 .elif r10_mpr lsl r10 rol56 r11 .elif r11_mpr lsl r11 rol56 r12 .elif r12_mpr lsl r12 rol56 r13 .elif r13_mpr lsl r13 rol56 r14 .elif r14_mpr lsl r14 rol56 r15 .elif r15_mpr lsl r15 rol56 r16 .elif r16_mpr lsl r16 rol56 r17 .elif r17_mpr lsl r17 rol56 r18 .elif r18_mpr lsl r18 rol56 r19 .elif r19_mpr lsl r19 rol56 r20 .elif r20_mpr lsl r20 rol56 r21 .elif r21_mpr lsl r21 rol56 r22 .elif r22_mpr lsl r22 rol56 r23 .elif r23_mpr lsl r23 rol56 r24 .elif r24_mpr lsl r24 rol56 r25 .else .error "Macro lsl64reg zu gross" .endif .endm .macro lsr16 ; @0 r0-r30 2c, 4b setr .set @0_mpr = 1 .if r0_mpr lsr r1 ror r0 .elif r1_mpr lsr r2 ror r1 .elif r2_mpr lsr r3 ror r2 .elif r3_mpr lsr r4 ror r3 .elif r4_mpr lsr r5 ror r4 .elif r5_mpr lsr r6 ror r5 .elif r6_mpr lsr r7 ror r6 .elif r7_mpr lsr r8 ror r7 .elif r8_mpr lsr r9 ror r8 .elif r9_mpr lsr r10 ror r9 .elif r10_mpr lsr r11 ror r10 .elif r11_mpr lsr r12 ror r11 .elif r12_mpr lsr r13 ror r12 .elif r13_mpr lsr r14 ror r13 .elif r14_mpr lsr r15 ror r14 .elif r15_mpr lsr r16 ror r15 .elif r16_mpr lsr r17 ror r16 .elif r17_mpr lsr r18 ror r17 .elif r18_mpr lsr r19 ror r18 .elif r19_mpr lsr r20 ror r19 .elif r20_mpr lsr r21 ror r20 .elif r21_mpr lsr r22 ror r21 .elif r22_mpr lsr r23 ror r22 .elif r23_mpr lsr r24 ror r23 .elif r24_mpr || temp_mpr || templ_mpr lsr r25 ror r24 .elif r25_mpr || temph_mpr lsr r26 ror r25 .elif r26_mpr || xl_mpr || X_mpr lsr r27 ror r26 .elif r27_mpr || xh_mpr lsr r28 ror r27 .elif r28_mpr || yl_mpr || Y_mpr lsr r29 ror r28 .elif r29_mpr || yh_mpr lsr r30 ror r29 .elif r30_mpr || zl_mpr || Z_mpr lsr r31 ror r30 .else .error "Macro lsr16 reg zu gross" .endif .endm .macro lsr24 ; @0 r0-r29 3c, 6b setr .set @0_mpr = 1 .if r0_mpr lsr r2 ror16 r0 .elif r1_mpr lsr r3 ror16 r1 .elif r2_mpr lsr r4 ror16 r2 .elif r3_mpr lsr r5 ror16 r3 .elif r4_mpr lsr r6 ror16 r4 .elif r5_mpr lsr r7 ror16 r5 .elif r6_mpr lsr r8 ror16 r6 .elif r7_mpr lsr r9 ror16 r7 .elif r8_mpr lsr r10 ror16 r8 .elif r9_mpr lsr r11 ror16 r9 .elif r10_mpr lsr r12 ror16 r10 .elif r11_mpr lsr r13 ror16 r11 .elif r12_mpr lsr r14 ror16 r12 .elif r13_mpr lsr r15 ror16 r13 .elif r14_mpr lsr r16 ror16 r14 .elif r15_mpr lsr r17 ror16 r15 .elif r16_mpr lsr r18 ror16 r16 .elif r17_mpr lsr r19 ror16 r17 .elif r18_mpr lsr r20 ror16 r18 .elif r19_mpr lsr r21 ror16 r19 .elif r20_mpr lsr r22 ror16 r20 .elif r21_mpr lsr r23 ror16 r21 .elif r22_mpr lsr r24 ror16 r22 .elif r23_mpr lsr r25 ror16 r23 .elif r24_mpr lsr r26 ror16 r24 .elif r25_mpr lsr r27 ror16 r25 .elif r26_mpr lsr r28 ror16 r26 .elif r27_mpr lsr r29 ror16 r27 .elif r28_mpr lsr r30 ror16 r28 .elif r29_mpr lsr r31 ror16 r29 .else .error "Macro lsr24 reg zu gross" .endif .endm .macro lsr32 ; @0 r0-r28 4c, 8b setr .set @0_mpr = 1 .if r0_mpr lsr r3 ror24 r0 .elif r1_mpr lsr r4 ror24 r1 .elif r2_mpr lsr r5 ror24 r2 .elif r3_mpr lsr r6 ror24 r3 .elif r4_mpr lsr r7 ror24 r4 .elif r5_mpr lsr r8 ror24 r5 .elif r6_mpr lsr r9 ror24 r6 .elif r7_mpr lsr r10 ror24 r7 .elif r8_mpr lsr r11 ror24 r8 .elif r9_mpr lsr r12 ror24 r9 .elif r10_mpr lsr r13 ror24 r10 .elif r11_mpr lsr r14 ror24 r11 .elif r12_mpr lsr r15 ror24 r12 .elif r13_mpr lsr r16 ror24 r13 .elif r14_mpr lsr r17 ror24 r14 .elif r15_mpr lsr r18 ror24 r15 .elif r16_mpr lsr r19 ror24 r16 .elif r17_mpr lsr r20 ror24 r17 .elif r18_mpr lsr r21 ror24 r18 .elif r19_mpr lsr r22 ror24 r19 .elif r20_mpr lsr r23 ror24 r20 .elif r21_mpr lsr r24 ror24 r21 .elif r22_mpr lsr r25 ror24 r22 .elif r23_mpr lsr r26 ror24 r23 .elif r24_mpr lsr r27 ror24 r24 .elif r25_mpr lsr r28 ror24 r25 .elif r26_mpr lsr r29 ror24 r26 .elif r27_mpr lsr r30 ror24 r27 .elif r28_mpr lsr r31 ror24 r28 .else .error "Macro lsr32 reg zu gross" .endif .endm .macro lsr40 ; @0 r0-r27 5c, 10b setr .set @0_mpr = 1 .if r0_mpr lsr r4 ror32 r0 .elif r1_mpr lsr r5 ror32 r1 .elif r2_mpr lsr r6 ror32 r2 .elif r3_mpr lsr r7 ror32 r3 .elif r4_mpr lsr r8 ror32 r4 .elif r5_mpr lsr r9 ror32 r5 .elif r6_mpr lsr r10 ror32 r6 .elif r7_mpr lsr r11 ror32 r7 .elif r8_mpr lsr r12 ror32 r8 .elif r9_mpr lsr r13 ror32 r9 .elif r10_mpr lsr r14 ror32 r10 .elif r11_mpr lsr r15 ror32 r11 .elif r12_mpr lsr r16 ror32 r12 .elif r13_mpr lsr r17 ror32 r13 .elif r14_mpr lsr r18 ror32 r14 .elif r15_mpr lsr r19 ror32 r15 .elif r16_mpr lsr r20 ror32 r16 .elif r17_mpr lsr r21 ror32 r17 .elif r18_mpr lsr r22 ror32 r18 .elif r19_mpr lsr r23 ror32 r19 .elif r20_mpr lsr r24 ror32 r20 .elif r21_mpr lsr r25 ror32 r21 .elif r22_mpr lsr r26 ror32 r22 .elif r23_mpr lsr r27 ror32 r23 .elif r24_mpr lsr r28 ror32 r24 .elif r25_mpr lsr r29 ror32 r25 .elif r26_mpr lsr r30 ror32 r26 .elif r27_mpr lsr r31 ror32 r27 .else .error "Macro lsr40 reg zu gross" .endif .endm .macro lsr48 ; @0 r0-r26 6c, 12b setr .set @0_mpr = 1 .if r0_mpr lsr r5 ror40 r0 .elif r1_mpr lsr r6 ror40 r1 .elif r2_mpr lsr r7 ror40 r2 .elif r3_mpr lsr r8 ror40 r3 .elif r4_mpr lsr r9 ror40 r4 .elif r5_mpr lsr r10 ror40 r5 .elif r6_mpr lsr r11 ror40 r6 .elif r7_mpr lsr r12 ror40 r7 .elif r8_mpr lsr r13 ror40 r8 .elif r9_mpr lsr r14 ror40 r9 .elif r10_mpr lsr r15 ror40 r10 .elif r11_mpr lsr r16 ror40 r11 .elif r12_mpr lsr r17 ror40 r12 .elif r13_mpr lsr r18 ror40 r13 .elif r14_mpr lsr r19 ror40 r14 .elif r15_mpr lsr r20 ror40 r15 .elif r16_mpr lsr r21 ror40 r16 .elif r17_mpr lsr r22 ror40 r17 .elif r18_mpr lsr r23 ror40 r18 .elif r19_mpr lsr r24 ror40 r19 .elif r20_mpr lsr r25 ror40 r20 .elif r21_mpr lsr r26 ror40 r21 .elif r22_mpr lsr r27 ror40 r22 .elif r23_mpr lsr r28 ror40 r23 .elif r24_mpr lsr r29 ror40 r24 .elif r25_mpr lsr r30 ror40 r25 .elif r26_mpr lsr r31 ror40 r26 .else .error "Macro lsr48 reg zu gross" .endif .endm .macro lsr56 ; @0 r0-r25 7c, 14b setr .set @0_mpr = 1 .if r0_mpr lsr r6 ror48 r0 .elif r1_mpr lsr r7 ror48 r1 .elif r2_mpr lsr r8 ror48 r2 .elif r3_mpr lsr r9 ror48 r3 .elif r4_mpr lsr r10 ror48 r4 .elif r5_mpr lsr r11 ror48 r5 .elif r6_mpr lsr r12 ror48 r6 .elif r7_mpr lsr r13 ror48 r7 .elif r8_mpr lsr r14 ror48 r8 .elif r9_mpr lsr r15 ror48 r9 .elif r10_mpr lsr r16 ror48 r10 .elif r11_mpr lsr r17 ror48 r11 .elif r12_mpr lsr r18 ror48 r12 .elif r13_mpr lsr r19 ror48 r13 .elif r14_mpr lsr r20 ror48 r14 .elif r15_mpr lsr r21 ror48 r15 .elif r16_mpr lsr r22 ror48 r16 .elif r17_mpr lsr r23 ror48 r17 .elif r18_mpr lsr r24 ror48 r18 .elif r19_mpr lsr r25 ror48 r19 .elif r20_mpr lsr r26 ror48 r20 .elif r21_mpr lsr r27 ror48 r21 .elif r22_mpr lsr r28 ror48 r22 .elif r23_mpr lsr r29 ror48 r23 .elif r24_mpr lsr r30 ror48 r24 .elif r25_mpr lsr r31 ror48 r25 .else .error "Macro lsr56 reg zu gross" .endif .endm .macro lsr64 ; @0 r0-r24 8c, 16b setr .set @0_mpr = 1 .if r0_mpr lsr r7 ror56 r0 .elif r1_mpr lsr r8 ror56 r1 .elif r2_mpr lsr r9 ror56 r2 .elif r3_mpr lsr r10 ror56 r3 .elif r4_mpr lsr r11 ror56 r4 .elif r5_mpr lsr r12 ror56 r5 .elif r6_mpr lsr r13 ror56 r6 .elif r7_mpr lsr r14 ror56 r7 .elif r8_mpr lsr r15 ror56 r8 .elif r9_mpr lsr r16 ror56 r9 .elif r10_mpr lsr r17 ror56 r10 .elif r11_mpr lsr r18 ror56 r11 .elif r12_mpr lsr r19 ror56 r12 .elif r13_mpr lsr r20 ror56 r13 .elif r14_mpr lsr r21 ror56 r14 .elif r15_mpr lsr r22 ror56 r15 .elif r16_mpr lsr r23 ror56 r16 .elif r17_mpr lsr r24 ror56 r17 .elif r18_mpr lsr r25 ror56 r18 .elif r19_mpr lsr r26 ror56 r19 .elif r20_mpr lsr r27 ror56 r20 .elif r21_mpr lsr r28 ror56 r21 .elif r22_mpr lsr r29 ror56 r22 .elif r23_mpr lsr r30 ror56 r23 .elif r24_mpr lsr r31 ror56 r24 .else .error "Macro lsr64 reg zu gross" .endif .endm .macro asr16 ; @0 r0-r30 2c, 4b setr .set @0_mpr = 1 .if r0_mpr asr r1 ror r0 .elif r1_mpr asr r2 ror r1 .elif r2_mpr asr r3 ror r2 .elif r3_mpr asr r4 ror r3 .elif r4_mpr asr r5 ror r4 .elif r5_mpr asr r6 ror r5 .elif r6_mpr asr r7 ror r6 .elif r7_mpr asr r8 ror r7 .elif r8_mpr asr r9 ror r8 .elif r9_mpr asr r10 ror r9 .elif r10_mpr asr r11 ror r10 .elif r11_mpr asr r12 ror r11 .elif r12_mpr asr r13 ror r12 .elif r13_mpr asr r14 ror r13 .elif r14_mpr asr r15 ror r14 .elif r15_mpr asr r16 ror r15 .elif r16_mpr asr r17 ror r16 .elif r17_mpr asr r18 ror r17 .elif r18_mpr asr r19 ror r18 .elif r19_mpr asr r20 ror r19 .elif r20_mpr asr r21 ror r20 .elif r21_mpr asr r22 ror r21 .elif r22_mpr asr r23 ror r22 .elif r23_mpr asr r24 ror r23 .elif r24_mpr || temp_mpr || templ_mpr asr r25 ror r24 .elif r25_mpr || temph_mpr asr r26 ror r25 .elif r26_mpr || xl_mpr || X_mpr asr r27 ror r26 .elif r27_mpr || xh_mpr asr r28 ror r27 .elif r28_mpr || yl_mpr || Y_mpr asr r29 ror r28 .elif r29_mpr || yh_mpr asr r30 ror r29 .elif r30_mpr || zl_mpr || Z_mpr asr r31 ror r30 .else .error "Macro asr16 reg zu gross" .endif .endm .macro asr24 ; @0 r0-r29 3c, 6b setr .set @0_mpr = 1 .if r0_mpr asr r2 ror16 r0 .elif r1_mpr asr r3 ror16 r1 .elif r2_mpr asr r4 ror16 r2 .elif r3_mpr asr r5 ror16 r3 .elif r4_mpr asr r6 ror16 r4 .elif r5_mpr asr r7 ror16 r5 .elif r6_mpr asr r8 ror16 r6 .elif r7_mpr asr r9 ror16 r7 .elif r8_mpr asr r10 ror16 r8 .elif r9_mpr asr r11 ror16 r9 .elif r10_mpr asr r12 ror16 r10 .elif r11_mpr asr r13 ror16 r11 .elif r12_mpr asr r14 ror16 r12 .elif r13_mpr asr r15 ror16 r13 .elif r14_mpr asr r16 ror16 r14 .elif r15_mpr asr r17 ror16 r15 .elif r16_mpr asr r18 ror16 r16 .elif r17_mpr asr r19 ror16 r17 .elif r18_mpr asr r20 ror16 r18 .elif r19_mpr asr r21 ror16 r19 .elif r20_mpr asr r22 ror16 r20 .elif r21_mpr asr r23 ror16 r21 .elif r22_mpr asr r24 ror16 r22 .elif r23_mpr asr r25 ror16 r23 .elif r24_mpr asr r26 ror16 r24 .elif r25_mpr asr r27 ror16 r25 .elif r26_mpr asr r28 ror16 r26 .elif r27_mpr asr r29 ror16 r27 .elif r28_mpr asr r30 ror16 r28 .elif r29_mpr asr r31 ror16 r29 .else .error "Macro asr24 reg zu gross" .endif .endm .macro asr32 ; @0 r0-r28 4c, 8b setr .set @0_mpr = 1 .if r0_mpr asr r3 ror24 r0 .elif r1_mpr asr r4 ror24 r1 .elif r2_mpr asr r5 ror24 r2 .elif r3_mpr asr r6 ror24 r3 .elif r4_mpr asr r7 ror24 r4 .elif r5_mpr asr r8 ror24 r5 .elif r6_mpr asr r9 ror24 r6 .elif r7_mpr asr r10 ror24 r7 .elif r8_mpr asr r11 ror24 r8 .elif r9_mpr asr r12 ror24 r9 .elif r10_mpr asr r13 ror24 r10 .elif r11_mpr asr r14 ror24 r11 .elif r12_mpr asr r15 ror24 r12 .elif r13_mpr asr r16 ror24 r13 .elif r14_mpr asr r17 ror24 r14 .elif r15_mpr asr r18 ror24 r15 .elif r16_mpr asr r19 ror24 r16 .elif r17_mpr asr r20 ror24 r17 .elif r18_mpr asr r21 ror24 r18 .elif r19_mpr asr r22 ror24 r19 .elif r20_mpr asr r23 ror24 r20 .elif r21_mpr asr r24 ror24 r21 .elif r22_mpr asr r25 ror24 r22 .elif r23_mpr asr r26 ror24 r23 .elif r24_mpr asr r27 ror24 r24 .elif r25_mpr asr r28 ror24 r25 .elif r26_mpr asr r29 ror24 r26 .elif r27_mpr asr r30 ror24 r27 .elif r28_mpr asr r31 ror24 r28 .else .error "Macro asr32 reg zu gross" .endif .endm .macro asr40 ; @0 r0-r27 5c, 10b setr .set @0_mpr = 1 .if r0_mpr asr r4 ror32 r0 .elif r1_mpr asr r5 ror32 r1 .elif r2_mpr asr r6 ror32 r2 .elif r3_mpr asr r7 ror32 r3 .elif r4_mpr asr r8 ror32 r4 .elif r5_mpr asr r9 ror32 r5 .elif r6_mpr asr r10 ror32 r6 .elif r7_mpr asr r11 ror32 r7 .elif r8_mpr asr r12 ror32 r8 .elif r9_mpr asr r13 ror32 r9 .elif r10_mpr asr r14 ror32 r10 .elif r11_mpr asr r15 ror32 r11 .elif r12_mpr asr r16 ror32 r12 .elif r13_mpr asr r17 ror32 r13 .elif r14_mpr asr r18 ror32 r14 .elif r15_mpr asr r19 ror32 r15 .elif r16_mpr asr r20 ror32 r16 .elif r17_mpr asr r21 ror32 r17 .elif r18_mpr asr r22 ror32 r18 .elif r19_mpr asr r23 ror32 r19 .elif r20_mpr asr r24 ror32 r20 .elif r21_mpr asr r25 ror32 r21 .elif r22_mpr asr r26 ror32 r22 .elif r23_mpr asr r27 ror32 r23 .elif r24_mpr asr r28 ror32 r24 .elif r25_mpr asr r29 ror32 r25 .elif r26_mpr asr r30 ror32 r26 .elif r27_mpr asr r31 ror32 r27 .else .error "Macro asr40 reg zu gross" .endif .endm .macro asr48 ; @0 r0-r26 6c, 12b setr .set @0_mpr = 1 .if r0_mpr asr r5 ror40 r0 .elif r1_mpr asr r6 ror40 r1 .elif r2_mpr asr r7 ror40 r2 .elif r3_mpr asr r8 ror40 r3 .elif r4_mpr asr r9 ror40 r4 .elif r5_mpr asr r10 ror40 r5 .elif r6_mpr asr r11 ror40 r6 .elif r7_mpr asr r12 ror40 r7 .elif r8_mpr asr r13 ror40 r8 .elif r9_mpr asr r14 ror40 r9 .elif r10_mpr asr r15 ror40 r10 .elif r11_mpr asr r16 ror40 r11 .elif r12_mpr asr r17 ror40 r12 .elif r13_mpr asr r18 ror40 r13 .elif r14_mpr asr r19 ror40 r14 .elif r15_mpr asr r20 ror40 r15 .elif r16_mpr asr r21 ror40 r16 .elif r17_mpr asr r22 ror40 r17 .elif r18_mpr asr r23 ror40 r18 .elif r19_mpr asr r24 ror40 r19 .elif r20_mpr asr r25 ror40 r20 .elif r21_mpr asr r26 ror40 r21 .elif r22_mpr asr r27 ror40 r22 .elif r23_mpr asr r28 ror40 r23 .elif r24_mpr asr r29 ror40 r24 .elif r25_mpr asr r30 ror40 r25 .elif r26_mpr asr r31 ror40 r26 .else .error "Macro asr48 reg zu gross" .endif .endm .macro asr56 ; @0 r0-r25 7c, 14b setr .set @0_mpr = 1 .if r0_mpr asr r6 ror48 r0 .elif r1_mpr asr r7 ror48 r1 .elif r2_mpr asr r8 ror48 r2 .elif r3_mpr asr r9 ror48 r3 .elif r4_mpr asr r10 ror48 r4 .elif r5_mpr asr r11 ror48 r5 .elif r6_mpr asr r12 ror48 r6 .elif r7_mpr asr r13 ror48 r7 .elif r8_mpr asr r14 ror48 r8 .elif r9_mpr asr r15 ror48 r9 .elif r10_mpr asr r16 ror48 r10 .elif r11_mpr asr r17 ror48 r11 .elif r12_mpr asr r18 ror48 r12 .elif r13_mpr asr r19 ror48 r13 .elif r14_mpr asr r20 ror48 r14 .elif r15_mpr asr r21 ror48 r15 .elif r16_mpr asr r22 ror48 r16 .elif r17_mpr asr r23 ror48 r17 .elif r18_mpr asr r24 ror48 r18 .elif r19_mpr asr r25 ror48 r19 .elif r20_mpr asr r26 ror48 r20 .elif r21_mpr asr r27 ror48 r21 .elif r22_mpr asr r28 ror48 r22 .elif r23_mpr asr r29 ror48 r23 .elif r24_mpr asr r30 ror48 r24 .elif r25_mpr asr r31 ror48 r25 .else .error "Macro asr56 reg zu gross" .endif .endm .macro asr64 ; @0 r0-r24 8c, 16b setr .set @0_mpr = 1 .if r0_mpr asr r7 ror56 r0 .elif r1_mpr asr r8 ror56 r1 .elif r2_mpr asr r9 ror56 r2 .elif r3_mpr asr r10 ror56 r3 .elif r4_mpr asr r11 ror56 r4 .elif r5_mpr asr r12 ror56 r5 .elif r6_mpr asr r13 ror56 r6 .elif r7_mpr asr r14 ror56 r7 .elif r8_mpr asr r15 ror56 r8 .elif r9_mpr asr r16 ror56 r9 .elif r10_mpr asr r17 ror56 r10 .elif r11_mpr asr r18 ror56 r11 .elif r12_mpr asr r19 ror56 r12 .elif r13_mpr asr r20 ror56 r13 .elif r14_mpr asr r21 ror56 r14 .elif r15_mpr asr r22 ror56 r15 .elif r16_mpr asr r23 ror56 r16 .elif r17_mpr asr r24 ror56 r17 .elif r18_mpr asr r25 ror56 r18 .elif r19_mpr asr r26 ror56 r19 .elif r20_mpr asr r27 ror56 r20 .elif r21_mpr asr r28 ror56 r21 .elif r22_mpr asr r29 ror56 r22 .elif r23_mpr asr r30 ror56 r23 .elif r24_mpr asr r31 ror56 r24 .else .error "Macro asr64 reg zu gross" .endif .endm .macro rl16 ; @0 r0-r30 5c, 10b setr .set @0_mpr = 1 .if r0_mpr setcarry r1,7 rol16 r0 .elif r1_mpr setcarry r2,7 rol16 r1 .elif r2_mpr setcarry r3,7 rol16 r2 .elif r3_mpr setcarry r4,7 rol16 r3 .elif r4_mpr setcarry r5,7 rol16 r4 .elif r5_mpr setcarry r6,7 rol16 r5 .elif r6_mpr setcarry r7,7 rol16 r6 .elif r7_mpr setcarry r8,7 rol16 r7 .elif r8_mpr setcarry r9,7 rol16 r8 .elif r9_mpr setcarry r10,7 rol16 r9 .elif r10_mpr setcarry r11,7 rol16 r10 .elif r11_mpr setcarry r12,7 rol16 r11 .elif r12_mpr setcarry r13,7 rol16 r12 .elif r13_mpr setcarry r14,7 rol16 r13 .elif r14_mpr setcarry r15,7 rol16 r14 .elif r15_mpr setcarry r16,7 rol16 r15 .elif r16_mpr setcarry r17,7 rol16 r16 .elif r17_mpr setcarry r18,7 rol16 r17 .elif r18_mpr setcarry r19,7 rol16 r18 .elif r19_mpr setcarry r20,7 rol16 r19 .elif r20_mpr setcarry r21,7 rol16 r20 .elif r21_mpr setcarry r22,7 rol16 r21 .elif r22_mpr setcarry r23,7 rol16 r22 .elif r23_mpr setcarry r24,7 rol16 r23 .elif r24_mpr || temp_mpr || templ_mpr setcarry r25,7 rol16 r24 .elif r25_mpr || temph_mpr setcarry r26,7 rol16 r25 .elif r26_mpr || xl_mpr || X_mpr setcarry r27,7 rol16 r26 .elif r27_mpr || xh_mpr setcarry r28,7 rol16 r27 .elif r28_mpr || yl_mpr || Y_mpr setcarry r29,7 rol16 r28 .elif r29_mpr || yh_mpr setcarry r30,7 rol16 r29 .elif r30_mpr || zl_mpr || Z_mpr setcarry r31,7 rol16 r30 .else .error "Macro rl16 reg zu gross" .endif .endm .macro rl24 ; @0 r0-r29 6c, 12b setr .set @0_mpr = 1 .if r0_mpr setcarry r2,7 rol24 r0 .elif r1_mpr setcarry r3,7 rol24 r1 .elif r2_mpr setcarry r4,7 rol24 r2 .elif r3_mpr setcarry r5,7 rol24 r3 .elif r4_mpr setcarry r6,7 rol24 r4 .elif r5_mpr setcarry r7,7 rol24 r5 .elif r6_mpr setcarry r8,7 rol24 r6 .elif r7_mpr setcarry r9,7 rol24 r7 .elif r8_mpr setcarry r10,7 rol24 r8 .elif r9_mpr setcarry r11,7 rol24 r9 .elif r10_mpr setcarry r12,7 rol24 r10 .elif r11_mpr setcarry r13,7 rol24 r11 .elif r12_mpr setcarry r14,7 rol24 r12 .elif r13_mpr setcarry r15,7 rol24 r13 .elif r14_mpr setcarry r16,7 rol24 r14 .elif r15_mpr setcarry r17,7 rol24 r15 .elif r16_mpr setcarry r18,7 rol24 r16 .elif r17_mpr setcarry r19,7 rol24 r17 .elif r18_mpr setcarry r20,7 rol24 r18 .elif r19_mpr setcarry r21,7 rol24 r19 .elif r20_mpr setcarry r22,7 rol24 r20 .elif r21_mpr setcarry r23,7 rol24 r21 .elif r22_mpr setcarry r24,7 rol24 r22 .elif r23_mpr setcarry r25,7 rol24 r23 .elif r24_mpr setcarry r26,7 rol24 r24 .elif r25_mpr setcarry r27,7 rol24 r25 .elif r26_mpr setcarry r28,7 rol24 r26 .elif r27_mpr setcarry r29,7 rol24 r27 .elif r28_mpr setcarry r30,7 rol24 r28 .elif r29_mpr setcarry r31,7 rol24 r29 .else .error "Macro rl24 reg zu gross" .endif .endm .macro rl32 ; @0 r0-r28 7c, 14b setr .set @0_mpr = 1 .if r0_mpr setcarry r3,7 rol32 r0 .elif r1_mpr setcarry r4,7 rol32 r1 .elif r2_mpr setcarry r5,7 rol32 r2 .elif r3_mpr setcarry r6,7 rol32 r3 .elif r4_mpr setcarry r7,7 rol32 r4 .elif r5_mpr setcarry r8,7 rol32 r5 .elif r6_mpr setcarry r9,7 rol32 r6 .elif r7_mpr setcarry r10,7 rol32 r7 .elif r8_mpr setcarry r11,7 rol32 r8 .elif r9_mpr setcarry r12,7 rol32 r9 .elif r10_mpr setcarry r13,7 rol32 r10 .elif r11_mpr setcarry r14,7 rol32 r11 .elif r12_mpr setcarry r15,7 rol32 r12 .elif r13_mpr setcarry r16,7 rol32 r13 .elif r14_mpr setcarry r17,7 rol32 r14 .elif r15_mpr setcarry r18,7 rol32 r15 .elif r16_mpr setcarry r19,7 rol32 r16 .elif r17_mpr setcarry r20,7 rol32 r17 .elif r18_mpr setcarry r21,7 rol32 r18 .elif r19_mpr setcarry r22,7 rol32 r19 .elif r20_mpr setcarry r23,7 rol32 r20 .elif r21_mpr setcarry r24,7 rol32 r21 .elif r22_mpr setcarry r25,7 rol32 r22 .elif r23_mpr setcarry r26,7 rol32 r23 .elif r24_mpr setcarry r27,7 rol32 r24 .elif r25_mpr setcarry r28,7 rol32 r25 .elif r26_mpr setcarry r29,7 rol32 r26 .elif r27_mpr setcarry r30,7 rol32 r27 .elif r28_mpr setcarry r31,7 rol32 r28 .else .error "Macro rl32 reg zu gross" .endif .endm .macro rl40 ; @0 r0-r27 8c, 16b setr .set @0_mpr = 1 .if r0_mpr setcarry r4,7 rol40 r0 .elif r1_mpr setcarry r4,7 rol40 r1 .elif r2_mpr setcarry r6,7 rol40 r2 .elif r3_mpr setcarry r7,7 rol40 r3 .elif r4_mpr setcarry r8,7 rol40 r4 .elif r5_mpr setcarry r9,7 rol40 r5 .elif r6_mpr setcarry r10,7 rol40 r6 .elif r7_mpr setcarry r11,7 rol40 r7 .elif r8_mpr setcarry r12,7 rol40 r8 .elif r9_mpr setcarry r13,7 rol40 r9 .elif r10_mpr setcarry r14,7 rol40 r10 .elif r11_mpr setcarry r15,7 rol40 r11 .elif r12_mpr setcarry r16,7 rol40 r12 .elif r13_mpr setcarry r17,7 rol40 r13 .elif r14_mpr setcarry r18,7 rol40 r14 .elif r15_mpr setcarry r19,7 rol40 r15 .elif r16_mpr setcarry r20,7 rol40 r16 .elif r17_mpr setcarry r21,7 rol40 r17 .elif r18_mpr setcarry r22,7 rol40 r18 .elif r19_mpr setcarry r23,7 rol40 r19 .elif r20_mpr setcarry r24,7 rol40 r20 .elif r21_mpr setcarry r25,7 rol40 r21 .elif r22_mpr setcarry r26,7 rol40 r22 .elif r23_mpr setcarry r27,7 rol40 r23 .elif r24_mpr setcarry r28,7 rol40 r24 .elif r25_mpr setcarry r29,7 rol40 r25 .elif r26_mpr setcarry r30,7 rol40 r26 .elif r27_mpr setcarry r31,7 rol40 r27 .else .error "Macro rl40 reg zu gross" .endif .endm .macro rl48 ; @0 r0-r26 9c, 18b setr .set @0_mpr = 1 .if r0_mpr setcarry r5,7 rol48 r0 .elif r1_mpr setcarry r6,7 rol48 r1 .elif r2_mpr setcarry r7,7 rol48 r2 .elif r3_mpr setcarry r8,7 rol48 r3 .elif r4_mpr setcarry r9,7 rol48 r4 .elif r5_mpr setcarry r10,7 rol48 r5 .elif r6_mpr setcarry r11,7 rol48 r6 .elif r7_mpr setcarry r12,7 rol48 r7 .elif r8_mpr setcarry r13,7 rol48 r8 .elif r9_mpr setcarry r14,7 rol48 r9 .elif r10_mpr setcarry r15,7 rol48 r10 .elif r11_mpr setcarry r16,7 rol48 r11 .elif r12_mpr setcarry r17,7 rol48 r12 .elif r13_mpr setcarry r18,7 rol48 r13 .elif r14_mpr setcarry r19,7 rol48 r14 .elif r15_mpr setcarry r20,7 rol48 r15 .elif r16_mpr setcarry r21,7 rol48 r16 .elif r17_mpr setcarry r22,7 rol48 r17 .elif r18_mpr setcarry r23,7 rol48 r18 .elif r19_mpr setcarry r24,7 rol48 r19 .elif r20_mpr setcarry r25,7 rol48 r20 .elif r21_mpr setcarry r26,7 rol48 r21 .elif r22_mpr setcarry r27,7 rol48 r22 .elif r23_mpr setcarry r28,7 rol48 r23 .elif r24_mpr setcarry r29,7 rol48 r24 .elif r25_mpr setcarry r30,7 rol48 r25 .elif r26_mpr setcarry r31,7 rol48 r26 .else .error "Macro rl48 reg zu gross" .endif .endm .macro rl56 ; @0 r0-r25 10c, 20b setr .set @0_mpr = 1 .if r0_mpr setcarry r6,7 rol56 r0 .elif r1_mpr setcarry r7,7 rol56 r1 .elif r2_mpr setcarry r8,7 rol56 r2 .elif r3_mpr setcarry r9,7 rol56 r3 .elif r4_mpr setcarry r10,7 rol56 r4 .elif r5_mpr setcarry r11,7 rol56 r5 .elif r6_mpr setcarry r12,7 rol56 r6 .elif r7_mpr setcarry r13,7 rol56 r7 .elif r8_mpr setcarry r14,7 rol56 r8 .elif r9_mpr setcarry r15,7 rol56 r9 .elif r10_mpr setcarry r16,7 rol56 r10 .elif r11_mpr setcarry r17,7 rol56 r11 .elif r12_mpr setcarry r18,7 rol56 r12 .elif r13_mpr setcarry r19,7 rol56 r13 .elif r14_mpr setcarry r20,7 rol56 r14 .elif r15_mpr setcarry r21,7 rol56 r15 .elif r16_mpr setcarry r22,7 rol56 r16 .elif r17_mpr setcarry r23,7 rol56 r17 .elif r18_mpr setcarry r24,7 rol56 r18 .elif r19_mpr setcarry r25,7 rol56 r19 .elif r20_mpr setcarry r26,7 rol56 r20 .elif r21_mpr setcarry r27,7 rol56 r21 .elif r22_mpr setcarry r28,7 rol56 r22 .elif r23_mpr setcarry r29,7 rol56 r23 .elif r24_mpr setcarry r30,7 rol56 r24 .elif r25_mpr setcarry r31,7 rol56 r25 .else .error "Macro rl56 reg zu gross" .endif .endm .macro rl64 ; @0 r0-r24 11c, 22b setr .set @0_mpr = 1 .if r0_mpr setcarry r7,7 rol64 r0 .elif r1_mpr setcarry r8,7 rol64 r1 .elif r2_mpr setcarry r9,7 rol64 r2 .elif r3_mpr setcarry r10,7 rol64 r3 .elif r4_mpr setcarry r11,7 rol64 r4 .elif r5_mpr setcarry r12,7 rol64 r5 .elif r6_mpr setcarry r13,7 rol64 r6 .elif r7_mpr setcarry r14,7 rol64 r7 .elif r8_mpr setcarry r15,7 rol64 r8 .elif r9_mpr setcarry r16,7 rol64 r9 .elif r10_mpr setcarry r17,7 rol64 r10 .elif r11_mpr setcarry r18,7 rol64 r11 .elif r12_mpr setcarry r19,7 rol64 r12 .elif r13_mpr setcarry r20,7 rol64 r13 .elif r14_mpr setcarry r21,7 rol64 r14 .elif r15_mpr setcarry r22,7 rol64 r15 .elif r16_mpr setcarry r23,7 rol64 r16 .elif r17_mpr setcarry r24,7 rol64 r17 .elif r18_mpr setcarry r25,7 rol64 r18 .elif r19_mpr setcarry r26,7 rol64 r19 .elif r20_mpr setcarry r27,7 rol64 r20 .elif r21_mpr setcarry r28,7 rol64 r21 .elif r22_mpr setcarry r29,7 rol64 r22 .elif r23_mpr setcarry r30,7 rol64 r23 .elif r24_mpr setcarry r31,7 rol64 r24 .else .error "Macro rl64 reg zu gross" .endif .endm .macro rr16 ; @0 r0-r30 5c, 10b setr .set @0_mpr = 1 .if r0_mpr setcarry r0,0 ror16 r0 .elif r1_mpr setcarry r1,0 ror16 r1 .elif r2_mpr setcarry r2,0 ror16 r2 .elif r3_mpr setcarry r3,0 ror16 r3 .elif r4_mpr setcarry r4,0 ror16 r4 .elif r5_mpr setcarry r5,0 ror16 r5 .elif r6_mpr setcarry r6,0 ror16 r6 .elif r7_mpr setcarry r7,0 ror16 r7 .elif r8_mpr setcarry r8,0 ror16 r8 .elif r9_mpr setcarry r9,0 ror16 r9 .elif r10_mpr setcarry r10,0 ror16 r10 .elif r11_mpr setcarry r11,0 ror16 r11 .elif r12_mpr setcarry r12,0 ror16 r12 .elif r13_mpr setcarry r13,0 ror16 r13 .elif r14_mpr setcarry r14,0 ror16 r14 .elif r15_mpr setcarry r15,0 ror16 r15 .elif r16_mpr setcarry r16,0 ror16 r16 .elif r17_mpr setcarry r17,0 ror16 r17 .elif r18_mpr setcarry r18,0 ror16 r18 .elif r19_mpr setcarry r19,0 ror16 r19 .elif r20_mpr setcarry r20,0 ror16 r20 .elif r21_mpr setcarry r21,0 ror16 r21 .elif r22_mpr setcarry r22,0 ror16 r22 .elif r23_mpr setcarry r23,0 ror16 r23 .elif r24_mpr || temp_mpr || templ_mpr setcarry r24,0 ror16 r24 .elif r25_mpr || temph_mpr setcarry r25,0 ror16 r25 .elif r26_mpr || xl_mpr || X_mpr setcarry r26,0 ror16 r26 .elif r27_mpr || xh_mpr setcarry r27,0 ror16 r27 .elif r28_mpr || yl_mpr || Y_mpr setcarry r28,0 ror16 r28 .elif r29_mpr || yh_mpr setcarry r29,0 ror16 r29 .elif r30_mpr || zl_mpr || Z_mpr setcarry r30,0 ror16 r30 .else .error "Macro rr16 reg zu gross" .endif .endm .macro rr24 ; @0 r0-r29 6c, 12b setr .set @0_mpr = 1 .if r0_mpr setcarry r0,0 ror24 r0 .elif r1_mpr setcarry r1,0 ror24 r1 .elif r2_mpr setcarry r2,0 ror24 r2 .elif r3_mpr setcarry r3,0 ror24 r3 .elif r4_mpr setcarry r4,0 ror24 r4 .elif r5_mpr setcarry r5,0 ror24 r5 .elif r6_mpr setcarry r6,0 ror24 r6 .elif r7_mpr setcarry r7,0 ror24 r7 .elif r8_mpr setcarry r8,0 ror24 r8 .elif r9_mpr setcarry r9,0 ror24 r9 .elif r10_mpr setcarry r10,0 ror24 r10 .elif r11_mpr setcarry r11,0 ror24 r11 .elif r12_mpr setcarry r12,0 ror24 r12 .elif r13_mpr setcarry r13,0 ror24 r13 .elif r14_mpr setcarry r14,0 ror24 r14 .elif r15_mpr setcarry r15,0 ror24 r15 .elif r16_mpr setcarry r16,0 ror24 r16 .elif r17_mpr setcarry r17,0 ror24 r17 .elif r18_mpr setcarry r18,0 ror24 r18 .elif r19_mpr setcarry r19,0 ror24 r19 .elif r20_mpr setcarry r20,0 ror24 r20 .elif r21_mpr setcarry r21,0 ror24 r21 .elif r22_mpr setcarry r22,0 ror24 r22 .elif r23_mpr setcarry r23,0 ror24 r23 .elif r24_mpr setcarry r24,0 ror24 r24 .elif r25_mpr setcarry r25,0 ror24 r25 .elif r26_mpr setcarry r26,0 ror24 r26 .elif r27_mpr setcarry r27,0 ror24 r27 .elif r28_mpr setcarry r28,0 ror24 r28 .elif r29_mpr setcarry r29,0 ror24 r29 .else .error "Macro rr24 reg zu gross" .endif .endm .macro rr32 ; @0 r0-r28 7c, 14b setr .set @0_mpr = 1 .if r0_mpr setcarry r0,0 ror32 r0 .elif r1_mpr setcarry r1,0 ror32 r1 .elif r2_mpr setcarry r2,0 ror32 r2 .elif r3_mpr setcarry r3,0 ror32 r3 .elif r4_mpr setcarry r4,0 ror32 r4 .elif r5_mpr setcarry r5,0 ror32 r5 .elif r6_mpr setcarry r6,0 ror32 r6 .elif r7_mpr setcarry r7,0 ror32 r7 .elif r8_mpr setcarry r8,0 ror32 r8 .elif r9_mpr setcarry r9,0 ror32 r9 .elif r10_mpr setcarry r10,0 ror32 r10 .elif r11_mpr setcarry r11,0 ror32 r11 .elif r12_mpr setcarry r12,0 ror32 r12 .elif r13_mpr setcarry r13,0 ror32 r13 .elif r14_mpr setcarry r14,0 ror32 r14 .elif r15_mpr setcarry r15,0 ror32 r15 .elif r16_mpr setcarry r16,0 ror32 r16 .elif r17_mpr setcarry r17,0 ror32 r17 .elif r18_mpr setcarry r18,0 ror32 r18 .elif r19_mpr setcarry r19,0 ror32 r19 .elif r20_mpr setcarry r20,0 ror32 r20 .elif r21_mpr setcarry r21,0 ror32 r21 .elif r22_mpr setcarry r22,0 ror32 r22 .elif r23_mpr setcarry r23,0 ror32 r23 .elif r24_mpr setcarry r24,0 ror32 r24 .elif r25_mpr setcarry r25,0 ror32 r25 .elif r26_mpr setcarry r26,0 ror32 r26 .elif r27_mpr setcarry r27,0 ror32 r27 .elif r28_mpr setcarry r28,0 ror32 r28 .else .error "Macro rr32 reg zu gross" .endif .endm .macro rr40 ; @0 r0-r27 8c, 16b setr .set @0_mpr = 1 .if r0_mpr setcarry r0,0 ror40 r0 .elif r1_mpr setcarry r1,0 ror40 r1 .elif r2_mpr setcarry r2,0 ror40 r2 .elif r3_mpr setcarry r3,0 ror40 r3 .elif r4_mpr setcarry r4,0 ror40 r4 .elif r5_mpr setcarry r5,0 ror40 r5 .elif r6_mpr setcarry r6,0 ror40 r6 .elif r7_mpr setcarry r7,0 ror40 r7 .elif r8_mpr setcarry r8,0 ror40 r8 .elif r9_mpr setcarry r9,0 ror40 r9 .elif r10_mpr setcarry r10,0 ror40 r10 .elif r11_mpr setcarry r11,0 ror40 r11 .elif r12_mpr setcarry r12,0 ror40 r12 .elif r13_mpr setcarry r13,0 ror40 r13 .elif r14_mpr setcarry r14,0 ror40 r14 .elif r15_mpr setcarry r15,0 ror40 r15 .elif r16_mpr setcarry r16,0 ror40 r16 .elif r17_mpr setcarry r17,0 ror40 r17 .elif r18_mpr setcarry r18,0 ror40 r18 .elif r19_mpr setcarry r19,0 ror40 r19 .elif r20_mpr setcarry r20,0 ror40 r20 .elif r21_mpr setcarry r21,0 ror40 r21 .elif r22_mpr setcarry r22,0 ror40 r22 .elif r23_mpr setcarry r23,0 ror40 r23 .elif r24_mpr setcarry r24,0 ror40 r24 .elif r25_mpr setcarry r25,0 ror40 r25 .elif r26_mpr setcarry r26,0 ror40 r26 .elif r27_mpr setcarry r27,0 ror40 r27 .else .error "Macro rr40 reg zu gross" .endif .endm .macro rr48 ; @0 r0-r26 9c, 18b setr .set @0_mpr = 1 .if r0_mpr setcarry r0,0 ror48 r0 .elif r1_mpr setcarry r1,0 ror48 r1 .elif r2_mpr setcarry r2,0 ror48 r2 .elif r3_mpr setcarry r3,0 ror48 r3 .elif r4_mpr setcarry r4,0 ror48 r4 .elif r5_mpr setcarry r5,0 ror48 r5 .elif r6_mpr setcarry r6,0 ror48 r6 .elif r7_mpr setcarry r7,0 ror48 r7 .elif r8_mpr setcarry r8,0 ror48 r8 .elif r9_mpr setcarry r9,0 ror48 r9 .elif r10_mpr setcarry r10,0 ror48 r10 .elif r11_mpr setcarry r11,0 ror48 r11 .elif r12_mpr setcarry r12,0 ror48 r12 .elif r13_mpr setcarry r13,0 ror48 r13 .elif r14_mpr setcarry r14,0 ror48 r14 .elif r15_mpr setcarry r15,0 ror48 r15 .elif r16_mpr setcarry r16,0 ror48 r16 .elif r17_mpr setcarry r17,0 ror48 r17 .elif r18_mpr setcarry r18,0 ror48 r18 .elif r19_mpr setcarry r19,0 ror48 r19 .elif r20_mpr setcarry r20,0 ror48 r20 .elif r21_mpr setcarry r21,0 ror48 r21 .elif r22_mpr setcarry r22,0 ror48 r22 .elif r23_mpr setcarry r23,0 ror48 r23 .elif r24_mpr setcarry r24,0 ror48 r24 .elif r25_mpr setcarry r25,0 ror48 r25 .elif r26_mpr setcarry r26,0 ror48 r26 .else .error "Macro rr48 reg zu gross" .endif .endm .macro rr56 ; @0 r0-r25 10c, 20b setr .set @0_mpr = 1 .if r0_mpr setcarry r0,0 ror56 r0 .elif r1_mpr setcarry r1,0 ror56 r1 .elif r2_mpr setcarry r2,0 ror56 r2 .elif r3_mpr setcarry r3,0 ror56 r3 .elif r4_mpr setcarry r4,0 ror56 r4 .elif r5_mpr setcarry r5,0 ror56 r5 .elif r6_mpr setcarry r6,0 ror56 r6 .elif r7_mpr setcarry r7,0 ror56 r7 .elif r8_mpr setcarry r8,0 ror56 r8 .elif r9_mpr setcarry r9,0 ror56 r9 .elif r10_mpr setcarry r10,0 ror56 r10 .elif r11_mpr setcarry r11,0 ror56 r11 .elif r12_mpr setcarry r12,0 ror56 r12 .elif r13_mpr setcarry r13,0 ror56 r13 .elif r14_mpr setcarry r14,0 ror56 r14 .elif r15_mpr setcarry r15,0 ror56 r15 .elif r16_mpr setcarry r16,0 ror56 r16 .elif r17_mpr setcarry r17,0 ror56 r17 .elif r18_mpr setcarry r18,0 ror56 r18 .elif r19_mpr setcarry r19,0 ror56 r19 .elif r20_mpr setcarry r20,0 ror56 r20 .elif r21_mpr setcarry r21,0 ror56 r21 .elif r22_mpr setcarry r22,0 ror56 r22 .elif r23_mpr setcarry r23,0 ror56 r23 .elif r24_mpr setcarry r24,0 ror56 r24 .elif r25_mpr setcarry r25,0 ror56 r25 .else .error "Macro rr56 reg zu gross" .endif .endm .macro rr64 ; @0 r0-r24 11c, 22b setr .set @0_mpr = 1 .if r0_mpr setcarry r0,0 ror64 r0 .elif r1_mpr setcarry r1,0 ror64 r1 .elif r2_mpr setcarry r2,0 ror64 r2 .elif r3_mpr setcarry r3,0 ror64 r3 .elif r4_mpr setcarry r4,0 ror64 r4 .elif r5_mpr setcarry r5,0 ror64 r5 .elif r6_mpr setcarry r6,0 ror64 r6 .elif r7_mpr setcarry r7,0 ror64 r7 .elif r8_mpr setcarry r8,0 ror64 r8 .elif r9_mpr setcarry r9,0 ror64 r9 .elif r10_mpr setcarry r10,0 ror64 r10 .elif r11_mpr setcarry r11,0 ror64 r11 .elif r12_mpr setcarry r12,0 ror64 r12 .elif r13_mpr setcarry r13,0 ror64 r13 .elif r14_mpr setcarry r14,0 ror64 r14 .elif r15_mpr setcarry r15,0 ror64 r15 .elif r16_mpr setcarry r16,0 ror64 r16 .elif r17_mpr setcarry r17,0 ror64 r17 .elif r18_mpr setcarry r18,0 ror64 r18 .elif r19_mpr setcarry r19,0 ror64 r19 .elif r20_mpr setcarry r20,0 ror64 r20 .elif r21_mpr setcarry r21,0 ror64 r21 .elif r22_mpr setcarry r22,0 ror64 r22 .elif r23_mpr setcarry r23,0 ror64 r23 .elif r24_mpr setcarry r24,0 ror64 r24 .else .error "Macro rr64 reg zu gross" .endif .endm #endif /* _MACRO_BASIC_ */ ;========================================================================= ;========================================================================= ;=========================================================================