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-- Company: 
-- Engineer: 
-- 
-- Create Date: 04.05.2021 17:53:58
-- Design Name: 
-- Module Name: asm - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity asm is
    Port ( clk : in STD_LOGIC;
           start : in STD_LOGIC;
           multiplicand : in STD_LOGIC_VECTOR (2 downto 0);
           multiplier : in STD_LOGIC_VECTOR (2 downto 0);
           product : out STD_LOGIC_VECTOR (5 downto 0);
           done : out STD_LOGIC);
end asm;

architecture Behavioral of asm is

type state_type is (S0, S1, S2, S3, S4);
signal state, next_state : state_type;
signal shift : std_logic;
signal CU : std_logic;
signal CD : std_logic;
signal add : std_logic;
signal M : unsigned(2 downto 0) := "000";
signal result : unsigned(5 downto 0) := (others => '0');
signal result_shift : unsigned(5 downto 0) := (others => '0');
signal i : integer range 0 to 4 := 0;
signal start_res : std_logic;
signal done_int : std_logic := '0';



begin

done <= done_int;


SYNC_PROC : process(clk)
begin
    if rising_edge(clk) then
        state <= next_state;
        if start_res = '1' then
            result <= (others => '0');
            M <= unsigned(multiplier);
           result_shift <= shift_left("000" &(unsigned(multiplicand)),0);
        elsif shift = '1' then
            M <= shift_right(unsigned(multiplier),i+1);
            result_shift <= shift_left("000" &(unsigned(multiplicand)),i+1);
        elsif add = '1' then
            result <= result + result_shift;
        end if;
        
        
    
        
            
                
        if done_int = '1' then
            i <= 0;
            CD <= '0';
        elsif i = 2 then
            CD <= '1';
        elsif CU = '1' then
            i <= i + 1;
        end if;
            
    end if;
end process;




NEXT_STATE_DECODE : process (state, start, M, CD, result)
begin

add <= '0';
CU <= '0';
shift <= '0';
start_res <= '0';


    case (state) is
        when S0 =>
            
            if start = '1' then
                next_state <= S1;
             else
                next_state <= S0;
            end if;

        
        when S1 => 
            start_res <= '1';
            product <= "000" & std_logic_vector(M);
            done_int <= '0';
            if falling_edge(start)  then
                next_state <= S2;
            else
                next_state <= S1;
            end if;    
        when S2 =>
            product <= std_logic_vector(result);
            if M(0) = '1' then
                add <= '1';
            end if;
            next_state <= S3;
            
        when S3 =>
            product <= std_logic_vector(result_shift);
            shift <= '1';
            CU <= '1';
            if CD = '1' then
                next_state <= S4;
                product <= std_logic_vector(result);
            else
                next_state <= S2;
            end if;
       
        when S4 => 
            done_int <= '1';
            next_state <= S0;
        
        when others =>
            next_state <= S0;
        
        end case;
end process;
end Behavioral;