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-- Company: 
-- Engineer: 
-- 
-- Create Date: 05.05.2021 17:47:01
-- Design Name: 
-- Module Name: tb - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity tb is
--  Port ( );
end tb;

architecture Behavioral of tb is

component ASM
    Port ( clk : in STD_LOGIC;
           start : in STD_LOGIC;
           multiplicand : in STD_LOGIC_VECTOR (2 downto 0);
           multiplier : in STD_LOGIC_VECTOR (2 downto 0);
           product : out STD_LOGIC_VECTOR (5 downto 0);
           done : out STD_LOGIC);
end component;

signal clk_int : std_logic := '0';
signal start_int : std_logic;
signal multiplicand_int : std_logic_vector (2 downto 0);
signal multiplier_int : std_logic_vector (2 downto 0);
signal product_int : std_logic_vector(5 downto 0);
signal done_int : std_logic;

begin

DUT : ASM
    port map (  clk => clk_int,
                start => start_int,
                multiplicand => multiplicand_int,
                multiplier => multiplier_int,
                product => product_int,
                done => done_int
              );
  
  clk_int <= not clk_int after 5 ns;
  start_int <= '0', '1' after 30 ns, '0' after 40 ns, '1' after 140 ns, '0' after 260 ns;
  multiplicand_int <= "111", "100" after 140 ns, "111" after 250 ns;
  multiplier_int <= "101", "001" after 140 ns, "100" after 250 ns;            

end Behavioral;