library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity tb_hysterese is
end tb_hysterese;
 
architecture tb of tb_hysterese is

component hysterese is port(
	Spannungslimit   : in  std_logic_vector(7 downto 0);
	HysVariable      : in  std_logic_vector(7 downto 0);
	ADC_WERT         : in  std_logic_vector(7 downto 0);
	Portpin          : out std_logic);
end component;

signal Spannungslimit: std_logic_vector(7 downto 0):=std_logic_vector(to_unsigned(200,8));
signal HysVariable   : std_logic_vector(7 downto 0):=std_logic_vector(to_unsigned(40,8));
signal ADC_WERT      : std_logic_vector(7 downto 0):=(others => '0');
signal Portpin       : std_logic:='0';
signal dir           : std_logic:='0';

begin

process begin
	wait for 10 ns;
	if dir = '0' then
		ADC_WERT <= std_logic_vector(unsigned(ADC_WERT) +1);
		if unsigned(ADC_WERT) = 254 then
			dir <= '1';
		end if;
	else
		ADC_WERT <= std_logic_vector(unsigned(ADC_WERT) -1);
		if unsigned(ADC_WERT) = 1 then
			dir <= '0';
		end if;
	end if;
end process;

UUT: hysterese port map(
	Spannungslimit   => Spannungslimit,
	HysVariable      => HysVariable,
	ADC_WERT         => ADC_WERT,
	Portpin          => Portpin);

end;