#include "ethernet.h"
#include "coretimer.h"


//netsh interface ipv4 add neighbors "Ethernet" 10.0.0.231 00-1e-c0-c6-de-2e
// eth.src == 00:1e:c0:c6:de:2e || eth.dst == 00:1e:c0:c6:de:2e


/*
 ETHCON1		0x00308180
ETHCON2		0x00000600

ETHRXST		0x0000A844

ETHRXFC		0x0000005B
ETHRXWM		0x00020000
ETHIEN		0x0000608F
ETHIRQ		0x00000200
ETHSTAT		0x00000080

EMAC1CFG1	0x00000080
EMAC1CFG2	0x000040B2
EMAC1IPT	0x00000012
EMAC1IPGR	0x00000C12
EMAC1CLRT	0x0000370F
EMAC1MAXF	0x00000600
EMAC1SUPP	0x00001000

EMAC1MCFG	0x00000020

EMAC1MADR	0x00000100

*/

typedef union
{
    struct
    {
        uint32_t            : 7;
        uint32_t EOWN       : 1;
        uint32_t NPV        : 1;
        uint32_t            : 7;        //defined by user
        uint32_t BYTE_COUNT : 11;
        uint32_t            : 3;
        uint32_t EOP        : 1;
        uint32_t SOP        : 1;
    };
    uint32_t            w;
}ETH_Buffer_Offset_0;  // descriptor header

typedef union
{
    struct
    {
        uint32_t PKT_CHECKSUM   : 16;
        uint32_t                : 8;
        uint32_t RXF_RSV        : 8;
    };
    uint32_t            w;
}ETH_Buffer_Offset_8;  // descriptor header

typedef struct
{
    ETH_Buffer_Offset_0     HEADER;        // header
    uint8_t*                DATA_BUFFER_ADDRESS;    // data buffer address
    ETH_Buffer_Offset_8     STAT;       // TX/RX packet status
    uint32_t                RSV;
    uint32_t*               NEXT_ED;    // next descriptor (hdr.NPV==1);
} ETH_Buffer;   // hardware TX/RX descriptor (linked).

uint8_t RX_Data_Buffer[2][1536];
ETH_Buffer RX_Header[2];

uint8_t TX_Data_Buffer[2][1536];
ETH_Buffer TX_Header[2];

void ethernet_init(){
    
    RX_Header[0].HEADER.EOWN = 1;
    RX_Header[0].HEADER.NPV = 1;
    RX_Header[0].DATA_BUFFER_ADDRESS = &RX_Data_Buffer[0][0];
    RX_Header[0].NEXT_ED = (uint32_t*)&RX_Header[1];
    
    RX_Header[1].HEADER.EOWN = 1;
    RX_Header[1].HEADER.NPV = 1;
    RX_Header[1].DATA_BUFFER_ADDRESS = &RX_Data_Buffer[1][0];
    RX_Header[1].NEXT_ED = (uint32_t*)&RX_Header[0];
    
    TX_Header[0].HEADER.EOWN = 1;
    TX_Header[0].HEADER.NPV = 1;
    TX_Header[0].DATA_BUFFER_ADDRESS = &TX_Data_Buffer[0][0];
    TX_Header[0].NEXT_ED = (uint32_t*)&TX_Header[1];
    
    TX_Header[1].HEADER.EOWN = 1;
    TX_Header[1].HEADER.NPV = 1;
    TX_Header[1].DATA_BUFFER_ADDRESS = &TX_Data_Buffer[1][0];
    TX_Header[1].NEXT_ED = (uint32_t*)&TX_Header[0];
    
    
    //nRST Pin Low -> Reset
    LATAbits.LATA0 = 1; //Init High
    TRISAbits.TRISA0 = 0; //Init Out
    
    DelayMs(10);
    
    ETHCON1bits.ON = 1;
    
    EMAC1CFG1bits.SOFTRESET = 0;
    EMAC1CFG1bits.PASSALL = 1;
    
    EMAC1CFG1 = 0x00000080;
    
    
    EMAC1CFG1 = 0x01;       //test
    
    
    ETHCON1bits.AUTOFC = 1; //Automatic Flow Control bit
    ETHCON1bits.PTV = 0x0030;
    
    ETHCON2 = 0x00000600;   //RX data Buffer size for descriptors is 1536 bytes
    
    
    ETHTXST = ((uint32_t)TX_Header & 0x1fffffff); //Starting Address of First Transmit Descriptor
    
    ETHRXST = ((uint32_t)RX_Header & 0x1fffffff); //Starting Address of First Receive Descriptor
    
    //ETHRXFC = 0x0000005B;// filtering
    
    ETHRXWMbits.RXFWM = 2;
    ETHRXWMbits.RXEWM = 0;
    
    EMAC1MAXF = 0x600;
    
    EMAC1SUPPbits.SPEEDRMII = 1; //100mbit
        
    ETHCON1bits.RXEN = 1;   //Receive Enable bit
    
}