library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity multiply is

    port 

    (

        clk          : in  std_logic;

        start        : in  std_logic;

        multiplicand : in  std_logic_vector(2 downto 0);

        multiplier   : in  std_logic_vector(2 downto 0);

        --

        product      : out std_logic_vector(5 downto 0);

        done         : out std_logic

    );

end entity multiply;

architecture rtl of multiply is

    type state_type is (IDLE, ADD, SHIFT, FINISH);

    signal state, next_state            : state_type;

    --

    signal count            : natural range 0 to 2;

    signal ma               : unsigned(2 downto 0);

    signal mb               : unsigned(5 downto 0);

    signal result           : unsigned(5 downto 0);
    
    
    signal count_next       : natural range 0 to 2;
    
    signal ma_next  : unsigned (2 downto 0);
    signal mb_next  : unsigned (5 downto 0);
    signal result_next : unsigned(5 downto 0);
    
    signal reg1, reg2 : std_logic;
    signal edge : std_logic;
    
begin

sync_proc :  process(clk)
begin
    if rising_edge(clk) then
        state <= next_state;
        count <= count_next;
        ma <= ma_next;
        mb <= mb_next;
        result <= result_next;
        reg1 <= start;
        reg2 <= reg1;

    end if;
end process;

edge <= reg1 and not reg2;
next_state_decode : process(all)--(state, start, count, result, ma, mb)

    begin

        next_state <= state;               
        ma_next <= ma;
        mb_next <= mb;
        result_next <= result;
        count_next <= count;
        
        
        -- default
        done    <= '0';

        case state is

            when IDLE =>

                if edge = '1' then

                    next_state       <= ADD;
                    
                    count_next <= 2; 
                                   
                    ma_next          <= unsigned( multiplicand);

                    mb_next          <= resize( unsigned( multiplier), mb'length);

                    result_next      <= ( others => '0');

                end if;

            when ADD =>
            
              
                
                
                if ma( 0) = '1' then

                    result_next      <= result + mb;
                   
                end if;
                
                next_state           <= SHIFT;

   
     

            when SHIFT =>
                
               
               
                if count > 0 then

                    mb_next          <= shift_left( mb, 1);

                    ma_next          <= shift_right( ma, 1);
                    
                    count_next       <= count - 1;
                    
                    next_state       <= ADD;

                else
                    
                    next_state       <= FINISH;
                                       
                end if;
                    
                    
            when FINISH =>
                
                done        <= '1';

                --product     <= std_logic_vector( result);

                next_state       <= IDLE;
                
                
           when others =>
           
               next_state        <= IDLE;

          
        end case;

    end process;
 product     <= std_logic_vector( result);
end architecture rtl;