library IEEE;
use IEEE.STD_LOGIC_1164.all;



entity top is
  port (clk_i : in std_logic;
--VGA   
        led_o : out std_logic_vector(47 downto 0);
        bcd_i : in std_logic_vector(23 downto 0);
        end top;

        architecture Behavioral of top is
          component seg_coder is
            port (
              a, b, c, d, e, f, g : out std_logic;
              bcd_i : in std_logic );
          end component seg_coder;

          signal s_led : std_logic_vector(47 downto 0);

        begin

          G_7seg : for idx in 0 to 5 Generate

            seg_coder_1 : entity work.seg_coder
              port map (
                a => s_led(8*idx + 0),
                b => s_led(8*idx + 1),
                c => s_led(8*idx + 2),
                d => s_led(8*idx + 3),
                e => s_led(8*idx + 4),
                f => s_led(8*idx + 5),
                g => s_led(8*idx + 6),
                bcd_i => bcd_i(4*idx+3 downto 4*idx));
            S_LED(8*IDX + 7) <= '0'  -- DECIMAL POINT
          end generate;


          P_output_buffer : process(clk_i)
          begin
            if rising_edge(clk_i) then
              led_o <= s_led;
            end if;
          end process P_output_buffer;
        end Behavioral;
---
        library IEEE;
        use IEEE.STD_LOGIC_1164.all;

        entity seg_coder is
          port (
            a, b, c, d, e, f, g : out std_logic;
            bcd_i : in std_logic);
        end entity seg_coder;

        architecture rtl of seg_coder is

        begin
          process (bcd_i)

          begin

            case bcd_i is
              when "0000" => a <= '1'; b <= '1'; c <= '1'; d <= '1'; e <= '1'; f <= '1'; g <= '0';
              when "0001" => a <= '0'; b <= '1'; c <= '1'; d <= '0'; e <= '0'; f <= '0'; g <= '0';
              when "0010" => a <= '1'; b <= '1'; c <= '0'; d <= '1'; e <= '1'; f <= '0'; g <= '1';
              when "0011" => a <= '1'; b <= '1'; c <= '1'; d <= '1'; e <= '0'; f <= '0'; g <= '1';
              when "0100" => a <= '0'; b <= '1'; c <= '1'; d <= '0'; e <= '0'; f <= '1'; g <= '1';
              when "0101" => a <= '1'; b <= '0'; c <= '1'; d <= '1'; e <= '0'; f <= '1'; g <= '1';
              when "0110" => a <= '1'; b <= '0'; c <= '1'; d <= '1'; e <= '1'; f <= '1'; g <= '1';
              when "0111" => a <= '1'; b <= '1'; c <= '1'; d <= '0'; e <= '0'; f <= '0'; g <= '0';
              when "1000" => a <= '1'; b <= '1'; c <= '1'; d <= '1'; e <= '1'; f <= '1'; g <= '1';
              when "1001" => a <= '1'; b <= '1'; c <= '1'; d <= '1'; e <= '0'; f <= '1'; g <= '1';
              when others => a <= '0'; b <= '0'; c <= '0'; d <= '0'; e <= '0'; f <= '0'; g <= '1';
            end case;
          end process;


        end architecture;