; macro_defs.inc
; 01.12.2021
; Defs fuer alles
#ifndef _MACRO_DEFS_
#define _MACRO_DEFS_ 

#ifndef BYTE_H
	#define BYTE_H
	#define byte5(x) (x>>32)&0xff
	#define byte6(x) (x>>40)&0xff
	#define byte7(x) (x>>48)&0xff
	#define byte8(x) (x>>56)&0xff
#endif /* BYTE_H */ 

#ifndef TEMP
	#define temp	r16
	#define templ	r16
	#define temph	r17
	#define temp0	r16
	#define temp1	r17
	#define temp2	r18
	#define temp3	r19
	#define CZ		r24
	#define czl 	r24
	#define czh 	r25
#endif /* TEMP */

; fuer Haupoperand-Register
#ifndef TEMP_MPR_H
	#define CZ_mpr 		r24_mpr
	#define czl_mpr 	r24_mpr
	#define czh_mpr 	r25_mpr
	#define temp_mpr 	r20_mpr
	#define templ_mpr 	r20_mpr
	#define temph_mpr 	r21_mpr
	#define temp0_mpr 	r20_mpr
	#define temp1_mpr 	r21_mpr
	#define temp2_mpr 	r22_mpr
	#define temp3_mpr 	r23_mpr
#endif /* TEMP_MPR_H */

; fuer 1.Operand-Register
#ifndef TEMP_A_H
	#define CZ_a 		r24_a
	#define czl_a 		r24_a
	#define czh_a 		r25_a
	#define temp_a 		r20_a
	#define templ_a 	r20_a
	#define temph_a 	r21_a
	#define temp0_a 	r20_a
	#define temp1_a 	r21_a
	#define temp2_a 	r22_a
	#define temp3_a 	r23_a
#endif /* TEMP_A_H */

; fuer 2.Operand-Register
#ifndef TEMP_B_H
	#define CZ_b 		r24_b
	#define czl_b 		r24_b
	#define czh_b 		r25_b
	#define temp_b 		r20_b
	#define templ_b 	r20_b
	#define temph_b 	r21_b
	#define temp0_b 	r20_b
	#define temp1_b 	r21_b
	#define temp2_b 	r22_b
	#define temp3_b 	r23_b
#endif /* TEMP_B_H */

; Fuer Unterschied zwischen unteren und oberen Register, auch bei mehr-Bytes OP
#ifndef OBEREREG
	#define OBEREREG r16_mpr||r17_mpr||r18_mpr||r19_mpr||r20_mpr||r21_mpr||r22_mpr||r23_mpr||r24_mpr||r25_mpr||r26_mpr||r27_mpr||r28_mpr||r29_mpr||r30_mpr||r31_mpr||X_mpr||xl_mpr||xh_mpr||Y_mpr||yl_mpr||yh_mpr||Z_mpr||zl_mpr||zh_mpr

	#define REG16 r0_mpr||r1_mpr||r2_mpr||r3_mpr||r4_mpr||r5_mpr||r6_mpr||r7_mpr||r8_mpr||r9_mpr||r10_mpr||r11_mpr||r12_mpr||r13_mpr||r14_mpr||r15_mpr||r16_mpr||r17_mpr||r18_mpr||r19_mpr||r20_mpr||r21_mpr||r22_mpr||r23_mpr||r24_mpr||r25_mpr||r26_mpr||r27_mpr||r28_mpr||r29_mpr||r30_mpr||X_mpr||xl_mpr||xh_mpr||Y_mpr||yl_mpr||yh_mpr||Z_mpr||zl_mpr
	#define REG24 r0_mpr||r1_mpr||r2_mpr||r3_mpr||r4_mpr||r5_mpr||r6_mpr||r7_mpr||r8_mpr||r9_mpr||r10_mpr||r11_mpr||r12_mpr||r13_mpr||r14_mpr||r15_mpr||r16_mpr||r17_mpr||r18_mpr||r19_mpr||r20_mpr||r21_mpr||r22_mpr||r23_mpr||r24_mpr||r25_mpr||r26_mpr||r27_mpr||r28_mpr||r29_mpr||X_mpr||xl_mpr||xh_mpr||Y_mpr||yl_mpr||yh_mpr
	#define REG32 r0_mpr||r1_mpr||r2_mpr||r3_mpr||r4_mpr||r5_mpr||r6_mpr||r7_mpr||r8_mpr||r9_mpr||r10_mpr||r11_mpr||r12_mpr||r13_mpr||r14_mpr||r15_mpr||r16_mpr||r17_mpr||r18_mpr||r19_mpr||r20_mpr||r21_mpr||r22_mpr||r23_mpr||r24_mpr||r25_mpr||r26_mpr||r27_mpr||r28_mpr||X_mpr||xl_mpr||xh_mpr||Y_mpr||yl_mpr
	#define REG40 r0_mpr||r1_mpr||r2_mpr||r3_mpr||r4_mpr||r5_mpr||r6_mpr||r7_mpr||r8_mpr||r9_mpr||r10_mpr||r11_mpr||r12_mpr||r13_mpr||r14_mpr||r15_mpr||r16_mpr||r17_mpr||r18_mpr||r19_mpr||r20_mpr||r21_mpr||r22_mpr||r23_mpr||r24_mpr||r25_mpr||r26_mpr||r27_mpr||X_mpr||xl_mpr||xh_mpr
	#define REG48 r0_mpr||r1_mpr||r2_mpr||r3_mpr||r4_mpr||r5_mpr||r6_mpr||r7_mpr||r8_mpr||r9_mpr||r10_mpr||r11_mpr||r12_mpr||r13_mpr||r14_mpr||r15_mpr||r16_mpr||r17_mpr||r18_mpr||r19_mpr||r20_mpr||r21_mpr||r22_mpr||r23_mpr||r24_mpr||r25_mpr||r26_mpr||X_mpr||xl_mpr
	#define REG56 r0_mpr||r1_mpr||r2_mpr||r3_mpr||r4_mpr||r5_mpr||r6_mpr||r7_mpr||r8_mpr||r9_mpr||r10_mpr||r11_mpr||r12_mpr||r13_mpr||r14_mpr||r15_mpr||r16_mpr||r17_mpr||r18_mpr||r19_mpr||r20_mpr||r21_mpr||r22_mpr||r23_mpr||r24_mpr||r25_mpr
	#define REG64 r0_mpr||r1_mpr||r2_mpr||r3_mpr||r4_mpr||r5_mpr||r6_mpr||r7_mpr||r8_mpr||r9_mpr||r10_mpr||r11_mpr||r12_mpr||r13_mpr||r14_mpr||r15_mpr||r16_mpr||r17_mpr||r18_mpr||r19_mpr||r20_mpr||r21_mpr||r22_mpr||r23_mpr||r24_mpr
#endif /* OBEREREG */
#ifndef OBEREREG_XX
	#define OBEREREG_16 r16_mpr||r17_mpr||r18_mpr||r19_mpr||r20_mpr||r21_mpr||r22_mpr||r23_mpr||r24_mpr||r25_mpr||r26_mpr||r27_mpr||r28_mpr||r29_mpr||r30_mpr||X_mpr||xl_mpr||xh_mpr||Y_mpr||yl_mpr||yh_mpr||Z_mpr||zl_mpr
	#define OBEREREG_24 r16_mpr||r17_mpr||r18_mpr||r19_mpr||r20_mpr||r21_mpr||r22_mpr||r23_mpr||r24_mpr||r25_mpr||r26_mpr||r27_mpr||r28_mpr||r29_mpr||X_mpr||xl_mpr||xh_mpr||Y_mpr||yl_mpr||yh_mpr
	#define OBEREREG_32 r16_mpr||r17_mpr||r18_mpr||r19_mpr||r20_mpr||r21_mpr||r22_mpr||r23_mpr||r24_mpr||r25_mpr||r26_mpr||r27_mpr||r28_mpr||X_mpr||xl_mpr||xh_mpr||Y_mpr||yl_mpr
	#define OBEREREG_40 r16_mpr||r17_mpr||r18_mpr||r19_mpr||r20_mpr||r21_mpr||r22_mpr||r23_mpr||r24_mpr||r25_mpr||r26_mpr||r27_mpr||X_mpr||xl_mpr||xh_mpr
	#define OBEREREG_48 r16_mpr||r17_mpr||r18_mpr||r19_mpr||r20_mpr||r21_mpr||r22_mpr||r23_mpr||r24_mpr||r25_mpr||r26_mpr||X_mpr||xl_mpr
	#define OBEREREG_56 r16_mpr||r17_mpr||r18_mpr||r19_mpr||r20_mpr||r21_mpr||r22_mpr||r23_mpr||r24_mpr||r25_mpr
	#define OBEREREG_64 r16_mpr||r17_mpr||r18_mpr||r19_mpr||r20_mpr||r21_mpr||r22_mpr||r23_mpr||r24_mpr
#endif /* OBEREREG_XX */ 
#ifndef UNTEREREG_XX
	#define UNTEREREG_16 r0_mpr||r1_mpr||r2_mpr||r3_mpr||r4_mpr||r5_mpr||r6_mpr||r7_mpr||r8_mpr||r9_mpr||r10_mpr||r11_mpr||r12_mpr||r13_mpr||r14_mpr
	#define UNTEREREG_24 r0_mpr||r1_mpr||r2_mpr||r3_mpr||r4_mpr||r5_mpr||r6_mpr||r7_mpr||r8_mpr||r9_mpr||r10_mpr||r11_mpr||r12_mpr||r13_mpr
	#define UNTEREREG_32 r0_mpr||r1_mpr||r2_mpr||r3_mpr||r4_mpr||r5_mpr||r6_mpr||r7_mpr||r8_mpr||r9_mpr||r10_mpr||r11_mpr||r12_mpr
	#define UNTEREREG_40 r0_mpr||r1_mpr||r2_mpr||r3_mpr||r4_mpr||r5_mpr||r6_mpr||r7_mpr||r8_mpr||r9_mpr||r10_mpr||r11_mpr
	#define UNTEREREG_48 r0_mpr||r1_mpr||r2_mpr||r3_mpr||r4_mpr||r5_mpr||r6_mpr||r7_mpr||r8_mpr||r9_mpr||r10_mpr
	#define UNTEREREG_56 r0_mpr||r1_mpr||r2_mpr||r3_mpr||r4_mpr||r5_mpr||r6_mpr||r7_mpr||r8_mpr||r9_mpr
	#define UNTEREREG_64 r0_mpr||r1_mpr||r2_mpr||r3_mpr||r4_mpr||r5_mpr||r6_mpr||r7_mpr||r8_mpr
#endif /* UNTEREREG_XX */

; Fuer Kontrolle auf zulaessige Reg
#ifndef REGAB
#define REGAB
	#define REG16A r0_a||r1_a||r2_a||r3_a||r4_a||r5_a||r6_a||r7_a||r8_a||r9_a||r10_a||r11_a||r12_a||r13_a||r14_a||r15_a||r16_a||r17_a||r18_a||r19_a||r20_a||r21_a||r22_a||r23_a||r24_a||r25_a||r26_a||r27_a||r28_a||r29_a||r30_a||X_a||xl_a||xh_a||Y_a||yl_a||yh_a||Z_a||zl_a
	#define REG24A r0_a||r1_a||r2_a||r3_a||r4_a||r5_a||r6_a||r7_a||r8_a||r9_a||r10_a||r11_a||r12_a||r13_a||r14_a||r15_a||r16_a||r17_a||r18_a||r19_a||r20_a||r21_a||r22_a||r23_a||r24_a||r25_a||r26_a||r27_a||r28_a||r29_a||X_a||xl_a||xh_a||Y_a||yl_a||yh_a
	#define REG32A r0_a||r1_a||r2_a||r3_a||r4_a||r5_a||r6_a||r7_a||r8_a||r9_a||r10_a||r11_a||r12_a||r13_a||r14_a||r15_a||r16_a||r17_a||r18_a||r19_a||r20_a||r21_a||r22_a||r23_a||r24_a||r25_a||r26_a||r27_a||r28_a||X_a||xl_a||xh_a||Y_a||yl_a
	#define REG40A r0_a||r1_a||r2_a||r3_a||r4_a||r5_a||r6_a||r7_a||r8_a||r9_a||r10_a||r11_a||r12_a||r13_a||r14_a||r15_a||r16_a||r17_a||r18_a||r19_a||r20_a||r21_a||r22_a||r23_a||r24_a||r25_a||r26_a||r27_a||X_a||xl_a||xh_a
	#define REG48A r0_a||r1_a||r2_a||r3_a||r4_a||r5_a||r6_a||r7_a||r8_a||r9_a||r10_a||r11_a||r12_a||r13_a||r14_a||r15_a||r16_a||r17_a||r18_a||r19_a||r20_a||r21_a||r22_a||r23_a||r24_a||r25_a||r26_a||X_a||xl_a
	#define REG56A r0_a||r1_a||r2_a||r3_a||r4_a||r5_a||r6_a||r7_a||r8_a||r9_a||r10_a||r11_a||r12_a||r13_a||r14_a||r15_a||r16_a||r17_a||r18_a||r19_a||r20_a||r21_a||r22_a||r23_a||r24_a||r25_a
	#define REG64A r0_a||r1_a||r2_a||r3_a||r4_a||r5_a||r6_a||r7_a||r8_a||r9_a||r10_a||r11_a||r12_a||r13_a||r14_a||r15_a||r16_a||r17_a||r18_a||r19_a||r20_a||r21_a||r22_a||r23_a||r24_a

	#define REG16B r0_b||r1_b||r2_b||r3_b||r4_b||r5_b||r6_b||r7_b||r8_b||r9_b||r10_b||r11_b||r12_b||r13_b||r14_b||r15_b||r16_b||r17_b||r18_b||r19_b||r20_b||r21_b||r22_b||r23_b||r24_b||r25_b||r26_b||r27_b||r28_b||r29_b||r30_b||X_b||xl_b||xh_b||Y_b||yl_b||yh_b||Z_b||zl_b
	#define REG24B r0_b||r1_b||r2_b||r3_b||r4_b||r5_b||r6_b||r7_b||r8_b||r9_b||r10_b||r11_b||r12_b||r13_b||r14_b||r15_b||r16_b||r17_b||r18_b||r19_b||r20_b||r21_b||r22_b||r23_b||r24_b||r25_b||r26_b||r27_b||r28_b||r29_b||X_b||xl_b||xh_b||Y_b||yl_b||yh_b
	#define REG32B r0_b||r1_b||r2_b||r3_b||r4_b||r5_b||r6_b||r7_b||r8_b||r9_b||r10_b||r11_b||r12_b||r13_b||r14_b||r15_b||r16_b||r17_b||r18_b||r19_b||r20_b||r21_b||r22_b||r23_b||r24_b||r25_b||r26_b||r27_b||r28_b||X_b||xl_b||xh_b||Y_b||yl_b
	#define REG40B r0_b||r1_b||r2_b||r3_b||r4_b||r5_b||r6_b||r7_b||r8_b||r9_b||r10_b||r11_b||r12_b||r13_b||r14_b||r15_b||r16_b||r17_b||r18_b||r19_b||r20_b||r21_b||r22_b||r23_b||r24_b||r25_b||r26_b||r27_b||X_b||xl_b||xh_b
	#define REG48B r0_b||r1_b||r2_b||r3_b||r4_b||r5_b||r6_b||r7_b||r8_b||r9_b||r10_b||r11_b||r12_b||r13_b||r14_b||r15_b||r16_b||r17_b||r18_b||r19_b||r20_b||r21_b||r22_b||r23_b||r24_b||r25_b||r26_b||X_b||xl_b
	#define REG56B r0_b||r1_b||r2_b||r3_b||r4_b||r5_b||r6_b||r7_b||r8_b||r9_b||r10_b||r11_b||r12_b||r13_b||r14_b||r15_b||r16_b||r17_b||r18_b||r19_b||r20_b||r21_b||r22_b||r23_b||r24_b||r25_b
	#define REG64B r0_b||r1_b||r2_b||r3_b||r4_b||r5_b||r6_b||r7_b||r8_b||r9_b||r10_b||r11_b||r12_b||r13_b||r14_b||r15_b||r16_b||r17_b||r18_b||r19_b||r20_b||r21_b||r22_b||r23_b||r24_b
	
	#define REG16AB (REG16A) && (REG16B)
	#define REG24AB (REG24A) && (REG24B)
	#define REG32AB (REG32A) && (REG32B)
	#define REG40AB (REG40A) && (REG40B)
	#define REG48AB (REG48A) && (REG48B)
	#define REG56AB (REG56A) && (REG56B)
	#define REG64AB (REG64A) && (REG64B)
#endif /* REGAB */

; Fuer Kontrolle auf zulaessige Reg fuer lpm (nur bis einschl.r30, r31 nicht bedient)
#ifndef REGLPM
#define REGLPM
	#define REG8L r0_a||r1_a||r2_a||r3_a||r4_a||r5_a||r6_a||r7_a||r8_a||r9_a||r10_a||r11_a||r12_a||r13_a||r14_a||r15_a||r16_a||r17_a||r18_a||r19_a||r20_a||r21_a||r22_a||r23_a||r24_a||r25_a||r26_a||r27_a||r28_a||r29_a||r30_a||X_a||xl_a||xh_a||Y_a||yl_a||yh_a||Z_a||zl_a
	#define REG16L r0_a||r1_a||r2_a||r3_a||r4_a||r5_a||r6_a||r7_a||r8_a||r9_a||r10_a||r11_a||r12_a||r13_a||r14_a||r15_a||r16_a||r17_a||r18_a||r19_a||r20_a||r21_a||r22_a||r23_a||r24_a||r25_a||r26_a||r27_a||r28_a||r29_a||X_a||xl_a||xh_a||Y_a||yl_a||yh_a
	#define REG24L r0_a||r1_a||r2_a||r3_a||r4_a||r5_a||r6_a||r7_a||r8_a||r9_a||r10_a||r11_a||r12_a||r13_a||r14_a||r15_a||r16_a||r17_a||r18_a||r19_a||r20_a||r21_a||r22_a||r23_a||r24_a||r25_a||r26_a||r27_a||r28_a||X_a||xl_a||xh_a||Y_a||yl_a
	#define REG32L r0_a||r1_a||r2_a||r3_a||r4_a||r5_a||r6_a||r7_a||r8_a||r9_a||r10_a||r11_a||r12_a||r13_a||r14_a||r15_a||r16_a||r17_a||r18_a||r19_a||r20_a||r21_a||r22_a||r23_a||r24_a||r25_a||r26_a||r27_a||X_a||xl_a||xh_a
	#define REG40L r0_a||r1_a||r2_a||r3_a||r4_a||r5_a||r6_a||r7_a||r8_a||r9_a||r10_a||r11_a||r12_a||r13_a||r14_a||r15_a||r16_a||r17_a||r18_a||r19_a||r20_a||r21_a||r22_a||r23_a||r24_a||r25_a||r26_a||X_a||xl_a
	#define REG48L r0_a||r1_a||r2_a||r3_a||r4_a||r5_a||r6_a||r7_a||r8_a||r9_a||r10_a||r11_a||r12_a||r13_a||r14_a||r15_a||r16_a||r17_a||r18_a||r19_a||r20_a||r21_a||r22_a||r23_a||r24_a||r25_a
	#define REG56L r0_a||r1_a||r2_a||r3_a||r4_a||r5_a||r6_a||r7_a||r8_a||r9_a||r10_a||r11_a||r12_a||r13_a||r14_a||r15_a||r16_a||r17_a||r18_a||r19_a||r20_a||r21_a||r22_a||r23_a||r24_a
	#define REG64L r0_a||r1_a||r2_a||r3_a||r4_a||r5_a||r6_a||r7_a||r8_a||r9_a||r10_a||r11_a||r12_a||r13_a||r14_a||r15_a||r16_a||r17_a||r18_a||r19_a||r20_a||r21_a||r22_a||r23_a
#endif /* REGLPM */ 

; fuer Kontrolle gegen gleiche Register
#ifndef REGGLEICH
	#define RGL0 (r0_a && r0_b)
	#define RGL1 (r1_a && r1_b)
	#define RGL2 (r2_a && r2_b)
	#define RGL3 (r3_a && r3_b)
	#define RGL4 (r4_a && r4_b)
	#define RGL5 (r5_a && r5_b)
	#define RGL6 (r6_a && r6_b)
	#define RGL7 (r7_a && r7_b)
	#define RGL8 (r8_a && r8_b)
	#define RGL9 (r9_a && r9_b)
	#define RGL10 (r10_a && r10_b)
	#define RGL11 (r11_a && r11_b)
	#define RGL12 (r12_a && r12_b)
	#define RGL13 (r13_a && r13_b)
	#define RGL14 (r14_a && r14_b)
	#define RGL15 (r15_a && r15_b)
	#define RGL16 (r16_a && r16_b)
	#define RGL17 (r17_a && r17_b)
	#define RGL18 (r18_a && r18_b)
	#define RGL19 (r19_a && r19_b)
	#define RGL20 (r20_a && r20_b)
	#define RGL21 (r21_a && r21_b)
	#define RGL22 (r22_a && r22_b)
	#define RGL23 (r23_a && r23_b)
	#define RGL24 (r24_a && r24_b)
	#define RGL25 (r25_a && r25_b)
	#define RGL26 ((r26_a||X_a||xl_a) && (r26_b||X_b||xl_b))
	#define RGL27 ((r27_a||xh_a) && (r27_b||xh_b))
	#define RGL28 ((r28_a||Y_a||yl_a) && (r28_b|Y_b||yl_b))
	#define RGL29 ((r29_a||yh_a) && (r29_b||yh_b))
	#define RGL30 ((r30_a||Z_a||zl_a) && (r30_b||Z_b||zl_b))
	#define RGL31 ((r31_a||zh_a) && (r31_b||zh_b))
	
	#define REGGLEICH_T0 (RGL0||RGL1||RGL2||RGL3||RGL4||RGL5||RGL6||RGL7||RGL8||RGL9||RGL10||RGL11||RGL12||RGL13||RGL14||RGL15)
	#define REGGLEICH_T1 (RGL16||RGL17||RGL18||RGL19||RGL20||RGL21||RGL22||RGL23||RGL24||RGL25||RGL26||RGL27||RGL28||RGL29||RGL30||RGL31)
	#define REGGLEICH REGGLEICH_T0||REGGLEICH_T0
#endif /* REGGLEICH */

; fuer movw
#ifndef REGW
#define REGW
	#define REG16WA r0_a||r2_a||r4_a||r6_a||r8_a||r10_a||r12_a||r14_a||r16_a||r18_a||r20_a||r22_a||r24_a||r26_a||r28_a||r30_a||X_a||xl_a||Y_a||yl_a||Z_a||zl_a
	#define REG24WA r0_a||r2_a||r4_a||r6_a||r8_a||r10_a||r12_a||r14_a||r16_a||r18_a||r20_a||r22_a||r24_a||r26_a||r28_a||X_a||xl_a||Y_a||yl_a
	#define REG32WA r0_a||r2_a||r4_a||r6_a||r8_a||r10_a||r12_a||r14_a||r16_a||r18_a||r20_a||r22_a||r24_a||r26_a||r28_a||X_a||xl_a||Y_a||yl_a
	#define REG40WA r0_a||r2_a||r4_a||r6_a||r8_a||r10_a||r12_a||r14_a||r16_a||r18_a||r20_a||r22_a||r24_a||r26_a||X_a||xl_a
	#define REG48WA r0_a||r2_a||r4_a||r6_a||r8_a||r10_a||r12_a||r14_a||r16_a||r18_a||r20_a||r22_a||r24_a||r26_a||X_a||xl_a
	#define REG56WA r0_a||r2_a||r4_a||r6_a||r8_a||r10_a||r12_a||r14_a||r16_a||r18_a||r20_a||r22_a||r24_a
	#define REG64WA r0_a||r2_a||r4_a||r6_a||r8_a||r10_a||r12_a||r14_a||r16_a||r18_a||r20_a||r22_a||r24_a

	#define REG16WB r0_b||r2_b||r4_b||r6_b||r8_b||r10_b||r12_b||r14_b||r16_b||r18_b||r20_b||r22_b||r24_b||r26_b||r28_b||r30_b||X_b||xl_b||Y_b||yl_b||Z_b||zl_b
	#define REG24WB r0_b||r2_b||r4_b||r6_b||r8_b||r10_b||r12_b||r14_b||r16_b||r18_b||r20_b||r22_b||r24_b||r26_b||r28_b||X_b||xl_b||Y_b||yl_b
	#define REG32WB r0_b||r2_b||r4_b||r6_b||r8_b||r10_b||r12_b||r14_b||r16_b||r18_b||r20_b||r22_b||r24_b||r26_b||r28_b||X_b||xl_b||Y_b||yl_b
	#define REG40WB r0_b||r2_b||r4_b||r6_b||r8_b||r10_b||r12_b||r14_b||r16_b||r18_b||r20_b||r22_b||r24_b||r26_b||X_b||xl_b
	#define REG48WB r0_b||r2_b||r4_b||r6_b||r8_b||r10_b||r12_b||r14_b||r16_b||r18_b||r20_b||r22_b||r24_b||r26_b||X_b||xl_b
	#define REG56WB r0_b||r2_b||r4_b||r6_b||r8_b||r10_b||r12_b||r14_b||r16_b||r18_b||r20_b||r22_b||r24_b
	#define REG64WB r0_b||r2_b||r4_b||r6_b||r8_b||r10_b||r12_b||r14_b||r16_b||r18_b||r20_b||r22_b||r24_b

	#define REG16W (REG16WA) && (REG16WB)
	#define REG24W (REG24WA) && (REG24WB)
	#define REG32W (REG32WA) && (REG32WB)
	#define REG40W (REG40WA) && (REG40WB)
	#define REG48W (REG48WA) && (REG48WB)
	#define REG56W (REG56WA) && (REG56WB)
	#define REG64W (REG64WA) && (REG64WB)

; Ungeradzaeligen fuer mov24,mov40,mov56
	#define REG24WAU r1_a||r3_a||r5_a||r7_a||r9_a||r11_a||r13_a||r15_a||r17_a||r19_a||r21_a||r23_a||r25_a||r27_a||r29_a||xh_a||yh_a
	#define REG32WAU r1_a||r3_a||r5_a||r7_a||r9_a||r11_a||r13_a||r15_a||r17_a||r19_a||r21_a||r23_a||r25_a||r27_a||xh_a
	#define REG40WAU r1_a||r3_a||r5_a||r7_a||r9_a||r11_a||r13_a||r15_a||r17_a||r19_a||r21_a||r23_a||r25_a||r27_a||xh_a
	#define REG48WAU r1_a||r3_a||r5_a||r7_a||r9_a||r11_a||r13_a||r15_a||r17_a||r19_a||r21_a||r23_a||r25_a
	#define REG56WAU r1_a||r3_a||r5_a||r7_a||r9_a||r11_a||r13_a||r15_a||r17_a||r19_a||r21_a||r23_a||r25_a
	#define REG64WAU r1_a||r3_a||r5_a||r7_a||r9_a||r11_a||r13_a||r15_a||r17_a||r19_a||r21_a||r23_a

	#define REG24WBU r1_b||r3_b||r5_b||r7_b||r9_b||r11_b||r13_b||r15_b||r17_b||r19_b||r21_b||r23_b||r25_b||r27_b||r29_b||xh_b||yh_b
	#define REG32WBU r1_b||r3_b||r5_b||r7_b||r9_b||r11_b||r13_b||r15_b||r17_b||r19_b||r21_b||r23_b||r25_b||r27_b||xh_b
	#define REG40WBU r1_b||r3_b||r5_b||r7_b||r9_b||r11_b||r13_b||r15_b||r17_b||r19_b||r21_b||r23_b||r25_b||r27_b||xh_b
	#define REG48WBU r1_b||r3_b||r5_b||r7_b||r9_b||r11_b||r13_b||r15_b||r17_b||r19_b||r21_b||r23_b||r25_b
	#define REG56WBU r1_b||r3_b||r5_b||r7_b||r9_b||r11_b||r13_b||r15_b||r17_b||r19_b||r21_b||r23_b||r25_b
	#define REG64WBU r1_b||r3_b||r5_b||r7_b||r9_b||r11_b||r13_b||r15_b||r17_b||r19_b||r21_b||r23_b

	#define REG24WU (REG24WAU) && (REG24WBU)
	#define REG32WU (REG32WAU) && (REG32WBU)
	#define REG40WU (REG40WAU) && (REG40WBU)
	#define REG48WU (REG48WAU) && (REG48WBU)
	#define REG56WU (REG56WAU) && (REG56WBU)
	#define REG64WU (REG64WAU) && (REG64WBU)

#endif /* REGW */


#ifndef _SETR_
#define _SETR_

.macro setr16	; fuer 1 Byte, wo nur zwischen r0-r15 und r16-r31 zu unterscheiden ist
	.set r16_mpr = 0
	.set r17_mpr = 0
	.set r18_mpr = 0
	.set r19_mpr = 0
	.set r20_mpr = 0
	.set r21_mpr = 0
	.set r22_mpr = 0
	.set r23_mpr = 0
	.set r24_mpr = 0
	.set r25_mpr = 0
	.set r26_mpr = 0
	.set r27_mpr = 0
	.set r28_mpr = 0
	.set r29_mpr = 0
	.set r30_mpr = 0
	.set r31_mpr = 0
	.set X_mpr = 0
	.set xl_mpr = 0
	.set xh_mpr = 0
	.set Y_mpr = 0
	.set yl_mpr = 0
	.set yh_mpr = 0
	.set Z_mpr = 0
	.set zl_mpr = 0
	.set zh_mpr = 0
.endm

.macro setr				; fuer mehrere Byte, wo die Register einzeln zu behandeln sind
	.set r0_mpr = 0
	.set r1_mpr = 0
	.set r2_mpr = 0
	.set r3_mpr = 0
	.set r4_mpr = 0
	.set r5_mpr = 0
	.set r6_mpr = 0
	.set r7_mpr = 0
	.set r8_mpr = 0
	.set r9_mpr = 0
	.set r10_mpr = 0
	.set r11_mpr = 0
	.set r12_mpr = 0
	.set r13_mpr = 0
	.set r14_mpr = 0
	.set r15_mpr = 0
	.set r16_mpr = 0
	.set r17_mpr = 0
	.set r18_mpr = 0
	.set r19_mpr = 0
	.set r20_mpr = 0
	.set r21_mpr = 0
	.set r22_mpr = 0
	.set r23_mpr = 0
	.set r24_mpr = 0
	.set r25_mpr = 0
	.set r26_mpr = 0
	.set r27_mpr = 0
	.set r28_mpr = 0
	.set r29_mpr = 0
	.set r30_mpr = 0
	.set r31_mpr = 0
	.set X_mpr = 0
	.set xl_mpr = 0
	.set xh_mpr = 0
	.set Y_mpr = 0
	.set yl_mpr = 0
	.set yh_mpr = 0
	.set Z_mpr = 0
	.set zl_mpr = 0
	.set zh_mpr = 0
.endm

.macro setr_a	; 1.Operand. 
; fuer mehrere Byte, wo die Register einzeln zu behandeln sind
	.set r0_a = 0
	.set r1_a = 0
	.set r2_a = 0
	.set r3_a = 0
	.set r4_a = 0
	.set r5_a = 0
	.set r6_a = 0
	.set r7_a = 0
	.set r8_a = 0
	.set r9_a = 0
	.set r10_a = 0
	.set r11_a = 0
	.set r12_a = 0
	.set r13_a = 0
	.set r14_a = 0
	.set r15_a = 0
	.set r16_a = 0
	.set r17_a = 0
	.set r18_a = 0
	.set r19_a = 0
	.set r20_a = 0
	.set r21_a = 0
	.set r22_a = 0
	.set r23_a = 0
	.set r24_a = 0
	.set r25_a = 0
	.set r26_a = 0
	.set r27_a = 0
	.set r28_a = 0
	.set r29_a = 0
	.set r30_a = 0
	.set r31_a = 0
	.set X_a = 0
	.set xl_a = 0
	.set xh_a = 0
	.set Y_a = 0
	.set yl_a = 0
	.set yh_a = 0
	.set Z_a = 0
	.set zl_a = 0
	.set zh_a = 0
.endm

.macro setr_b	; 2.Operand. 
; fuer mehrere Byte, wo die Register einzeln zu behandeln sind
	.set r0_b = 0
	.set r1_b = 0
	.set r2_b = 0
	.set r3_b = 0
	.set r4_b = 0
	.set r5_b = 0
	.set r6_b = 0
	.set r7_b = 0
	.set r8_b = 0
	.set r9_b = 0
	.set r10_b = 0
	.set r11_b = 0
	.set r12_b = 0
	.set r13_b = 0
	.set r14_b = 0
	.set r15_b = 0
	.set r16_b = 0
	.set r17_b = 0
	.set r18_b = 0
	.set r19_b = 0
	.set r20_b = 0
	.set r21_b = 0
	.set r22_b = 0
	.set r23_b = 0
	.set r24_b = 0
	.set r25_b = 0
	.set r26_b = 0
	.set r27_b = 0
	.set r28_b = 0
	.set r29_b = 0
	.set r30_b = 0
	.set r31_b = 0
	.set X_b = 0
	.set xl_b = 0
	.set xh_b = 0
	.set Y_b = 0
	.set yl_b = 0
	.set yh_b = 0
	.set Z_b = 0
	.set zl_b = 0
	.set zh_b = 0
.endm

; Diese Macros sind eingefuehrt, um als temporare obere Register verschiedene
; Register waehlen zu koennen.
.macro setwork
	.set r16_w = 0
	.set r17_w = 0
	.set r18_w = 0
	.set r19_w = 0
	.set r20_w = 0
	.set r21_w = 0
	.set r22_w = 0
	.set r23_w = 0
	.set r24_w = 0
	.set r25_w = 0
	.set r26_w = 0
	.set r27_w = 0
	.set r28_w = 0
	.set r29_w = 0
	.set r30_w = 0
	.set r31_w = 0
.endm

.macro work16
	setwork
	.set r16_w = 1
.endm

.macro work17
	setwork
	.set r17_w = 1
.endm

.macro work18
	setwork
	.set r18_w = 1
.endm

.macro work19
	setwork
	.set r19_w = 1
.endm

.macro work20
	setwork
	.set r20_w = 1
.endm

.macro work21
	setwork
	.set r21_w = 1
.endm
.macro work22
	setwork
	.set r22_w = 1
.endm

.macro work23
	setwork
	.set r23_w = 1
.endm

.macro work24
	setwork
	.set r24_w = 1
.endm

.macro work25
	setwork
	.set r25_w = 1
.endm

.macro work26
	setwork
	.set r26_w = 1
.endm

.macro work27
	setwork
	.set r27_w = 1
.endm

.macro work28
	setwork
	.set r28_w = 1
.endm

.macro work29
	setwork
	.set r29_w = 1
.endm

.macro work30
	setwork
	.set r30_w = 1
.endm

.macro work31
	setwork
	.set r31_w = 1
.endm

; Diese Macros sind eingefuehrt, um als Pufferregister verschiedene
; Register waehlen zu koennen.
.macro setpuff
	.set r0_p = 0
	.set r1_p = 0
	.set r2_p = 0
	.set r3_p = 0
	.set r4_p = 0
	.set r5_p = 0
	.set r6_p = 0
	.set r7_p = 0
	.set r8_p = 0
	.set r9_p = 0
	.set r10_p = 0
	.set r11_p = 0
	.set r12_p = 0
	.set r13_p = 0
	.set r14_p = 0
	.set r15_p = 0
	.set r16_p = 0
	.set r17_p = 0
	.set r18_p = 0
	.set r19_p = 0
	.set r20_p = 0
	.set r21_p = 0
	.set r22_p = 0
	.set r23_p = 0
	.set r24_p = 0
	.set r25_p = 0
	.set r26_p = 0
	.set r27_p = 0
	.set r28_p = 0
	.set r29_p = 0
	.set r30_p = 0
	.set r31_p = 0
.endm

.macro puff0
	setpuff
	.set r0_p = 1
.endm

.macro puff1
	setpuff
	.set r1_p = 1
.endm

.macro puff2
	setpuff
	.set r2_p = 1
.endm

.macro puff3
	setpuff
	.set r3_p = 1
.endm

.macro puff4
	setpuff
	.set r4_p = 1
.endm

.macro puff5
	setpuff
	.set r5_p = 1
.endm

.macro puff6
	setpuff
	.set r6_p = 1
.endm

.macro puff7
	setpuff
	.set r7_p = 1
.endm

.macro puff8
	setpuff
	.set r8_p = 1
.endm

.macro puff9
	setpuff
	.set r9_p = 1
.endm

.macro puff10
	setpuff
	.set r10_p = 1
.endm

.macro puff11
	setpuff
	.set r11_p = 1
.endm

.macro puff12
	setpuff
	.set r12_p = 1
.endm

.macro puff13
	setpuff
	.set r13_p = 1
.endm

.macro puff14
	setpuff
	.set r14_p = 1
.endm

.macro puff15
	setpuff
	.set r15_p = 1
.endm

.macro puff16
	setpuff
	.set r16_p = 1
.endm

.macro puff17
	setpuff
	.set r17_p = 1
.endm

.macro puff18
	setpuff
	.set r18_p = 1
.endm

.macro puff19
	setpuff
	.set r19_p = 1
.endm

.macro puff20
	setpuff
	.set r20_p = 1
.endm

.macro puff21
	setpuff
	.set r21_p = 1
.endm

.macro puff22
	setpuff
	.set r22_p = 1
.endm

.macro puff23
	setpuff
	.set r23_p = 1
.endm

.macro puff24
	setpuff
	.set r24_p = 1
.endm

.macro puff25
	setpuff
	.set r25_p = 1
.endm

.macro puff26
	setpuff
	.set r26_p = 1
.endm

.macro puff27
	setpuff
	.set r27_p = 1
.endm

.macro puff28
	setpuff
	.set r28_p = 1
.endm

.macro puff29
	setpuff
	.set r29_p = 1
.endm

.macro puff30
	setpuff
	.set r30_p = 1
.endm

.macro puff31
	setpuff
	.set r31_p = 1
.endm

#endif /* _SETR_ */ 

;===========================================================================
;=== Macros fuer REG-Undef =================================================
;===========================================================================
; undefxyz		undefiniert xl,h,yl,yh,zl,zh
; defrestore	undefiniert RA-RB, wieder definiert xl,h,yl,yh,zl,zh
; defrestore_a  undefiniert RA
; defrestore_b	undefiniert RB

; defxyz		definiert xl,xh,yl,yh,zl,zh

; defreg_16a	definiert RA0,RA1
; defreg_24a	definiert RA0,RA1,RA2
; defreg_32a	definiert RA0,RA1,RA2,RA3
; defreg_40a	definiert RA0,RA1,RA2,RA3,RA4
; defreg_48a	definiert RA0,RA1,RA2,RA3,RA4,RA5
; defreg_56a	definiert RA0,RA1,RA2,RA3,RA4,RA5,RA6
; defreg_64a	definiert RA0,RA1,RA2,RA3,RA4,RA5,RA6,RA7

; defreg_16b	definiert RB0,RB1
; defreg_24b	definiert RB0,RB1,RB2
; defreg_32b	definiert RB0,RB1,RB2,RB3
; defreg_40b	definiert RB0,RB1,RB2,RB3,RB4
; defreg_48b	definiert RB0,RB1,RB2,RB3,RB4,RB5
; defreg_56b	definiert RB0,RB1,RB2,RB3,RB4,RB5,RB6
; defreg_64b	definiert RB0,RB1,RB2,RB3,RB4,RB5,RB6,RB7

;=========================================================================== 
; um Warning zu vermeiden, da xl,xh,yl,yh,zl,zh in *.inc-Datei vordefiniert
.macro undefxyz
	.ifdef xl
		.undef xl
	.endif
	.ifdef xh
		.undef xh
	.endif
	.ifdef yl
		.undef yl
	.endif
	.ifdef yh
		.undef yh
	.endif
	.ifdef zl
		.undef zl
	.endif
	.ifdef zh
		.undef zh
	.endif
.endm

.macro defrestore_a
	.ifdef RA0
		.undef RA0
	.endif
	.ifdef RA1
		.undef RA1
	.endif
	.ifdef RA2
		.undef RA2
	.endif
	.ifdef RA3
		.undef RA3
	.endif
	.ifdef RA4
		.undef RA4
	.endif
	.ifdef RA5
		.undef RA5
	.endif
	.ifdef RA6
		.undef RA6
	.endif
	.ifdef RA7
		.undef RA7
	.endif
.endm

.macro defrestore_b
	.ifdef RB0
		.undef RB0
	.endif
	.ifdef RB1
		.undef RB1
	.endif
	.ifdef RB2
		.undef RB2
	.endif
	.ifdef RB3
		.undef RB3
	.endif
	.ifdef RB4
		.undef RB4
	.endif
	.ifdef RB5
		.undef RB5
	.endif
	.ifdef RB6
		.undef RB6
	.endif
	.ifdef RB7
		.undef RB7
	.endif
.endm

.macro defxyz
	.ifndef xl
		.def xl = r26
	.endif
	.ifndef xh
		.def xh = r27
	.endif
	.ifndef yl
		.def yl = r28
	.endif
	.ifndef yh
		.def yh = r29
	.endif
	.ifndef zl
		.def zl = r30
	.endif
	.ifndef zh
		.def zh = r31
	.endif
.endm


; nach Macro alles zurueck setzen
.macro defrestore

	defrestore_a
	defrestore_b
	defxyz
.endm

; hier werden Register aus @ definiert

; fuer work
.macro defreg_16w
	.if r17_w
		.def RB0 = r17
		.def RB1 = r18
	.elif r18_w
		.def RB0 = r18
		.def RB1 = r19
	.elif r19_w
		.def RB0 = r19
		.def RB1 = r20
	.elif r20_w
		.def RB0 = r20
		.def RB1 = r21
	.elif r21_w
		.def RB0 = r21
		.def RB1 = r22
	.elif r22_w
		.def RB0 = r22
		.def RB1 = r23
	.elif r23_w
		.def RB0 = r23
		.def RB1 = r24
	.elif r24_w
		.def RB0 = r24
		.def RB1 = r25
	.elif r25_w
		undefxyz
		.def RB0 = r25
		.def RB1 = r26
	.elif r26_w
		undefxyz
		.def RB0 = r26
		.def RB1 = r27
	.elif r27_w
		undefxyz
		.def RB0 = r27
		.def RB1 = r28
	.elif r28_w
		undefxyz
		.def RB0 = r28
		.def RB1 = r29
	.elif r29_w
		undefxyz
		.def RB0 = r29
		.def RB1 = r30
	.elif r30_w
		undefxyz
		.def RB0 = r30
		.def RB1 = r31
	.elif r31_w
		.def RB0 = r31
	.else
		.def RB0 = r16
		.def RB1 = r17
	.endif
.endm

; fuer Puffer
.macro defreg_16p
	.if r0_p
		.def RB0 = r0
		.def RB1 = r1
	.elif r1_p
		.def RB0 = r1
		.def RB1 = r2
	.elif r2_p
		.def RB0 = r2
		.def RB1 = r3
	.elif r3_p
		.def RB0 = r3
		.def RB1 = r4
	.elif r4_p
		.def RB0 = r4
		.def RB1 = r5
	.elif r5_p
		.def RB0 = r5
		.def RB1 = r6
	.elif r6_p
		.def RB0 = r6
		.def RB1 = r7
	.elif r7_p
		.def RB0 = r7
		.def RB1 = r8
	.elif r8_p
		.def RB0 = r8
		.def RB1 = r9
	.elif r9_p
		.def RB0 = r9
		.def RB1 = r10
	.elif r10_p
		.def RB0 = r10
		.def RB1 = r11
	.elif r11_p
		.def RB0 = r11
		.def RB1 = r12
	.elif r12_p
		.def RB0 = r12
		.def RB1 = r13
	.elif r13_p
		.def RB0 = r13
		.def RB1 = r14
	.elif r14_p
		.def RB0 = r14
		.def RB1 = r15
	.elif r15_p
		.def RB0 = r15
		.def RB1 = r16
	.elif r16_p
		.def RB0 = r16
		.def RB1 = r17
	.elif r17_p
		.def RB0 = r17
		.def RB1 = r18
	.elif r18_p
		.def RB0 = r18
		.def RB1 = r19
	.elif r19_p
		.def RB0 = r19
		.def RB1 = r20
	.elif r20_p
		.def RB0 = r20
		.def RB1 = r21
	.elif r21_p
		.def RB0 = r21
		.def RB1 = r22
	.elif r22_p
		.def RB0 = r22
		.def RB1 = r23
	.elif r23_p
		.def RB0 = r23
		.def RB1 = r24
	.elif r24_p
		.def RB0 = r24
		.def RB1 = r25
	.elif r25_p
		undefxyz
		.def RB0 = r25
		.def RB1 = r26
	.elif r26_p
		undefxyz
		.def RB0 = r26
		.def RB1 = r27
	.elif r27_p
		undefxyz
		.def RB0 = r27
		.def RB1 = r28
	.elif r28_p
		undefxyz
		.def RB0 = r28
		.def RB1 = r29
	.elif r29_p
		undefxyz
		.def RB0 = r29
		.def RB1 = r30
	.elif r30_p
		undefxyz
		.def RB0 = r30
		.def RB1 = r31
	.elif r31_p
		.def RB0 = r31
	.else
		.def RB0 = r0
		.def RB1 = r1
	.endif
.endm

.macro defreg_16a
	.if r0_a
		.def RA0 = r0
		.def RA1 = r1
	.elif r1_a
		.def RA0 = r1
		.def RA1 = r2
	.elif r2_a
		.def RA0 = r2
		.def RA1 = r3
	.elif r3_a
		.def RA0 = r3
		.def RA1 = r4
	.elif r4_a
		.def RA0 = r4
		.def RA1 = r5
	.elif r5_a
		.def RA0 = r5
		.def RA1 = r6
	.elif r6_a
		.def RA0 = r6
		.def RA1 = r7
	.elif r7_a
		.def RA0 = r7
		.def RA1 = r8
	.elif r8_a
		.def RA0 = r8
		.def RA1 = r9
	.elif r9_a
		.def RA0 = r9
		.def RA1 = r10
	.elif r10_a
		.def RA0 = r10
		.def RA1 = r11
	.elif r11_a
		.def RA0 = r11
		.def RA1 = r12
	.elif r12_a
		.def RA0 = r12
		.def RA1 = r13
	.elif r13_a
		.def RA0 = r13
		.def RA1 = r14
	.elif r14_a
		.def RA0 = r14
		.def RA1 = r15
	.elif r15_a
		.def RA0 = r15
		.def RA1 = r16
	.elif r16_a
		.def RA0 = r16
		.def RA1 = r17
	.elif r17_a
		.def RA0 = r17
		.def RA1 = r18
	.elif r18_a
		.def RA0 = r18
		.def RA1 = r19
	.elif r19_a
		.def RA0 = r19
		.def RA1 = r20
	.elif r20_a
		.def RA0 = r20
		.def RA1 = r21
	.elif r21_a
		.def RA0 = r21
		.def RA1 = r22
	.elif r22_a
		.def RA0 = r22
		.def RA1 = r23
	.elif r23_a
		.def RA0 = r23
		.def RA1 = r24
	.elif r24_a
		.def RA0 = r24
		.def RA1 = r25
	.elif r25_a
		undefxyz
		.def RA0 = r25
		.def RA1 = r26
	.elif r26_a || X_a || xl_a
		undefxyz
		.def RA0 = r26
		.def RA1 = r27
	.elif r27_a || xh_a
		undefxyz
		.def RA0 = r27
		.def RA1 = r28
	.elif r28_a || Y_a || yl_a
		undefxyz
		.def RA0 = r28
		.def RA1 = r29
	.elif r29_a || yh_a
		undefxyz
		.def RA0 = r29
		.def RA1 = r30
	.elif r30_a || Z_a || zl_a
		undefxyz
		.def RA0 = r30
		.def RA1 = r31
	.else
		.error "Macro defreg_16a reg zu gross"
	.endif
.endm

.macro defreg_24a
	.if r0_a
		.def RA0 = r0
		.def RA1 = r1
		.def RA2 = r2
	.elif r1_a
		.def RA0 = r1
		.def RA1 = r2
		.def RA2 = r3
	.elif r2_a
		.def RA0 = r2
		.def RA1 = r3
		.def RA2 = r4
	.elif r3_a
		.def RA0 = r3
		.def RA1 = r4
		.def RA2 = r5
	.elif r4_a
		.def RA0 = r4
		.def RA1 = r5
		.def RA2 = r6
	.elif r5_a
		.def RA0 = r5
		.def RA1 = r6
		.def RA2 = r7
	.elif r6_a
		.def RA0 = r6
		.def RA1 = r7
		.def RA2 = r8
	.elif r7_a
		.def RA0 = r7
		.def RA1 = r8
		.def RA2 = r9
	.elif r8_a
		.def RA0 = r8
		.def RA1 = r9
		.def RA2 = r10
	.elif r9_a
		.def RA0 = r9
		.def RA1 = r10
		.def RA2 = r11
	.elif r10_a
		.def RA0 = r10
		.def RA1 = r11
		.def RA2 = r12
	.elif r11_a
		.def RA0 = r11
		.def RA1 = r12
		.def RA2 = r13
	.elif r12_a
		.def RA0 = r12
		.def RA1 = r13
		.def RA2 = r14
	.elif r13_a
		.def RA0 = r13
		.def RA1 = r14
		.def RA2 = r15
	.elif r14_a
		.def RA0 = r14
		.def RA1 = r15
		.def RA2 = r16
	.elif r15_a
		.def RA0 = r15
		.def RA1 = r16
		.def RA2 = r17
	.elif r16_a
		.def RA0 = r16
		.def RA1 = r17
		.def RA2 = r18
	.elif r17_a
		.def RA0 = r17
		.def RA1 = r18
		.def RA2 = r19
	.elif r18_a
		.def RA0 = r18
		.def RA1 = r19
		.def RA2 = r20
	.elif r19_a
		.def RA0 = r19
		.def RA1 = r20
		.def RA2 = r21
	.elif r20_a
		.def RA0 = r20
		.def RA1 = r21
		.def RA2 = r22
	.elif r21_a
		.def RA0 = r21
		.def RA1 = r22
		.def RA2 = r23
	.elif r22_a
		.def RA0 = r22
		.def RA1 = r23
		.def RA2 = r24
	.elif r23_a
		.def RA0 = r23
		.def RA1 = r24
		.def RA2 = r25
	.elif r24_a
		undefxyz
		.def RA0 = r24
		.def RA1 = r25
		.def RA2 = r26
	.elif r25_a
		undefxyz
		.def RA0 = r25
		.def RA1 = r26
		.def RA2 = r27
	.elif r26_a || X_a || xl_a
		undefxyz
		.def RA0 = r26
		.def RA1 = r27
		.def RA2 = r28
	.elif r27_a || xh_a
		undefxyz
		.def RA0 = r27
		.def RA1 = r28
		.def RA2 = r29
	.elif r28_a || Y_a || yl_a
		undefxyz
		.def RA0 = r28
		.def RA1 = r29
		.def RA2 = r30
	.elif r29_a || yh_a
		undefxyz
		.def RA0 = r29
		.def RA1 = r30
		.def RA2 = r31
	.elif r30_a || Z_a || zl_a
		undefxyz
		.def RA0 = r30
		.def RA1 = r31
	.else
		.error "Macro defreg_24a reg zu gross"
	.endif
.endm

.macro defreg_32a
	.if r0_a
		.def RA0 = r0
		.def RA1 = r1
		.def RA2 = r2
		.def RA3 = r3
	.elif r1_a
		.def RA0 = r1
		.def RA1 = r2
		.def RA2 = r3
		.def RA3 = r4
	.elif r2_a
		.def RA0 = r2
		.def RA1 = r3
		.def RA2 = r4
		.def RA3 = r5
	.elif r3_a
		.def RA0 = r3
		.def RA1 = r4
		.def RA2 = r5
		.def RA3 = r6
	.elif r4_a
		.def RA0 = r4
		.def RA1 = r5
		.def RA2 = r6
		.def RA3 = r7
	.elif r5_a
		.def RA0 = r5
		.def RA1 = r6
		.def RA2 = r7
		.def RA3 = r8
	.elif r6_a
		.def RA0 = r6
		.def RA1 = r7
		.def RA2 = r8
		.def RA3 = r9
	.elif r7_a
		.def RA0 = r7
		.def RA1 = r8
		.def RA2 = r9
		.def RA3 = r10
	.elif r8_a
		.def RA0 = r8
		.def RA1 = r9
		.def RA2 = r10
		.def RA3 = r11
	.elif r9_a
		.def RA0 = r9
		.def RA1 = r10
		.def RA2 = r11
		.def RA3 = r12
	.elif r10_a
		.def RA0 = r10
		.def RA1 = r11
		.def RA2 = r12
		.def RA3 = r13
	.elif r11_a
		.def RA0 = r11
		.def RA1 = r12
		.def RA2 = r13
		.def RA3 = r14
	.elif r12_a
		.def RA0 = r12
		.def RA1 = r13
		.def RA2 = r14
		.def RA3 = r15
	.elif r13_a
		.def RA0 = r13
		.def RA1 = r14
		.def RA2 = r15
		.def RA3 = r16
	.elif r14_a
		.def RA0 = r14
		.def RA1 = r15
		.def RA2 = r16
		.def RA3 = r17
	.elif r15_a
		.def RA0 = r15
		.def RA1 = r16
		.def RA2 = r17
		.def RA3 = r18
	.elif r16_a
		.def RA0 = r16
		.def RA1 = r17
		.def RA2 = r18
		.def RA3 = r19
	.elif r17_a
		.def RA0 = r17
		.def RA1 = r18
		.def RA2 = r19
		.def RA3 = r20
	.elif r18_a
		.def RA0 = r18
		.def RA1 = r19
		.def RA2 = r20
		.def RA3 = r21
	.elif r19_a
		.def RA0 = r19
		.def RA1 = r20
		.def RA2 = r21
		.def RA3 = r22
	.elif r20_a
		.def RA0 = r20
		.def RA1 = r21
		.def RA2 = r22
		.def RA3 = r23
	.elif r21_a
		.def RA0 = r21
		.def RA1 = r22
		.def RA2 = r23
		.def RA3 = r24
	.elif r22_a
		.def RA0 = r22
		.def RA1 = r23
		.def RA2 = r24
		.def RA3 = r25
	.elif r23_a
		undefxyz
		.def RA0 = r23
		.def RA1 = r24
		.def RA2 = r25
		.def RA3 = r26
	.elif r24_a
		undefxyz
		.def RA0 = r24
		.def RA1 = r25
		.def RA2 = r26
		.def RA3 = r27
	.elif r25_a
		undefxyz
		.def RA0 = r25
		.def RA1 = r26
		.def RA2 = r27
		.def RA3 = r28
	.elif r26_a || X_a || xl_a
		undefxyz
		.def RA0 = r26
		.def RA1 = r27
		.def RA2 = r28
		.def RA3 = r29
	.elif r27_a || xh_a
		undefxyz
		.def RA0 = r27
		.def RA1 = r28
		.def RA2 = r29
		.def RA3 = r30
	.elif r28_a || Y_a || yl_a
		undefxyz
		.def RA0 = r28
		.def RA1 = r29
		.def RA2 = r30
		.def RA3 = r31
	.elif r29_a || yh_a
		undefxyz
		.def RA0 = r29
		.def RA1 = r30
		.def RA2 = r31
	.elif r30_a || Z_a || zl_a
		undefxyz
		.def RA0 = r30
		.def RA1 = r31
	.else
		.error "Macro defreg_32a reg zu gross"
	.endif
.endm

.macro defreg_40a
	.if r0_a
		.def RA0 = r0
		.def RA1 = r1
		.def RA2 = r2
		.def RA3 = r3
		.def RA4 = r4
	.elif r1_a
		.def RA0 = r1
		.def RA1 = r2
		.def RA2 = r3
		.def RA3 = r4
		.def RA4 = r5
	.elif r2_a
		.def RA0 = r2
		.def RA1 = r3
		.def RA2 = r4
		.def RA3 = r5
		.def RA4 = r6
	.elif r3_a
		.def RA0 = r3
		.def RA1 = r4
		.def RA2 = r5
		.def RA3 = r6
		.def RA4 = r7
	.elif r4_a
		.def RA0 = r4
		.def RA1 = r5
		.def RA2 = r6
		.def RA3 = r7
		.def RA4 = r8
	.elif r5_a
		.def RA0 = r5
		.def RA1 = r6
		.def RA2 = r7
		.def RA3 = r8
		.def RA4 = r9
	.elif r6_a
		.def RA0 = r6
		.def RA1 = r7
		.def RA2 = r8
		.def RA3 = r9
		.def RA4 = r10
	.elif r7_a
		.def RA0 = r7
		.def RA1 = r8
		.def RA2 = r9
		.def RA3 = r10
		.def RA4 = r11
	.elif r8_a
		.def RA0 = r8
		.def RA1 = r9
		.def RA2 = r10
		.def RA3 = r11
		.def RA4 = r12
	.elif r9_a
		.def RA0 = r9
		.def RA1 = r10
		.def RA2 = r11
		.def RA3 = r12
		.def RA4 = r13
	.elif r10_a
		.def RA0 = r10
		.def RA1 = r11
		.def RA2 = r12
		.def RA3 = r13
		.def RA4 = r14
	.elif r11_a
		.def RA0 = r11
		.def RA1 = r12
		.def RA2 = r13
		.def RA3 = r14
		.def RA4 = r15
	.elif r12_a
		.def RA0 = r12
		.def RA1 = r13
		.def RA2 = r14
		.def RA3 = r15
		.def RA4 = r16
	.elif r13_a
		.def RA0 = r13
		.def RA1 = r14
		.def RA2 = r15
		.def RA3 = r16
		.def RA4 = r17
	.elif r14_a
		.def RA0 = r14
		.def RA1 = r15
		.def RA2 = r16
		.def RA3 = r17
		.def RA4 = r18
	.elif r15_a
		.def RA0 = r15
		.def RA1 = r16
		.def RA2 = r17
		.def RA3 = r18
		.def RA4 = r19
	.elif r16_a
		.def RA0 = r16
		.def RA1 = r17
		.def RA2 = r18
		.def RA3 = r19
		.def RA4 = r20
	.elif r17_a
		.def RA0 = r17
		.def RA1 = r18
		.def RA2 = r19
		.def RA3 = r20
		.def RA4 = r21
	.elif r18_a
		.def RA0 = r18
		.def RA1 = r19
		.def RA2 = r20
		.def RA3 = r21
		.def RA4 = r22
	.elif r19_a
		.def RA0 = r19
		.def RA1 = r20
		.def RA2 = r21
		.def RA3 = r22
		.def RA4 = r23
	.elif r20_a
		.def RA0 = r20
		.def RA1 = r21
		.def RA2 = r22
		.def RA3 = r23
		.def RA4 = r24
	.elif r21_a
		.def RA0 = r21
		.def RA1 = r22
		.def RA2 = r23
		.def RA3 = r24
		.def RA4 = r25
	.elif r22_a
		undefxyz
		.def RA0 = r22
		.def RA1 = r23
		.def RA2 = r24
		.def RA3 = r25
		.def RA4 = r26
	.elif r23_a
		undefxyz
		.def RA0 = r23
		.def RA1 = r24
		.def RA2 = r25
		.def RA3 = r26
		.def RA4 = r27
	.elif r24_a
		undefxyz
		.def RA0 = r24
		.def RA1 = r25
		.def RA2 = r26
		.def RA3 = r27
		.def RA4 = r28
	.elif r25_a
		undefxyz
		.def RA0 = r25
		.def RA1 = r26
		.def RA2 = r27
		.def RA3 = r28
		.def RA4 = r29
	.elif r26_a || X_a || xl_a
		undefxyz
		.def RA0 = r26
		.def RA1 = r27
		.def RA2 = r28
		.def RA3 = r29
		.def RA4 = r30
	.elif r27_a || xh_a
		undefxyz
		.def RA0 = r27
		.def RA1 = r28
		.def RA2 = r29
		.def RA3 = r30
		.def RA4 = r31
	.elif r28_a || Y_a || yl_a
		undefxyz
		.def RA0 = r28
		.def RA1 = r29
		.def RA2 = r30
		.def RA3 = r31
	.elif r29_a || yh_a
		undefxyz
		.def RA0 = r29
		.def RA1 = r30
		.def RA2 = r31
	.elif r30_a || Z_a || zl_a
		undefxyz
		.def RA0 = r30
		.def RA1 = r31
	.else
		.error "Macro defreg_40a reg zu gross"
	.endif
.endm

.macro defreg_48a
	.if r0_a
		.def RA0 = r0
		.def RA1 = r1
		.def RA2 = r2
		.def RA3 = r3
		.def RA4 = r4
		.def RA5 = r5
	.elif r1_a
		.def RA0 = r1
		.def RA1 = r2
		.def RA2 = r3
		.def RA3 = r4
		.def RA4 = r5
		.def RA5 = r6
	.elif r2_a
		.def RA0 = r2
		.def RA1 = r3
		.def RA2 = r4
		.def RA3 = r5
		.def RA4 = r6
		.def RA5 = r7
	.elif r3_a
		.def RA0 = r3
		.def RA1 = r4
		.def RA2 = r5
		.def RA3 = r6
		.def RA4 = r7
		.def RA5 = r8
	.elif r4_a
		.def RA0 = r4
		.def RA1 = r5
		.def RA2 = r6
		.def RA3 = r7
		.def RA4 = r8
		.def RA5 = r9
	.elif r5_a
		.def RA0 = r5
		.def RA1 = r6
		.def RA2 = r7
		.def RA3 = r8
		.def RA4 = r9
		.def RA5 = r10
	.elif r6_a
		.def RA0 = r6
		.def RA1 = r7
		.def RA2 = r8
		.def RA3 = r9
		.def RA4 = r10
		.def RA5 = r11
	.elif r7_a
		.def RA0 = r7
		.def RA1 = r8
		.def RA2 = r9
		.def RA3 = r10
		.def RA4 = r11
		.def RA5 = r12
	.elif r8_a
		.def RA0 = r8
		.def RA1 = r9
		.def RA2 = r10
		.def RA3 = r11
		.def RA4 = r12
		.def RA5 = r13
	.elif r9_a
		.def RA0 = r9
		.def RA1 = r10
		.def RA2 = r11
		.def RA3 = r12
		.def RA4 = r13
		.def RA5 = r14
	.elif r10_a
		.def RA0 = r10
		.def RA1 = r11
		.def RA2 = r12
		.def RA3 = r13
		.def RA4 = r14
		.def RA5 = r15
	.elif r11_a
		.def RA0 = r11
		.def RA1 = r12
		.def RA2 = r13
		.def RA3 = r14
		.def RA4 = r15
		.def RA5 = r16
	.elif r12_a
		.def RA0 = r12
		.def RA1 = r13
		.def RA2 = r14
		.def RA3 = r15
		.def RA4 = r16
		.def RA5 = r17
	.elif r13_a
		.def RA0 = r13
		.def RA1 = r14
		.def RA2 = r15
		.def RA3 = r16
		.def RA4 = r17
		.def RA5 = r18
	.elif r14_a
		.def RA0 = r14
		.def RA1 = r15
		.def RA2 = r16
		.def RA3 = r17
		.def RA4 = r18
		.def RA5 = r19
	.elif r15_a
		.def RA0 = r15
		.def RA1 = r16
		.def RA2 = r17
		.def RA3 = r18
		.def RA4 = r19
		.def RA5 = r20
	.elif r16_a
		.def RA0 = r16
		.def RA1 = r17
		.def RA2 = r18
		.def RA3 = r19
		.def RA4 = r20
		.def RA5 = r21
	.elif r17_a
		.def RA0 = r17
		.def RA1 = r18
		.def RA2 = r19
		.def RA3 = r20
		.def RA4 = r21
		.def RA5 = r22
	.elif r18_a
		.def RA0 = r18
		.def RA1 = r19
		.def RA2 = r20
		.def RA3 = r21
		.def RA4 = r22
		.def RA5 = r23
	.elif r19_a
		.def RA0 = r19
		.def RA1 = r20
		.def RA2 = r21
		.def RA3 = r22
		.def RA4 = r23
		.def RA5 = r24
	.elif r20_a
		.def RA0 = r20
		.def RA1 = r21
		.def RA2 = r22
		.def RA3 = r23
		.def RA4 = r24
		.def RA5 = r25
	.elif r21_a
		undefxyz
		.def RA0 = r21
		.def RA1 = r22
		.def RA2 = r23
		.def RA3 = r24
		.def RA4 = r25
		.def RA5 = r26
	.elif r22_a
		undefxyz
		.def RA0 = r22
		.def RA1 = r23
		.def RA2 = r24
		.def RA3 = r25
		.def RA4 = r26
		.def RA5 = r27
	.elif r23_a
		undefxyz
		.def RA0 = r23
		.def RA1 = r24
		.def RA2 = r25
		.def RA3 = r26
		.def RA4 = r27
		.def RA5 = r28
	.elif r24_a
		undefxyz
		.def RA0 = r24
		.def RA1 = r25
		.def RA2 = r26
		.def RA3 = r27
		.def RA4 = r28
		.def RA5 = r29
	.elif r25_a
		undefxyz
		.def RA0 = r25
		.def RA1 = r26
		.def RA2 = r27
		.def RA3 = r28
		.def RA4 = r29
		.def RA5 = r30
	.elif r26_a || X_a || xl_a
		undefxyz
		.def RA0 = r26
		.def RA1 = r27
		.def RA2 = r28
		.def RA3 = r29
		.def RA4 = r30
		.def RA5 = r31
	.elif r27_a || xh_a
		undefxyz
		.def RA0 = r27
		.def RA1 = r28
		.def RA2 = r29
		.def RA3 = r30
		.def RA4 = r31
	.elif r28_a || Y_a || yl_a
		undefxyz
		.def RA0 = r28
		.def RA1 = r29
		.def RA2 = r30
		.def RA3 = r31
	.elif r29_a || yh_a
		undefxyz
		.def RA0 = r29
		.def RA1 = r30
		.def RA2 = r31
	.elif r30_a || Z_a || zl_a
		undefxyz
		.def RA0 = r30
		.def RA1 = r31
	.else
		.error "Macro defreg_48a reg zu gross"
	.endif
.endm

.macro defreg_56a
	.if r0_a
		.def RA0 = r0
		.def RA1 = r1
		.def RA2 = r2
		.def RA3 = r3
		.def RA4 = r4
		.def RA5 = r5
		.def RA6 = r6
	.elif r1_a
		.def RA0 = r1
		.def RA1 = r2
		.def RA2 = r3
		.def RA3 = r4
		.def RA4 = r5
		.def RA5 = r6
		.def RA6 = r7
	.elif r2_a
		.def RA0 = r2
		.def RA1 = r3
		.def RA2 = r4
		.def RA3 = r5
		.def RA4 = r6
		.def RA5 = r7
		.def RA6 = r8
	.elif r3_a
		.def RA0 = r3
		.def RA1 = r4
		.def RA2 = r5
		.def RA3 = r6
		.def RA4 = r7
		.def RA5 = r8
		.def RA6 = r9
	.elif r4_a
		.def RA0 = r4
		.def RA1 = r5
		.def RA2 = r6
		.def RA3 = r7
		.def RA4 = r8
		.def RA5 = r9
		.def RA6 = r10
	.elif r5_a
		.def RA0 = r5
		.def RA1 = r6
		.def RA2 = r7
		.def RA3 = r8
		.def RA4 = r9
		.def RA5 = r10
		.def RA6 = r11
	.elif r6_a
		.def RA0 = r6
		.def RA1 = r7
		.def RA2 = r8
		.def RA3 = r9
		.def RA4 = r10
		.def RA5 = r11
		.def RA6 = r12
	.elif r7_a
		.def RA0 = r7
		.def RA1 = r8
		.def RA2 = r9
		.def RA3 = r10
		.def RA4 = r11
		.def RA5 = r12
		.def RA6 = r13
	.elif r8_a
		.def RA0 = r8
		.def RA1 = r9
		.def RA2 = r10
		.def RA3 = r11
		.def RA4 = r12
		.def RA5 = r13
		.def RA6 = r14
	.elif r9_a
		.def RA0 = r9
		.def RA1 = r10
		.def RA2 = r11
		.def RA3 = r12
		.def RA4 = r13
		.def RA5 = r14
		.def RA6 = r15
	.elif r10_a
		.def RA0 = r10
		.def RA1 = r11
		.def RA2 = r12
		.def RA3 = r13
		.def RA4 = r14
		.def RA5 = r15
		.def RA6 = r16
	.elif r11_a
		.def RA0 = r11
		.def RA1 = r12
		.def RA2 = r13
		.def RA3 = r14
		.def RA4 = r15
		.def RA5 = r16
		.def RA6 = r17
	.elif r12_a
		.def RA0 = r12
		.def RA1 = r13
		.def RA2 = r14
		.def RA3 = r15
		.def RA4 = r16
		.def RA5 = r17
		.def RA6 = r18
	.elif r13_a
		.def RA0 = r13
		.def RA1 = r14
		.def RA2 = r15
		.def RA3 = r16
		.def RA4 = r17
		.def RA5 = r18
		.def RA6 = r19
	.elif r14_a
		.def RA0 = r14
		.def RA1 = r15
		.def RA2 = r16
		.def RA3 = r17
		.def RA4 = r18
		.def RA5 = r19
		.def RA6 = r20
	.elif r15_a
		.def RA0 = r15
		.def RA1 = r16
		.def RA2 = r17
		.def RA3 = r18
		.def RA4 = r19
		.def RA5 = r20
		.def RA6 = r21
	.elif r16_a
		.def RA0 = r16
		.def RA1 = r17
		.def RA2 = r18
		.def RA3 = r19
		.def RA4 = r20
		.def RA5 = r21
		.def RA6 = r22
	.elif r17_a
		.def RA0 = r17
		.def RA1 = r18
		.def RA2 = r19
		.def RA3 = r20
		.def RA4 = r21
		.def RA5 = r22
		.def RA6 = r23
	.elif r18_a
		.def RA0 = r18
		.def RA1 = r19
		.def RA2 = r20
		.def RA3 = r21
		.def RA4 = r22
		.def RA5 = r23
		.def RA6 = r24
	.elif r19_a
		.def RA0 = r19
		.def RA1 = r20
		.def RA2 = r21
		.def RA3 = r22
		.def RA4 = r23
		.def RA5 = r24
		.def RA6 = r25
	.elif r20_a
		undefxyz
		.def RA0 = r20
		.def RA1 = r21
		.def RA2 = r22
		.def RA3 = r23
		.def RA4 = r24
		.def RA5 = r25
		.def RA6 = r26
	.elif r21_a
		undefxyz
		.def RA0 = r21
		.def RA1 = r22
		.def RA2 = r23
		.def RA3 = r24
		.def RA4 = r25
		.def RA5 = r26
		.def RA6 = r27
	.elif r22_a
		undefxyz
		.def RA0 = r22
		.def RA1 = r23
		.def RA2 = r24
		.def RA3 = r25
		.def RA4 = r26
		.def RA5 = r27
		.def RA6 = r28
	.elif r23_a
		undefxyz
		.def RA0 = r23
		.def RA1 = r24
		.def RA2 = r25
		.def RA3 = r26
		.def RA4 = r27
		.def RA5 = r28
		.def RA6 = r29
	.elif r24_a
		undefxyz
		.def RA0 = r24
		.def RA1 = r25
		.def RA2 = r26
		.def RA3 = r27
		.def RA4 = r28
		.def RA5 = r29
		.def RA6 = r30
	.elif r25_a
		undefxyz
		.def RA0 = r25
		.def RA1 = r26
		.def RA2 = r27
		.def RA3 = r28
		.def RA4 = r29
		.def RA5 = r30
		.def RA6 = r31
	.elif r26_a || X_a || xl_a
		undefxyz
		.def RA0 = r26
		.def RA1 = r27
		.def RA2 = r28
		.def RA3 = r29
		.def RA4 = r30
		.def RA5 = r31
	.elif r27_a || xh_a
		undefxyz
		.def RA0 = r27
		.def RA1 = r28
		.def RA2 = r29
		.def RA3 = r30
		.def RA4 = r31
	.elif r28_a || Y_a || yl_a
		undefxyz
		.def RA0 = r28
		.def RA1 = r29
		.def RA2 = r30
		.def RA3 = r31
	.elif r29_a || yh_a
		undefxyz
		.def RA0 = r29
		.def RA1 = r30
		.def RA2 = r31
	.elif r30_a || Z_a || zl_a
		undefxyz
		.def RA0 = r30
		.def RA1 = r31
	.else
		.error "Macro defreg_56a reg zu gross"
	.endif
.endm


.macro defreg_64a
	.if r0_a
		.def RA0 = r0
		.def RA1 = r1
		.def RA2 = r2
		.def RA3 = r3
		.def RA4 = r4
		.def RA5 = r5
		.def RA6 = r6
		.def RA7 = r7
	.elif r1_a
		.def RA0 = r1
		.def RA1 = r2
		.def RA2 = r3
		.def RA3 = r4
		.def RA4 = r5
		.def RA5 = r6
		.def RA6 = r7
		.def RA7 = r8
	.elif r2_a
		.def RA0 = r2
		.def RA1 = r3
		.def RA2 = r4
		.def RA3 = r5
		.def RA4 = r6
		.def RA5 = r7
		.def RA6 = r8
		.def RA7 = r9
	.elif r3_a
		.def RA0 = r3
		.def RA1 = r4
		.def RA2 = r5
		.def RA3 = r6
		.def RA4 = r7
		.def RA5 = r8
		.def RA6 = r9
		.def RA7 = r10
	.elif r4_a
		.def RA0 = r4
		.def RA1 = r5
		.def RA2 = r6
		.def RA3 = r7
		.def RA4 = r8
		.def RA5 = r9
		.def RA6 = r10
		.def RA7 = r11
	.elif r5_a
		.def RA0 = r5
		.def RA1 = r6
		.def RA2 = r7
		.def RA3 = r8
		.def RA4 = r9
		.def RA5 = r10
		.def RA6 = r11
		.def RA7 = r12
	.elif r6_a
		.def RA0 = r6
		.def RA1 = r7
		.def RA2 = r8
		.def RA3 = r9
		.def RA4 = r10
		.def RA5 = r11
		.def RA6 = r12
		.def RA7 = r13
	.elif r7_a
		.def RA0 = r7
		.def RA1 = r8
		.def RA2 = r9
		.def RA3 = r10
		.def RA4 = r11
		.def RA5 = r12
		.def RA6 = r13
		.def RA7 = r14
	.elif r8_a
		.def RA0 = r8
		.def RA1 = r9
		.def RA2 = r10
		.def RA3 = r11
		.def RA4 = r12
		.def RA5 = r13
		.def RA6 = r14
		.def RA7 = r15
	.elif r9_a
		.def RA0 = r9
		.def RA1 = r10
		.def RA2 = r11
		.def RA3 = r12
		.def RA4 = r13
		.def RA5 = r14
		.def RA6 = r15
		.def RA7 = r16
	.elif r10_a
		.def RA0 = r10
		.def RA1 = r11
		.def RA2 = r12
		.def RA3 = r13
		.def RA4 = r14
		.def RA5 = r15
		.def RA6 = r16
		.def RA7 = r17
	.elif r11_a
		.def RA0 = r11
		.def RA1 = r12
		.def RA2 = r13
		.def RA3 = r14
		.def RA4 = r15
		.def RA5 = r16
		.def RA6 = r17
		.def RA7 = r18
	.elif r12_a
		.def RA0 = r12
		.def RA1 = r13
		.def RA2 = r14
		.def RA3 = r15
		.def RA4 = r16
		.def RA5 = r17
		.def RA6 = r18
		.def RA7 = r19
	.elif r13_a
		.def RA0 = r13
		.def RA1 = r14
		.def RA2 = r15
		.def RA3 = r16
		.def RA4 = r17
		.def RA5 = r18
		.def RA6 = r19
		.def RA7 = r20
	.elif r14_a
		.def RA0 = r14
		.def RA1 = r15
		.def RA2 = r16
		.def RA3 = r17
		.def RA4 = r18
		.def RA5 = r19
		.def RA6 = r20
		.def RA7 = r21
	.elif r15_a
		.def RA0 = r15
		.def RA1 = r16
		.def RA2 = r17
		.def RA3 = r18
		.def RA4 = r19
		.def RA5 = r20
		.def RA6 = r21
		.def RA7 = r22
	.elif r16_a
		.def RA0 = r16
		.def RA1 = r17
		.def RA2 = r18
		.def RA3 = r19
		.def RA4 = r20
		.def RA5 = r21
		.def RA6 = r22
		.def RA7 = r23
	.elif r17_a
		.def RA0 = r17
		.def RA1 = r18
		.def RA2 = r19
		.def RA3 = r20
		.def RA4 = r21
		.def RA5 = r22
		.def RA6 = r23
		.def RA7 = r24
	.elif r18_a
		.def RA0 = r18
		.def RA1 = r19
		.def RA2 = r20
		.def RA3 = r21
		.def RA4 = r22
		.def RA5 = r23
		.def RA6 = r24
		.def RA7 = r25
	.elif r19_a
		undefxyz
		.def RA0 = r19
		.def RA1 = r20
		.def RA2 = r21
		.def RA3 = r22
		.def RA4 = r23
		.def RA5 = r24
		.def RA6 = r25
		.def RA7 = r26
	.elif r20_a
		undefxyz
		.def RA0 = r20
		.def RA1 = r21
		.def RA2 = r22
		.def RA3 = r23
		.def RA4 = r24
		.def RA5 = r25
		.def RA6 = r26
		.def RA7 = r27
	.elif r21_a
		undefxyz
		.def RA0 = r21
		.def RA1 = r22
		.def RA2 = r23
		.def RA3 = r24
		.def RA4 = r25
		.def RA5 = r26
		.def RA6 = r27
		.def RA7 = r28
	.elif r22_a
		undefxyz
		.def RA0 = r22
		.def RA1 = r23
		.def RA2 = r24
		.def RA3 = r25
		.def RA4 = r26
		.def RA5 = r27
		.def RA6 = r28
		.def RA7 = r29
	.elif r23_a
		undefxyz
		.def RA0 = r23
		.def RA1 = r24
		.def RA2 = r25
		.def RA3 = r26
		.def RA4 = r27
		.def RA5 = r28
		.def RA6 = r29
		.def RA7 = r30
	.elif r24_a
		undefxyz
		.def RA0 = r24
		.def RA1 = r25
		.def RA2 = r26
		.def RA3 = r27
		.def RA4 = r28
		.def RA5 = r29
		.def RA6 = r30
		.def RA7 = r31
	.elif r25_a
		undefxyz
		.def RA0 = r25
		.def RA1 = r26
		.def RA2 = r27
		.def RA3 = r28
		.def RA4 = r29
		.def RA5 = r30
		.def RA6 = r31
	.elif r26_a || X_a || xl_a
		undefxyz
		.def RA0 = r26
		.def RA1 = r27
		.def RA2 = r28
		.def RA3 = r29
		.def RA4 = r30
		.def RA5 = r31
	.elif r27_a || xh_a
		undefxyz
		.def RA0 = r27
		.def RA1 = r28
		.def RA2 = r29
		.def RA3 = r30
		.def RA4 = r31
	.elif r28_a || Y_a || yl_a
		undefxyz
		.def RA0 = r28
		.def RA1 = r29
		.def RA2 = r30
		.def RA3 = r31
	.elif r29_a || yh_a
		undefxyz
		.def RA0 = r29
		.def RA1 = r30
		.def RA2 = r31
	.elif r30_a || Z_a || zl_a
		undefxyz
		.def RA0 = r30
		.def RA1 = r31
	.else
		.error "Macro defreg_64a reg zu gross"
	.endif
.endm

;=======

.macro defreg_16b
	.if r0_b
		.def RB0 = r0
		.def RB1 = r1
	.elif r1_b
		.def RB0 = r1
		.def RB1 = r2
	.elif r2_b
		.def RB0 = r2
		.def RB1 = r3
	.elif r3_b
		.def RB0 = r3
		.def RB1 = r4
	.elif r4_b
		.def RB0 = r4
		.def RB1 = r5
	.elif r5_b
		.def RB0 = r5
		.def RB1 = r6
	.elif r6_b
		.def RB0 = r6
		.def RB1 = r7
	.elif r7_b
		.def RB0 = r7
		.def RB1 = r8
	.elif r8_b
		.def RB0 = r8
		.def RB1 = r9
	.elif r9_b
		.def RB0 = r9
		.def RB1 = r10
	.elif r10_b
		.def RB0 = r10
		.def RB1 = r11
	.elif r11_b
		.def RB0 = r11
		.def RB1 = r12
	.elif r12_b
		.def RB0 = r12
		.def RB1 = r13
	.elif r13_b
		.def RB0 = r13
		.def RB1 = r14
	.elif r14_b
		.def RB0 = r14
		.def RB1 = r15
	.elif r15_b
		.def RB0 = r15
		.def RB1 = r16
	.elif r16_b
		.def RB0 = r16
		.def RB1 = r17
	.elif r17_b
		.def RB0 = r17
		.def RB1 = r18
	.elif r18_b
		.def RB0 = r18
		.def RB1 = r19
	.elif r19_b
		.def RB0 = r19
		.def RB1 = r20
	.elif r20_b
		.def RB0 = r20
		.def RB1 = r21
	.elif r21_b
		.def RB0 = r21
		.def RB1 = r22
	.elif r22_b
		.def RB0 = r22
		.def RB1 = r23
	.elif r23_b
		.def RB0 = r23
		.def RB1 = r24
	.elif r24_b
		.def RB0 = r24
		.def RB1 = r25
	.elif r25_b
		undefxyz
		.def RB0 = r25
		.def RB1 = r26
	.elif r26_b || X_b || xl_b
		undefxyz
		.def RB0 = r26
		.def RB1 = r27
	.elif r27_b || xh_b
		undefxyz
		.def RB0 = r27
		.def RB1 = r28
	.elif r28_b || Y_b || yl_b
		undefxyz
		.def RB0 = r28
		.def RB1 = r29
	.elif r29_b || yh_b
		undefxyz
		.def RB0 = r29
		.def RB1 = r30
	.elif r30_b || Z_b || zl_b
		undefxyz
		.def RB0 = r30
		.def RB1 = r31
	.else
		.error "Macro defreg_16b reg zu gross"
	.endif
.endm

.macro defreg_24b
	.if r0_b
		.def RB0 = r0
		.def RB1 = r1
		.def RB2 = r2
	.elif r1_b
		.def RB0 = r1
		.def RB1 = r2
		.def RB2 = r3
	.elif r2_b
		.def RB0 = r2
		.def RB1 = r3
		.def RB2 = r4
	.elif r3_b
		.def RB0 = r3
		.def RB1 = r4
		.def RB2 = r5
	.elif r4_b
		.def RB0 = r4
		.def RB1 = r5
		.def RB2 = r6
	.elif r5_b
		.def RB0 = r5
		.def RB1 = r6
		.def RB2 = r7
	.elif r6_b
		.def RB0 = r6
		.def RB1 = r7
		.def RB2 = r8
	.elif r7_b
		.def RB0 = r7
		.def RB1 = r8
		.def RB2 = r9
	.elif r8_b
		.def RB0 = r8
		.def RB1 = r9
		.def RB2 = r10
	.elif r9_b
		.def RB0 = r9
		.def RB1 = r10
		.def RB2 = r11
	.elif r10_b
		.def RB0 = r10
		.def RB1 = r11
		.def RB2 = r12
	.elif r11_b
		.def RB0 = r11
		.def RB1 = r12
		.def RB2 = r13
	.elif r12_b
		.def RB0 = r12
		.def RB1 = r13
		.def RB2 = r14
	.elif r13_b
		.def RB0 = r13
		.def RB1 = r14
		.def RB2 = r15
	.elif r14_b
		.def RB0 = r14
		.def RB1 = r15
		.def RB2 = r16
	.elif r15_b
		.def RB0 = r15
		.def RB1 = r16
		.def RB2 = r17
	.elif r16_b
		.def RB0 = r16
		.def RB1 = r17
		.def RB2 = r18
	.elif r17_b
		.def RB0 = r17
		.def RB1 = r18
		.def RB2 = r19
	.elif r18_b
		.def RB0 = r18
		.def RB1 = r19
		.def RB2 = r20
	.elif r19_b
		.def RB0 = r19
		.def RB1 = r20
		.def RB2 = r21
	.elif r20_b
		.def RB0 = r20
		.def RB1 = r21
		.def RB2 = r22
	.elif r21_b
		.def RB0 = r21
		.def RB1 = r22
		.def RB2 = r23
	.elif r22_b
		.def RB0 = r22
		.def RB1 = r23
		.def RB2 = r24
	.elif r23_b
		.def RB0 = r23
		.def RB1 = r24
		.def RB2 = r25
	.elif r24_b
		undefxyz
		.def RB0 = r24
		.def RB1 = r25
		.def RB2 = r26
	.elif r25_b
		undefxyz
		.def RB0 = r25
		.def RB1 = r26
		.def RB2 = r27
	.elif r26_b || X_b || xl_b
		undefxyz
		.def RB0 = r26
		.def RB1 = r27
		.def RB2 = r28
	.elif r27_b || xh_b
		undefxyz
		.def RB0 = r27
		.def RB1 = r28
		.def RB2 = r29
	.elif r28_b || Y_b || yl_b
		undefxyz
		.def RB0 = r28
		.def RB1 = r29
		.def RB2 = r30
	.elif r29_b || yh_b
		undefxyz
		.def RB0 = r29
		.def RB1 = r30
		.def RB2 = r31
	.elif r30_b || Z_b || zl_b
		undefxyz
		.def RB0 = r30
		.def RB1 = r31
	.else
		.error "Macro defreg_24b reg zu gross"
	.endif
.endm

.macro defreg_32b
	.if r0_b
		.def RB0 = r0
		.def RB1 = r1
		.def RB2 = r2
		.def RB3 = r3
	.elif r1_b
		.def RB0 = r1
		.def RB1 = r2
		.def RB2 = r3
		.def RB3 = r4
	.elif r2_b
		.def RB0 = r2
		.def RB1 = r3
		.def RB2 = r4
		.def RB3 = r5
	.elif r3_b
		.def RB0 = r3
		.def RB1 = r4
		.def RB2 = r5
		.def RB3 = r6
	.elif r4_b
		.def RB0 = r4
		.def RB1 = r5
		.def RB2 = r6
		.def RB3 = r7
	.elif r5_b
		.def RB0 = r5
		.def RB1 = r6
		.def RB2 = r7
		.def RB3 = r8
	.elif r6_b
		.def RB0 = r6
		.def RB1 = r7
		.def RB2 = r8
		.def RB3 = r9
	.elif r7_b
		.def RB0 = r7
		.def RB1 = r8
		.def RB2 = r9
		.def RB3 = r10
	.elif r8_b
		.def RB0 = r8
		.def RB1 = r9
		.def RB2 = r10
		.def RB3 = r11
	.elif r9_b
		.def RB0 = r9
		.def RB1 = r10
		.def RB2 = r11
		.def RB3 = r12
	.elif r10_b
		.def RB0 = r10
		.def RB1 = r11
		.def RB2 = r12
		.def RB3 = r13
	.elif r11_b
		.def RB0 = r11
		.def RB1 = r12
		.def RB2 = r13
		.def RB3 = r14
	.elif r12_b
		.def RB0 = r12
		.def RB1 = r13
		.def RB2 = r14
		.def RB3 = r15
	.elif r13_b
		.def RB0 = r13
		.def RB1 = r14
		.def RB2 = r15
		.def RB3 = r16
	.elif r14_b
		.def RB0 = r14
		.def RB1 = r15
		.def RB2 = r16
		.def RB3 = r17
	.elif r15_b
		.def RB0 = r15
		.def RB1 = r16
		.def RB2 = r17
		.def RB3 = r18
	.elif r16_b
		.def RB0 = r16
		.def RB1 = r17
		.def RB2 = r18
		.def RB3 = r19
	.elif r17_b
		.def RB0 = r17
		.def RB1 = r18
		.def RB2 = r19
		.def RB3 = r20
	.elif r18_b
		.def RB0 = r18
		.def RB1 = r19
		.def RB2 = r20
		.def RB3 = r21
	.elif r19_b
		.def RB0 = r19
		.def RB1 = r20
		.def RB2 = r21
		.def RB3 = r22
	.elif r20_b
		.def RB0 = r20
		.def RB1 = r21
		.def RB2 = r22
		.def RB3 = r23
	.elif r21_b
		.def RB0 = r21
		.def RB1 = r22
		.def RB2 = r23
		.def RB3 = r24
	.elif r22_b
		.def RB0 = r22
		.def RB1 = r23
		.def RB2 = r24
		.def RB3 = r25
	.elif r23_b
		undefxyz
		.def RB0 = r23
		.def RB1 = r24
		.def RB2 = r25
		.def RB3 = r26
	.elif r24_b
		undefxyz
		.def RB0 = r24
		.def RB1 = r25
		.def RB2 = r26
		.def RB3 = r27
	.elif r25_b
		undefxyz
		.def RB0 = r25
		.def RB1 = r26
		.def RB2 = r27
		.def RB3 = r28
	.elif r26_b || X_b || xl_b
		undefxyz
		.def RB0 = r26
		.def RB1 = r27
		.def RB2 = r28
		.def RB3 = r29
	.elif r27_b || xh_b
		undefxyz
		.def RB0 = r27
		.def RB1 = r28
		.def RB2 = r29
		.def RB3 = r30
	.elif r28_b || Y_b || yl_b
		undefxyz
		.def RB0 = r28
		.def RB1 = r29
		.def RB2 = r30
		.def RB3 = r31
	.elif r29_b || yh_b
		undefxyz
		.def RB0 = r29
		.def RB1 = r30
		.def RB2 = r31
	.elif r30_b || Z_b || zl_b
		undefxyz
		.def RB0 = r30
		.def RB1 = r31
	.else
		.error "Macro defreg_32b reg zu gross"
	.endif
.endm

.macro defreg_40b
	.if r0_b
		.def RB0 = r0
		.def RB1 = r1
		.def RB2 = r2
		.def RB3 = r3
		.def RB4 = r4
	.elif r1_b
		.def RB0 = r1
		.def RB1 = r2
		.def RB2 = r3
		.def RB3 = r4
		.def RB4 = r5
	.elif r2_b
		.def RB0 = r2
		.def RB1 = r3
		.def RB2 = r4
		.def RB3 = r5
		.def RB4 = r6
	.elif r3_b
		.def RB0 = r3
		.def RB1 = r4
		.def RB2 = r5
		.def RB3 = r6
		.def RB4 = r7
	.elif r4_b
		.def RB0 = r4
		.def RB1 = r5
		.def RB2 = r6
		.def RB3 = r7
		.def RB4 = r8
	.elif r5_b
		.def RB0 = r5
		.def RB1 = r6
		.def RB2 = r7
		.def RB3 = r8
		.def RB4 = r9
	.elif r6_b
		.def RB0 = r6
		.def RB1 = r7
		.def RB2 = r8
		.def RB3 = r9
		.def RB4 = r10
	.elif r7_b
		.def RB0 = r7
		.def RB1 = r8
		.def RB2 = r9
		.def RB3 = r10
		.def RB4 = r11
	.elif r8_b
		.def RB0 = r8
		.def RB1 = r9
		.def RB2 = r10
		.def RB3 = r11
		.def RB4 = r12
	.elif r9_b
		.def RB0 = r9
		.def RB1 = r10
		.def RB2 = r11
		.def RB3 = r12
		.def RB4 = r13
	.elif r10_b
		.def RB0 = r10
		.def RB1 = r11
		.def RB2 = r12
		.def RB3 = r13
		.def RB4 = r14
	.elif r11_b
		.def RB0 = r11
		.def RB1 = r12
		.def RB2 = r13
		.def RB3 = r14
		.def RB4 = r15
	.elif r12_b
		.def RB0 = r12
		.def RB1 = r13
		.def RB2 = r14
		.def RB3 = r15
		.def RB4 = r16
	.elif r13_b
		.def RB0 = r13
		.def RB1 = r14
		.def RB2 = r15
		.def RB3 = r16
		.def RB4 = r17
	.elif r14_b
		.def RB0 = r14
		.def RB1 = r15
		.def RB2 = r16
		.def RB3 = r17
		.def RB4 = r18
	.elif r15_b
		.def RB0 = r15
		.def RB1 = r16
		.def RB2 = r17
		.def RB3 = r18
		.def RB4 = r19
	.elif r16_b
		.def RB0 = r16
		.def RB1 = r17
		.def RB2 = r18
		.def RB3 = r19
		.def RB4 = r20
	.elif r17_b
		.def RB0 = r17
		.def RB1 = r18
		.def RB2 = r19
		.def RB3 = r20
		.def RB4 = r21
	.elif r18_b
		.def RB0 = r18
		.def RB1 = r19
		.def RB2 = r20
		.def RB3 = r21
		.def RB4 = r22
	.elif r19_b
		.def RB0 = r19
		.def RB1 = r20
		.def RB2 = r21
		.def RB3 = r22
		.def RB4 = r23
	.elif r20_b
		.def RB0 = r20
		.def RB1 = r21
		.def RB2 = r22
		.def RB3 = r23
		.def RB4 = r24
	.elif r21_b
		.def RB0 = r21
		.def RB1 = r22
		.def RB2 = r23
		.def RB3 = r24
		.def RB4 = r25
	.elif r22_b
		undefxyz
		.def RB0 = r22
		.def RB1 = r23
		.def RB2 = r24
		.def RB3 = r25
		.def RB4 = r26
	.elif r23_b
		undefxyz
		.def RB0 = r23
		.def RB1 = r24
		.def RB2 = r25
		.def RB3 = r26
		.def RB4 = r27
	.elif r24_b
		undefxyz
		.def RB0 = r24
		.def RB1 = r25
		.def RB2 = r26
		.def RB3 = r27
		.def RB4 = r28
	.elif r25_b
		undefxyz
		.def RB0 = r25
		.def RB1 = r26
		.def RB2 = r27
		.def RB3 = r28
		.def RB4 = r29
	.elif r26_b || X_b || xl_b
		undefxyz
		.def RB0 = r26
		.def RB1 = r27
		.def RB2 = r28
		.def RB3 = r29
		.def RB4 = r30
	.elif r27_b || xh_b
		undefxyz
		.def RB0 = r27
		.def RB1 = r28
		.def RB2 = r29
		.def RB3 = r30
		.def RB4 = r31
	.elif r28_b || Y_b || yl_b
		undefxyz
		.def RB0 = r28
		.def RB1 = r29
		.def RB2 = r30
		.def RB3 = r31
	.elif r29_b || yh_b
		undefxyz
		.def RB0 = r29
		.def RB1 = r30
		.def RB2 = r31
	.elif r30_b || Z_b || zl_b
		undefxyz
		.def RB0 = r30
		.def RB1 = r31
	.else
		.error "Macro defreg_40b reg zu gross"
	.endif
.endm

.macro defreg_48b
	.if r0_b
		.def RB0 = r0
		.def RB1 = r1
		.def RB2 = r2
		.def RB3 = r3
		.def RB4 = r4
		.def RB5 = r5
	.elif r1_b
		.def RB0 = r1
		.def RB1 = r2
		.def RB2 = r3
		.def RB3 = r4
		.def RB4 = r5
		.def RB5 = r6
	.elif r2_b
		.def RB0 = r2
		.def RB1 = r3
		.def RB2 = r4
		.def RB3 = r5
		.def RB4 = r6
		.def RB5 = r7
	.elif r3_b
		.def RB0 = r3
		.def RB1 = r4
		.def RB2 = r5
		.def RB3 = r6
		.def RB4 = r7
		.def RB5 = r8
	.elif r4_b
		.def RB0 = r4
		.def RB1 = r5
		.def RB2 = r6
		.def RB3 = r7
		.def RB4 = r8
		.def RB5 = r9
	.elif r5_b
		.def RB0 = r5
		.def RB1 = r6
		.def RB2 = r7
		.def RB3 = r8
		.def RB4 = r9
		.def RB5 = r10
	.elif r6_b
		.def RB0 = r6
		.def RB1 = r7
		.def RB2 = r8
		.def RB3 = r9
		.def RB4 = r10
		.def RB5 = r11
	.elif r7_b
		.def RB0 = r7
		.def RB1 = r8
		.def RB2 = r9
		.def RB3 = r10
		.def RB4 = r11
		.def RB5 = r12
	.elif r8_b
		.def RB0 = r8
		.def RB1 = r9
		.def RB2 = r10
		.def RB3 = r11
		.def RB4 = r12
		.def RB5 = r13
	.elif r9_b
		.def RB0 = r9
		.def RB1 = r10
		.def RB2 = r11
		.def RB3 = r12
		.def RB4 = r13
		.def RB5 = r14
	.elif r10_b
		.def RB0 = r10
		.def RB1 = r11
		.def RB2 = r12
		.def RB3 = r13
		.def RB4 = r14
		.def RB5 = r15
	.elif r11_b
		.def RB0 = r11
		.def RB1 = r12
		.def RB2 = r13
		.def RB3 = r14
		.def RB4 = r15
		.def RB5 = r16
	.elif r12_b
		.def RB0 = r12
		.def RB1 = r13
		.def RB2 = r14
		.def RB3 = r15
		.def RB4 = r16
		.def RB5 = r17
	.elif r13_b
		.def RB0 = r13
		.def RB1 = r14
		.def RB2 = r15
		.def RB3 = r16
		.def RB4 = r17
		.def RB5 = r18
	.elif r14_b
		.def RB0 = r14
		.def RB1 = r15
		.def RB2 = r16
		.def RB3 = r17
		.def RB4 = r18
		.def RB5 = r19
	.elif r15_b
		.def RB0 = r15
		.def RB1 = r16
		.def RB2 = r17
		.def RB3 = r18
		.def RB4 = r19
		.def RB5 = r20
	.elif r16_b
		.def RB0 = r16
		.def RB1 = r17
		.def RB2 = r18
		.def RB3 = r19
		.def RB4 = r20
		.def RB5 = r21
	.elif r17_b
		.def RB0 = r17
		.def RB1 = r18
		.def RB2 = r19
		.def RB3 = r20
		.def RB4 = r21
		.def RB5 = r22
	.elif r18_b
		.def RB0 = r18
		.def RB1 = r19
		.def RB2 = r20
		.def RB3 = r21
		.def RB4 = r22
		.def RB5 = r23
	.elif r19_b
		.def RB0 = r19
		.def RB1 = r20
		.def RB2 = r21
		.def RB3 = r22
		.def RB4 = r23
		.def RB5 = r24
	.elif r20_b
		.def RB0 = r20
		.def RB1 = r21
		.def RB2 = r22
		.def RB3 = r23
		.def RB4 = r24
		.def RB5 = r25
	.elif r21_b
		undefxyz
		.def RB0 = r21
		.def RB1 = r22
		.def RB2 = r23
		.def RB3 = r24
		.def RB4 = r25
		.def RB5 = r26
	.elif r22_b
		undefxyz
		.def RB0 = r22
		.def RB1 = r23
		.def RB2 = r24
		.def RB3 = r25
		.def RB4 = r26
		.def RB5 = r27
	.elif r23_b
		undefxyz
		.def RB0 = r23
		.def RB1 = r24
		.def RB2 = r25
		.def RB3 = r26
		.def RB4 = r27
		.def RB5 = r28
	.elif r24_b
		undefxyz
		.def RB0 = r24
		.def RB1 = r25
		.def RB2 = r26
		.def RB3 = r27
		.def RB4 = r28
		.def RB5 = r29
	.elif r25_b
		undefxyz
		.def RB0 = r25
		.def RB1 = r26
		.def RB2 = r27
		.def RB3 = r28
		.def RB4 = r29
		.def RB5 = r30
	.elif r26_b || X_b || xl_b
		undefxyz
		.def RB0 = r26
		.def RB1 = r27
		.def RB2 = r28
		.def RB3 = r29
		.def RB4 = r30
		.def RB5 = r31
	.elif r27_b || xh_b
		undefxyz
		.def RB0 = r27
		.def RB1 = r28
		.def RB2 = r29
		.def RB3 = r30
		.def RB4 = r31
	.elif r28_b || Y_b || yl_b
		undefxyz
		.def RB0 = r28
		.def RB1 = r29
		.def RB2 = r30
		.def RB3 = r31
	.elif r29_b || yh_b
		undefxyz
		.def RB0 = r29
		.def RB1 = r30
		.def RB2 = r31
	.elif r30_b || Z_b || zl_b
		undefxyz
		.def RB0 = r30
		.def RB1 = r31
	.else
		.error "Macro defreg_48b reg zu gross"
	.endif
.endm

.macro defreg_56b
	.if r0_b
		.def RB0 = r0
		.def RB1 = r1
		.def RB2 = r2
		.def RB3 = r3
		.def RB4 = r4
		.def RB5 = r5
		.def RB6 = r6
	.elif r1_b
		.def RB0 = r1
		.def RB1 = r2
		.def RB2 = r3
		.def RB3 = r4
		.def RB4 = r5
		.def RB5 = r6
		.def RB6 = r7
	.elif r2_b
		.def RB0 = r2
		.def RB1 = r3
		.def RB2 = r4
		.def RB3 = r5
		.def RB4 = r6
		.def RB5 = r7
		.def RB6 = r8
	.elif r3_b
		.def RB0 = r3
		.def RB1 = r4
		.def RB2 = r5
		.def RB3 = r6
		.def RB4 = r7
		.def RB5 = r8
		.def RB6 = r9
	.elif r4_b
		.def RB0 = r4
		.def RB1 = r5
		.def RB2 = r6
		.def RB3 = r7
		.def RB4 = r8
		.def RB5 = r9
		.def RB6 = r10
	.elif r5_b
		.def RB0 = r5
		.def RB1 = r6
		.def RB2 = r7
		.def RB3 = r8
		.def RB4 = r9
		.def RB5 = r10
		.def RB6 = r11
	.elif r6_b
		.def RB0 = r6
		.def RB1 = r7
		.def RB2 = r8
		.def RB3 = r9
		.def RB4 = r10
		.def RB5 = r11
		.def RB6 = r12
	.elif r7_b
		.def RB0 = r7
		.def RB1 = r8
		.def RB2 = r9
		.def RB3 = r10
		.def RB4 = r11
		.def RB5 = r12
		.def RB6 = r13
	.elif r8_b
		.def RB0 = r8
		.def RB1 = r9
		.def RB2 = r10
		.def RB3 = r11
		.def RB4 = r12
		.def RB5 = r13
		.def RB6 = r14
	.elif r9_b
		.def RB0 = r9
		.def RB1 = r10
		.def RB2 = r11
		.def RB3 = r12
		.def RB4 = r13
		.def RB5 = r14
		.def RB6 = r15
	.elif r10_b
		.def RB0 = r10
		.def RB1 = r11
		.def RB2 = r12
		.def RB3 = r13
		.def RB4 = r14
		.def RB5 = r15
		.def RB6 = r16
	.elif r11_b
		.def RB0 = r11
		.def RB1 = r12
		.def RB2 = r13
		.def RB3 = r14
		.def RB4 = r15
		.def RB5 = r16
		.def RB6 = r17
	.elif r12_b
		.def RB0 = r12
		.def RB1 = r13
		.def RB2 = r14
		.def RB3 = r15
		.def RB4 = r16
		.def RB5 = r17
		.def RB6 = r18
	.elif r13_b
		.def RB0 = r13
		.def RB1 = r14
		.def RB2 = r15
		.def RB3 = r16
		.def RB4 = r17
		.def RB5 = r18
		.def RB6 = r19
	.elif r14_b
		.def RB0 = r14
		.def RB1 = r15
		.def RB2 = r16
		.def RB3 = r17
		.def RB4 = r18
		.def RB5 = r19
		.def RB6 = r20
	.elif r15_b
		.def RB0 = r15
		.def RB1 = r16
		.def RB2 = r17
		.def RB3 = r18
		.def RB4 = r19
		.def RB5 = r20
		.def RB6 = r21
	.elif r16_b
		.def RB0 = r16
		.def RB1 = r17
		.def RB2 = r18
		.def RB3 = r19
		.def RB4 = r20
		.def RB5 = r21
		.def RB6 = r22
	.elif r17_b
		.def RB0 = r17
		.def RB1 = r18
		.def RB2 = r19
		.def RB3 = r20
		.def RB4 = r21
		.def RB5 = r22
		.def RB6 = r23
	.elif r18_b
		.def RB0 = r18
		.def RB1 = r19
		.def RB2 = r20
		.def RB3 = r21
		.def RB4 = r22
		.def RB5 = r23
		.def RB6 = r24
	.elif r19_b
		.def RB0 = r19
		.def RB1 = r20
		.def RB2 = r21
		.def RB3 = r22
		.def RB4 = r23
		.def RB5 = r24
		.def RB6 = r25
	.elif r20_b
		undefxyz
		.def RB0 = r20
		.def RB1 = r21
		.def RB2 = r22
		.def RB3 = r23
		.def RB4 = r24
		.def RB5 = r25
		.def RB6 = r26
	.elif r21_b
		undefxyz
		.def RB0 = r21
		.def RB1 = r22
		.def RB2 = r23
		.def RB3 = r24
		.def RB4 = r25
		.def RB5 = r26
		.def RB6 = r27
	.elif r22_b
		undefxyz
		.def RB0 = r22
		.def RB1 = r23
		.def RB2 = r24
		.def RB3 = r25
		.def RB4 = r26
		.def RB5 = r27
		.def RB6 = r28
	.elif r23_b
		undefxyz
		.def RB0 = r23
		.def RB1 = r24
		.def RB2 = r25
		.def RB3 = r26
		.def RB4 = r27
		.def RB5 = r28
		.def RB6 = r29
	.elif r24_b
		undefxyz
		.def RB0 = r24
		.def RB1 = r25
		.def RB2 = r26
		.def RB3 = r27
		.def RB4 = r28
		.def RB5 = r29
		.def RB6 = r30
	.elif r25_b
		undefxyz
		.def RB0 = r25
		.def RB1 = r26
		.def RB2 = r27
		.def RB3 = r28
		.def RB4 = r29
		.def RB5 = r30
		.def RB6 = r31
	.elif r26_b || X_b || xl_b
		undefxyz
		.def RB0 = r26
		.def RB1 = r27
		.def RB2 = r28
		.def RB3 = r29
		.def RB4 = r30
		.def RB5 = r31
	.elif r27_b || xh_b
		undefxyz
		.def RB0 = r27
		.def RB1 = r28
		.def RB2 = r29
		.def RB3 = r30
		.def RB4 = r31
	.elif r28_b || Y_b || yl_b
		undefxyz
		.def RB0 = r28
		.def RB1 = r29
		.def RB2 = r30
		.def RB3 = r31
	.elif r29_b || yh_b
		undefxyz
		.def RB0 = r29
		.def RB1 = r30
		.def RB2 = r31
	.elif r30_b || Z_b || zl_b
		undefxyz
		.def RB0 = r30
		.def RB1 = r31
	.else
		.error "Macro defreg_56b reg zu gross"
	.endif
.endm


.macro defreg_64b
	.if r0_b
		.def RB0 = r0
		.def RB1 = r1
		.def RB2 = r2
		.def RB3 = r3
		.def RB4 = r4
		.def RB5 = r5
		.def RB6 = r6
		.def RB7 = r7
	.elif r1_b
		.def RB0 = r1
		.def RB1 = r2
		.def RB2 = r3
		.def RB3 = r4
		.def RB4 = r5
		.def RB5 = r6
		.def RB6 = r7
		.def RB7 = r8
	.elif r2_b
		.def RB0 = r2
		.def RB1 = r3
		.def RB2 = r4
		.def RB3 = r5
		.def RB4 = r6
		.def RB5 = r7
		.def RB6 = r8
		.def RB7 = r9
	.elif r3_b
		.def RB0 = r3
		.def RB1 = r4
		.def RB2 = r5
		.def RB3 = r6
		.def RB4 = r7
		.def RB5 = r8
		.def RB6 = r9
		.def RB7 = r10
	.elif r4_b
		.def RB0 = r4
		.def RB1 = r5
		.def RB2 = r6
		.def RB3 = r7
		.def RB4 = r8
		.def RB5 = r9
		.def RB6 = r10
		.def RB7 = r11
	.elif r5_b
		.def RB0 = r5
		.def RB1 = r6
		.def RB2 = r7
		.def RB3 = r8
		.def RB4 = r9
		.def RB5 = r10
		.def RB6 = r11
		.def RB7 = r12
	.elif r6_b
		.def RB0 = r6
		.def RB1 = r7
		.def RB2 = r8
		.def RB3 = r9
		.def RB4 = r10
		.def RB5 = r11
		.def RB6 = r12
		.def RB7 = r13
	.elif r7_b
		.def RB0 = r7
		.def RB1 = r8
		.def RB2 = r9
		.def RB3 = r10
		.def RB4 = r11
		.def RB5 = r12
		.def RB6 = r13
		.def RB7 = r14
	.elif r8_b
		.def RB0 = r8
		.def RB1 = r9
		.def RB2 = r10
		.def RB3 = r11
		.def RB4 = r12
		.def RB5 = r13
		.def RB6 = r14
		.def RB7 = r15
	.elif r9_b
		.def RB0 = r9
		.def RB1 = r10
		.def RB2 = r11
		.def RB3 = r12
		.def RB4 = r13
		.def RB5 = r14
		.def RB6 = r15
		.def RB7 = r16
	.elif r10_b
		.def RB0 = r10
		.def RB1 = r11
		.def RB2 = r12
		.def RB3 = r13
		.def RB4 = r14
		.def RB5 = r15
		.def RB6 = r16
		.def RB7 = r17
	.elif r11_b
		.def RB0 = r11
		.def RB1 = r12
		.def RB2 = r13
		.def RB3 = r14
		.def RB4 = r15
		.def RB5 = r16
		.def RB6 = r17
		.def RB7 = r18
	.elif r12_b
		.def RB0 = r12
		.def RB1 = r13
		.def RB2 = r14
		.def RB3 = r15
		.def RB4 = r16
		.def RB5 = r17
		.def RB6 = r18
		.def RB7 = r19
	.elif r13_b
		.def RB0 = r13
		.def RB1 = r14
		.def RB2 = r15
		.def RB3 = r16
		.def RB4 = r17
		.def RB5 = r18
		.def RB6 = r19
		.def RB7 = r20
	.elif r14_b
		.def RB0 = r14
		.def RB1 = r15
		.def RB2 = r16
		.def RB3 = r17
		.def RB4 = r18
		.def RB5 = r19
		.def RB6 = r20
		.def RB7 = r21
	.elif r15_b
		.def RB0 = r15
		.def RB1 = r16
		.def RB2 = r17
		.def RB3 = r18
		.def RB4 = r19
		.def RB5 = r20
		.def RB6 = r21
		.def RB7 = r22
	.elif r16_b
		.def RB0 = r16
		.def RB1 = r17
		.def RB2 = r18
		.def RB3 = r19
		.def RB4 = r20
		.def RB5 = r21
		.def RB6 = r22
		.def RB7 = r23
	.elif r17_b
		.def RB0 = r17
		.def RB1 = r18
		.def RB2 = r19
		.def RB3 = r20
		.def RB4 = r21
		.def RB5 = r22
		.def RB6 = r23
		.def RB7 = r24
	.elif r18_b
		.def RB0 = r18
		.def RB1 = r19
		.def RB2 = r20
		.def RB3 = r21
		.def RB4 = r22
		.def RB5 = r23
		.def RB6 = r24
		.def RB7 = r25
	.elif r19_b
		undefxyz
		.def RB0 = r19
		.def RB1 = r20
		.def RB2 = r21
		.def RB3 = r22
		.def RB4 = r23
		.def RB5 = r24
		.def RB6 = r25
		.def RB7 = r26
	.elif r20_b
		undefxyz
		.def RB0 = r20
		.def RB1 = r21
		.def RB2 = r22
		.def RB3 = r23
		.def RB4 = r24
		.def RB5 = r25
		.def RB6 = r26
		.def RB7 = r27
	.elif r21_b
		undefxyz
		.def RB0 = r21
		.def RB1 = r22
		.def RB2 = r23
		.def RB3 = r24
		.def RB4 = r25
		.def RB5 = r26
		.def RB6 = r27
		.def RB7 = r28
	.elif r22_b
		undefxyz
		.def RB0 = r22
		.def RB1 = r23
		.def RB2 = r24
		.def RB3 = r25
		.def RB4 = r26
		.def RB5 = r27
		.def RB6 = r28
		.def RB7 = r29
	.elif r23_b
		undefxyz
		.def RB0 = r23
		.def RB1 = r24
		.def RB2 = r25
		.def RB3 = r26
		.def RB4 = r27
		.def RB5 = r28
		.def RB6 = r29
		.def RB7 = r30
	.elif r24_b
		undefxyz
		.def RB0 = r24
		.def RB1 = r25
		.def RB2 = r26
		.def RB3 = r27
		.def RB4 = r28
		.def RB5 = r29
		.def RB6 = r30
		.def RB7 = r31
	.elif r25_b
		undefxyz
		.def RB0 = r25
		.def RB1 = r26
		.def RB2 = r27
		.def RB3 = r28
		.def RB4 = r29
		.def RB5 = r30
		.def RB6 = r31
	.elif r26_b || X_b || xl_b
		undefxyz
		.def RB0 = r26
		.def RB1 = r27
		.def RB2 = r28
		.def RB3 = r29
		.def RB4 = r30
		.def RB5 = r31
	.elif r27_b || xh_b
		undefxyz
		.def RB0 = r27
		.def RB1 = r28
		.def RB2 = r29
		.def RB3 = r30
		.def RB4 = r31
	.elif r28_b || Y_b || yl_b
		undefxyz
		.def RB0 = r28
		.def RB1 = r29
		.def RB2 = r30
		.def RB3 = r31
	.elif r29_b || yh_b
		undefxyz
		.def RB0 = r29
		.def RB1 = r30
		.def RB2 = r31
	.elif r30_b || Z_b || zl_b
		undefxyz
		.def RB0 = r30
		.def RB1 = r31
	.else
		.error "Macro defreg_64b reg zu gross"
	.endif
.endm


;=============================================================================
#endif /* _MACRO_DEFS_ */