#include "../Inc/stm32h753bit6.hpp" /*****************************************************************************/ /* Globals and Static Initialization */ /*****************************************************************************/ INTERRUPT_VECTOR const STM32H753BIT6::s_interruptTable STM32H753BIT6::c_interruptTable = { (uint32) ISR_WWDG, // 0x040 Window Watchdog (uint32) ISR_PVD_PVM, // 0x044 PVD through EXTI Line (uint32) ISR_RTC_TAMPER_CSSLSE, // 0x048 RTC Tamper, CSS LSE (uint32) ISR_RTC_WAKEUP, // 0x04C RTC Wakeup (uint32) ISR_FLASH, // 0x050 Flash (uint32) ISR_RCC, // 0x054 RCC (uint32) ISR_EXTI_0, // 0x058 External Interrupt 0 (uint32) ISR_EXTI_1, // 0x05C External Interrupt 1 (uint32) ISR_EXTI_2, // 0x060 External Interrupt 2 (uint32) ISR_EXTI_3, // 0x064 External Interrupt 3 (uint32) ISR_EXTI_4, // 0x068 External Interrupt 4 (uint32) ISR_DMA_1_CH0, // 0x06C DMA 1 Channel 0 (uint32) ISR_DMA_1_CH1, // 0x070 DMA 1 Channel 1 (uint32) ISR_DMA_1_CH2, // 0x074 DMA 1 Channel 2 (uint32) ISR_DMA_1_CH3, // 0x078 DMA 1 Channel 3 (uint32) ISR_DMA_1_CH4, // 0x07C DMA 1 Channel 4 (uint32) ISR_DMA_1_CH5, // 0x080 DMA 1 Channel 5 (uint32) ISR_DMA_1_CH6, // 0x084 DMA 1 Channel 6 (uint32) ISR_ADC_1_2, // 0x088 ADC 1 and ADC 2 (uint32) ISR_FDCAN_1_INT0, // 0x08C FDCAN 1 Interrupt 0 (uint32) ISR_FDCAN_2_INT0, // 0x090 FDCAN 2 Interrupt 0 (uint32) ISR_FDCAN_1_INT1, // 0x094 FDCAN 1 Interrupt 1 (uint32) ISR_FDCAN_2_INT1, // 0x098 FDCAN 2 Interrupt 1 (uint32) ISR_EXTI_9_TO_5, // 0x09C External Interrupt 9 to 5 (uint32) ISR_TIMER_1_BREAK, // 0x0A0 Timer 1 Break (uint32) ISR_TIMER_1_UPDATE, // 0x0A4 Timer 1 Update (uint32) ISR_TIMER_1_TRIGGER_COMMUTATION, // 0x0A8 Timer 1 Trigger and Commutation (uint32) ISR_TIMER_1_CAPTURE_COMPARE, // 0x0AC Timer 1 Capture Compare (uint32) ISR_TIMER_2, // 0x0B0 Timer 2 (uint32) ISR_TIMER_3, // 0x0B4 Timer 3 (uint32) ISR_TIMER_4, // 0x0B8 Timer 4 (uint32) ISR_I2C_1_EVENT, // 0x0BC I2C 1 Event (uint32) ISR_I2C_1_ERROR, // 0x0C0 I2C 1 Error (uint32) ISR_I2C_2_EVENT, // 0x0C4 I2C 2 Event (uint32) ISR_I2C_2_ERROR, // 0x0C8 I2C 2 Error (uint32) ISR_SPI_1, // 0x0CC SPI 1 (uint32) ISR_SPI_2, // 0x0D0 SPI 2 (uint32) ISR_USART_1, // 0x0D4 USART 1 (uint32) ISR_USART_2, // 0x0D8 USART 2 (uint32) ISR_USART_3, // 0x0DC USART 3 (uint32) ISR_EXTI_15_TO_10, // 0x0E0 External Interrupt 15 to 10 (uint32) ISR_RTC_ALARM_EXTI, // 0x0E4 RTC Alarm through External Interrupt (uint32) 0, // 0x0E8 Reserved (uint32) ISR_TIMER_8_BREAK_AND_TIMER_12, // 0x0EC Timer 8 Break and Timer 12 (uint32) ISR_TIMER_8_UPDATE_AND_TIMER_13, // 0x0F0 Timer 8 Update and TImer 13 (uint32) ISR_TIMER_8_TRIGGER_COMMUTATION_AND_TIMER_14, // 0x0F4 Timer 8 Trigger and Commutation and Timer 14 (uint32) ISR_TIMER_8_CAPTURE_COMPARE, // 0x0F8 Timer 8 Capture Compare (uint32) ISR_DMA_1_CH7, // 0x0FC DMA 1 Channel 7 (uint32) ISR_FMC, // 0x100 FMC (uint32) ISR_SDMMC_1, // 0x104 SDMMC 1 (uint32) ISR_TIMER_5, // 0x108 Timer 5 (uint32) ISR_SPI_3, // 0x10C SPI 3 (uint32) ISR_UART_4, // 0x110 UART 4 (uint32) ISR_UART_5, // 0x114 UART 5 (uint32) ISR_TIMER_6_AND_DAC, // 0x118 Timer 6 and DAC Underrun Error (uint32) ISR_TIMER_7, // 0x11C Timer 7 (uint32) ISR_DMA_2_CH0, // 0x120 DMA 2 Channel 0 (uint32) ISR_DMA_2_CH1, // 0x124 DMA 2 Channel 1 (uint32) ISR_DMA_2_CH2, // 0x128 DMA 2 Channel 2 (uint32) ISR_DMA_2_CH3, // 0x12C DMA 2 Channel 3 (uint32) ISR_DMA_2_CH4, // 0x130 DMA 2 Channel 4 (uint32) ISR_ETHERNET, // 0x134 Ethernet Global (uint32) ISR_ETHERNET_WAKEUP, // 0x138 Ethernet Wakeup (uint32) ISR_FDCAN_CALIBRATION, // 0x13C FDCAN Calibration (uint32) ISR_ARM_CORTEX_M7_SEND_EVEN, // 0x140 ARM Cortex M7 Send Even Interrupt (uint32) 0, // 0x144 Reserved (uint32) 0, // 0x148 Reserved (uint32) 0, // 0x14C Reserved (uint32) ISR_DMA_2_CH5, // 0x150 DMA 2 Channel 5 (uint32) ISR_DMA_2_CH6, // 0x154 DMA 2 Channel 6 (uint32) ISR_DMA_2_CH7, // 0x158 DMA 2 Channel 7 (uint32) ISR_USART_6, // 0x15C USART 6 (uint32) ISR_I2C_3_EVENT, // 0x160 I2C 3 Event (uint32) ISR_I2C_3_ERROR, // 0x164 I2C 3 Error (uint32) ISR_USB_HS_EP1_OUT, // 0x168 USB OTG High Speed EP1 OUT (uint32) ISR_USB_HS_EP1_IN, // 0x16C USB OTG High Speed EP1 IN (uint32) ISR_USB_HS_WAKEUP, // 0x170 USB OTG High Speed Wakeup (uint32) ISR_USB_HS, // 0x174 USB OTG High Speed Global (uint32) ISR_DCMI, // 0x178 Digital Camera Interface (uint32) ISR_CRYPTO, // 0x17C Cryptographic Processor (uint32) ISR_HASH_RNG, // 0x180 Hash Processor and True Random Number Generator (uint32) ISR_FPU, // 0x184 CPU Floating Point Unit (uint32) ISR_UART_7, // 0x188 UART 7 (uint32) ISR_UART_8, // 0x18C UART 8 (uint32) ISR_SPI_4, // 0x190 SPI 4 (uint32) ISR_SPI_5, // 0x194 SPI 5 (uint32) ISR_SPI_6, // 0x198 SPI 6 (uint32) ISR_SAI_1, // 0x19C SAI 1 (uint32) ISR_LTDC, // 0x1A0 LTDC Controller Global (uint32) ISR_LTDC_ERROR, // 0x1A4 LTDC Controller Error (uint32) ISR_DMA2D, // 0x1A8 DMA2D (uint32) ISR_SAI_2, // 0x1AC SAI 2 (uint32) ISR_QUADSPI, // 0x1B0 Quad SPI (uint32) ISR_LP_TIMER_1, // 0x1B4 Low Power Timer 1 (uint32) ISR_HDMI_CEC, // 0x1B8 HDMI CEC (uint32) ISR_I2C_4_EVENT, // 0x1BC I2C 4 Event (uint32) ISR_I2C_4_ERROR, // 0x1C0 I2C 4 Error (uint32) ISR_SPDIF, // 0x1C4 SPDIF (uint32) ISR_USB_FS_EP1_OUT, // 0x1C8 USB OTG Full Speed EP1 OUT (uint32) ISR_USB_FS_EP1_IN, // 0x1CC USB OTG Full Speed EP1 IN (uint32) ISR_USB_FS_WAKEUP, // 0x1D0 USB OTG Full Speed Wakeup (uint32) ISR_USB_FS, // 0x1D4 USB OTG Full Speed Global (uint32) ISR_DMAMUX_1_OVERRUN, // 0x1D8 DMAMUX 1 Overrun (uint32) ISR_HR_TIMER_MASTER, // 0x1DC High Resolution Timer Master Timer (uint32) ISR_HR_TIMER_A, // 0x1E0 High Resolution Timer Channel A (uint32) ISR_HR_TIMER_B, // 0x1E4 High Resolution Timer Channel B (uint32) ISR_HR_TIMER_C, // 0x1E8 High Resolution Timer Channel C (uint32) ISR_HR_TIMER_D, // 0x1EC High Resolution Timer Channel D (uint32) ISR_HR_TIMER_E, // 0x1F0 High Resolution Timer Channel E (uint32) ISR_HR_TIMER_FAULT, // 0x1F4 High Resolution Timer Fault (uint32) ISR_DFSDM_FILTER_0, // 0x1F8 DFSDM Filter 0 (uint32) ISR_DFSDM_FILTER_1, // 0x1FC DFSDM Filter 1 (uint32) ISR_DFSDM_FILTER_2, // 0x200 DFSDM Filter 2 (uint32) ISR_DFSDM_FILTER_3, // 0x204 DFSDM Filter 3 (uint32) ISR_SAI_3, // 0x208 SAI 3 (uint32) ISR_SWPMI, // 0x20C SWPMI (uint32) ISR_TIMER_15, // 0x210 Timer 15 (uint32) ISR_TIMER_16, // 0x214 Timer 16 (uint32) ISR_TIMER_17, // 0x218 Timer 17 (uint32) ISR_MDIOS_WAKEUP, // 0x21C MDIOS Wakeup (uint32) ISR_MDIOS, // 0x220 MDIOS Global (uint32) ISR_JPEG, // 0x224 JPEG (uint32) ISR_MDMA, // 0x228 MDMA (uint32) 0, // 0x22C Reserved (uint32) ISR_SDMMC_2, // 0x230 SDMMC 2 (uint32) ISR_HSEM, // 0x234 HSEM (uint32) 0, // 0x238 Reserved (uint32) ISR_ADC_3, // 0x23C ADC 3 (uint32) ISR_DMAMUX_2_OVERRUN, // 0x240 DMAMUX 2 Overrun (uint32) ISR_BDMA_CH0, // 0x244 BDMA Channel 0 (uint32) ISR_BDMA_CH1, // 0x248 BDMA Channel 1 (uint32) ISR_BDMA_CH2, // 0x24C BDMA Channel 2 (uint32) ISR_BDMA_CH3, // 0x250 BDMA Channel 3 (uint32) ISR_BDMA_CH4, // 0x254 BDMA Channel 4 (uint32) ISR_BDMA_CH5, // 0x258 BDMA Channel 5 (uint32) ISR_BDMA_CH6, // 0x25C BDMA Channel 6 (uint32) ISR_BDMA_CH7, // 0x260 BDMA Channel 7 (uint32) ISR_COMP_1_2, // 0x264 Comparator 1 and 2 (uint32) ISR_LP_TIMER_2, // 0x268 Low Power Timer 2 (uint32) ISR_LP_TIMER_3, // 0x26C Low Power Timer 3 (uint32) ISR_LP_TIMER_4, // 0x270 Low Power Timer 4 (uint32) ISR_LP_TIMER_5, // 0x274 Low Power Timer 5 (uint32) ISR_LP_UART, // 0x278 Low Power UART (uint32) ISR_WWDG_RESET, // 0x27C Window Watchdog Reset (uint32) ISR_CRS, // 0x280 Clock Recovery System (uint32) ISR_RAM_ECC, // 0x284 ECC Diagnostic for RAMECC D1 to D3 (uint32) ISR_SAI_4, // 0x288 SAI 4 Global (uint32) 0, // 0x28C Reserved (uint32) 0, // 0x290 Reserved (uint32) ISR_WAKEUP_PIN_0_TO_5, // 0x294 Wakeup Pins 0 to 5 (uint32) 0, // 0x298 Reserved (uint32) 0, // 0x29C Reserved (uint32) 0, // 0x2A0 Reserved (uint32) 0, // 0x2A4 Reserved (uint32) 0, // 0x2A8 Reserved (uint32) 0, // 0x2AC Reserved (uint32) 0, // 0x2B0 Reserved (uint32) 0, // 0x2B4 Reserved (uint32) 0, // 0x2B8 Reserved (uint32) 0, // 0x2BC Reserved (uint32) 0, // 0x2C0 Reserved (uint32) 0, // 0x2C4 Reserved (uint32) 0, // 0x2C8 Reserved (uint32) 0, // 0x2CC Reserved (uint32) 0, // 0x2D0 Reserved (uint32) 0, // 0x2D4 Reserved (uint32) 0, // 0x2D8 Reserved (uint32) 0, // 0x2DC Reserved (uint32) 0, // 0x2E0 Reserved (uint32) 0, // 0x2E4 Reserved (uint32) 0, // 0x2E8 Reserved (uint32) 0, // 0x2EC Reserved (uint32) 0, // 0x2F0 Reserved (uint32) 0, // 0x2F4 Reserved (uint32) 0, // 0x2F8 Reserved (uint32) 0, // 0x2FC Reserved (uint32) 0, // 0x300 Reserved (uint32) 0, // 0x304 Reserved (uint32) 0, // 0x308 Reserved (uint32) 0, // 0x30C Reserved (uint32) 0, // 0x310 Reserved (uint32) 0, // 0x314 Reserved (uint32) 0, // 0x318 Reserved (uint32) 0, // 0x31C Reserved (uint32) 0, // 0x320 Reserved (uint32) 0, // 0x324 Reserved (uint32) 0, // 0x328 Reserved (uint32) 0, // 0x32C Reserved (uint32) 0, // 0x330 Reserved (uint32) 0, // 0x334 Reserved (uint32) 0, // 0x338 Reserved (uint32) 0, // 0x33C Reserved (uint32) 0, // 0x340 Reserved (uint32) 0, // 0x344 Reserved (uint32) 0, // 0x348 Reserved (uint32) 0, // 0x34C Reserved (uint32) 0, // 0x350 Reserved (uint32) 0, // 0x354 Reserved (uint32) 0, // 0x358 Reserved (uint32) 0, // 0x35C Reserved (uint32) 0, // 0x360 Reserved (uint32) 0, // 0x364 Reserved (uint32) 0, // 0x368 Reserved (uint32) 0, // 0x36C Reserved (uint32) 0, // 0x370 Reserved (uint32) 0, // 0x374 Reserved (uint32) 0, // 0x378 Reserved (uint32) 0, // 0x37C Reserved (uint32) 0, // 0x380 Reserved (uint32) 0, // 0x384 Reserved (uint32) 0, // 0x388 Reserved (uint32) 0, // 0x38C Reserved (uint32) 0, // 0x390 Reserved (uint32) 0, // 0x394 Reserved (uint32) 0, // 0x398 Reserved (uint32) 0, // 0x39C Reserved (uint32) 0, // 0x3A0 Reserved (uint32) 0, // 0x3A4 Reserved (uint32) 0, // 0x3A8 Reserved (uint32) 0, // 0x3AC Reserved (uint32) 0, // 0x3B0 Reserved (uint32) 0, // 0x3B4 Reserved (uint32) 0, // 0x3B8 Reserved (uint32) 0, // 0x3BC Reserved (uint32) 0, // 0x3C0 Reserved (uint32) 0, // 0x3C4 Reserved (uint32) 0, // 0x3C8 Reserved (uint32) 0, // 0x3CC Reserved (uint32) 0, // 0x3D0 Reserved (uint32) 0, // 0x3D4 Reserved (uint32) 0, // 0x3D8 Reserved (uint32) 0, // 0x3DC Reserved (uint32) 0, // 0x3E0 Reserved (uint32) 0, // 0x3E4 Reserved (uint32) 0, // 0x3E8 Reserved (uint32) 0, // 0x3EC Reserved (uint32) 0, // 0x3F0 Reserved (uint32) 0, // 0x3F4 Reserved (uint32) 0, // 0x3F8 Reserved (uint32) 0 // 0x3FC Reserved }; /*****************************************************************************/ /* Private */ /*****************************************************************************/ void CODE_FLASH(STM32H753BIT6::copy_flashToRAM)(const uint32* const src, uint32* const dest, uint32 sizeInBytes) { for(uint32 i = 0; i < sizeInBytes / 4; i++) { *(dest + i) = *(src + i); } } void CODE_FLASH(STM32H753BIT6::zeroOutRAM)(uint32* const startAddress, uint32 sizeInBytes) { for(uint32 i = 0; i < sizeInBytes / 4; i++) { *(startAddress + i) = 0; } } /*****************************************************************************/ /* Public */ /*****************************************************************************/ CODE_HARDWARE(STM32H753BIT6::STM32H753BIT6)() : m_debug(), m_syscfg(), m_pwr(m_syscfg), m_flash(), m_rcc(m_pwr, m_flash), m_backupSRAM(m_rcc), m_gpio(m_rcc), m_hsem(), m_rtc(m_rcc), m_exti(), m_vrefbuf(m_rcc), m_dma2d(m_hsem[16]), m_mdma(), m_dmamux(), m_dma_1({m_hsem[0], m_hsem[1], m_hsem[2], m_hsem[3], m_hsem[4], m_hsem[5], m_hsem[6], m_hsem[7]}), m_dma_2({m_hsem[8], m_hsem[9], m_hsem[10], m_hsem[11], m_hsem[12], m_hsem[13], m_hsem[14], m_hsem[15]}), m_adc_1(m_rcc, m_dma_1[0], m_dmamux, System::get().get_nvic()), m_adc_2(m_rcc, m_dma_1[1], m_dmamux, System::get().get_nvic()), m_adc_3(m_rcc, m_dma_1[2], m_dmamux, System::get().get_nvic()), m_timer_1(m_rcc), m_timer_2(m_rcc), m_timer_3(m_rcc), m_timer_12(m_rcc), m_timer_13(m_rcc), m_timer_15(m_rcc), m_timer_16(m_rcc), m_timer_17(m_rcc), m_uart_5(m_rcc, m_dma_1[3], m_dma_1[4], m_dmamux, System::get().get_nvic()), m_uart_7(m_rcc, m_dma_1[5], m_dma_1[6], m_dmamux, System::get().get_nvic()), m_fmc(m_rcc), m_ltdc(), m_i2c_1(), m_sdmmc_1(m_hsem[17]), m_sdmmc_2(m_hsem[18]) { } STM32H753BIT6& CODE_HARDWARE(STM32H753BIT6::get)() { static STM32H753BIT6 DATA_HARDWARE_0(stm32h753bit6); return(stm32h753bit6); } feedback CODE_HARDWARE(STM32H753BIT6::startup)() { if(m_debug.startup() != OK) { return(FAIL); } if(m_syscfg.startup() != OK) { return(FAIL); } if(m_pwr.startup() != OK) { return(FAIL); } if(m_flash.startup() != OK) { return(FAIL); } if(m_rcc.startup() != OK) { return(FAIL); } if(m_backupSRAM.startup() != OK) { return(FAIL); } if(m_gpio.startup() != OK) { return(FAIL); } for(uint32 i = 0; i < HSEM::c_number; i++) { if(m_hsem[i].startup(m_rcc, i) != OK) { return(FAIL); } } if(m_rtc.startup() != OK) { return(FAIL); } if(m_exti.startup(m_rcc) != OK) { return(FAIL); } if(m_vrefbuf.startup() != OK) { return(FAIL); } if(m_dma2d.startup(m_rcc) != OK) { return(FAIL); } if(m_mdma.startup(m_rcc) != OK) { return(FAIL); } if(m_dmamux.startup() != OK) { return(FAIL); } for(uint32 i = 0; i < DMA_1::c_channel; i++) { if(m_dma_1[i].startup(m_rcc, i) != OK) { return(FAIL); } } for(uint32 i = 0; i < DMA_2::c_channel; i++) { if(m_dma_2[i].startup(m_rcc, i) != OK) { return(FAIL); } } if(m_adc_1.startup(m_vrefbuf) != OK) { return(FAIL); } if(m_adc_2.startup(m_vrefbuf) != OK) { return(FAIL); } if(m_adc_3.startup(m_vrefbuf) != OK) { return(FAIL); } if(m_timer_1.startup() != OK) { return(FAIL); } if(m_timer_2.startup() != OK) { return(FAIL); } if(m_timer_3.startup() != OK) { return(FAIL); } if(m_timer_12.startup() != OK) { return(FAIL); } if(m_timer_13.startup() != OK) { return(FAIL); } if(m_timer_15.startup() != OK) { return(FAIL); } if(m_timer_16.startup() != OK) { return(FAIL); } if(m_timer_17.startup() != OK) { return(FAIL); } if(m_uart_5.startup() != OK) { return(FAIL); } if(m_uart_7.startup() != OK) { return(FAIL); } if(m_fmc.startup() != OK) { return(FAIL); } if(m_ltdc.startup(m_rcc) != OK) { return(FAIL); } if(m_i2c_1.startup(m_rcc) != OK) { return(FAIL); } if(m_sdmmc_1.startup() != OK) { return(FAIL); } if(m_sdmmc_2.startup() != OK) { return(FAIL); } return(OK); } Debug& CODE_HARDWARE(STM32H753BIT6::get_debug)() { return(m_debug); } Pwr& CODE_HARDWARE(STM32H753BIT6::get_pwr)() { return(m_pwr); } Flash& CODE_HARDWARE(STM32H753BIT6::get_flash)() { return(m_flash); } RCC& CODE_HARDWARE(STM32H753BIT6::get_rcc)() { return(m_rcc); } BackupSRAM& CODE_HARDWARE(STM32H753BIT6::get_backupSRAM)() { return(m_backupSRAM); } GPIO& CODE_HARDWARE(STM32H753BIT6::get_gpio)() { return(m_gpio); } HSEM& CODE_HARDWARE(STM32H753BIT6::get_hsem)(uint8 number) { if(number < HSEM::c_number) { return(m_hsem[number]); } HSEM& fail = (HSEM&) *((HSEM*) NULL); return(fail); } RTC& CODE_HARDWARE(STM32H753BIT6::get_rtc)() { return(m_rtc); } EXTI& CODE_HARDWARE(STM32H753BIT6::get_exti)() { return(m_exti); } VREFBUF& CODE_HARDWARE(STM32H753BIT6::get_vrefbuf)() { return(m_vrefbuf); } DMA2D& CODE_HARDWARE(STM32H753BIT6::get_dma2d)() { return(m_dma2d); } MDMA& CODE_HARDWARE(STM32H753BIT6::get_mdma)() { return(m_mdma); } DMAMUX& CODE_HARDWARE(STM32H753BIT6::get_dmamux)() { return(m_dmamux); } DMA_1& CODE_HARDWARE(STM32H753BIT6::get_dma_1)(uint8 channel) { if(channel < DMA_1::c_channel) { return(m_dma_1[channel]); } DMA_1& fail = (DMA_1&) *((DMA_1*) NULL); return(fail); } DMA_2& CODE_HARDWARE(STM32H753BIT6::get_dma_2)(uint8 channel) { if(channel < DMA_2::c_channel) { return(m_dma_2[channel]); } DMA_2& fail = (DMA_2&) *((DMA_2*) NULL); return(fail); } ADC_1& CODE_HARDWARE(STM32H753BIT6::get_adc_1)() { return(m_adc_1); } ADC_2& CODE_HARDWARE(STM32H753BIT6::get_adc_2)() { return(m_adc_2); } ADC_3& CODE_HARDWARE(STM32H753BIT6::get_adc_3)() { return(m_adc_3); } Timer_1& CODE_HARDWARE(STM32H753BIT6::get_timer_1)() { return(m_timer_1); } Timer_2& CODE_HARDWARE(STM32H753BIT6::get_timer_2)() { return(m_timer_2); } Timer_3& CODE_HARDWARE(STM32H753BIT6::get_timer_3)() { return(m_timer_3); } Timer_12& CODE_HARDWARE(STM32H753BIT6::get_timer_12)() { return(m_timer_12); } Timer_13& CODE_HARDWARE(STM32H753BIT6::get_timer_13)() { return(m_timer_13); } Timer_15& CODE_HARDWARE(STM32H753BIT6::get_timer_15)() { return(m_timer_15); } Timer_16& CODE_HARDWARE(STM32H753BIT6::get_timer_16)() { return(m_timer_16); } Timer_17& CODE_HARDWARE(STM32H753BIT6::get_timer_17)() { return(m_timer_17); } UART_5& CODE_HARDWARE(STM32H753BIT6::get_uart_5)() { return(m_uart_5); } UART_7& CODE_HARDWARE(STM32H753BIT6::get_uart_7)() { return(m_uart_7); } FMC& CODE_HARDWARE(STM32H753BIT6::get_fmc)() { return(m_fmc); } LTDC& CODE_HARDWARE(STM32H753BIT6::get_ltdc)() { return(m_ltdc); } I2C_1& CODE_HARDWARE(STM32H753BIT6::get_i2c_1)() { return(m_i2c_1); } SDMMC_1& CODE_HARDWARE(STM32H753BIT6::get_sdmmc_1)() { return(m_sdmmc_1); } SDMMC_2& CODE_HARDWARE(STM32H753BIT6::get_sdmmc_2)() { return(m_sdmmc_2); } void CODE_FLASH(EXCEPTION_RESET)() { extern uint32 __c_memory_SRAM_ITCM_start__; extern uint32 __c_memory_SRAM_ITCM_size__; extern uint32 __c_memory_SRAM_DTCM_start__; extern uint32 __c_memory_SRAM_DTCM_size__; extern uint32 __c_memory_SRAM_AXI_start__; extern uint32 __c_memory_SRAM_AXI_size__; extern uint32 __c_memory_SRAM_1_start__; extern uint32 __c_memory_SRAM_1_size__; extern uint32 __c_memory_SRAM_2_start__; extern uint32 __c_memory_SRAM_2_size__; extern uint32 __c_memory_SRAM_3_start__; extern uint32 __c_memory_SRAM_3_size__; extern uint32 __c_memory_SRAM_4_start__; extern uint32 __c_memory_SRAM_4_size__; extern uint32 __c_code_isr_flash_start__; extern uint32 __c_code_isr_flash_size__; extern uint32 __c_code_isr_ram_start__; extern uint32 __c_code_sram_flash_start__; extern uint32 __c_code_sram_flash_size__; extern uint32 __c_code_sram_ram_start__; extern uint32 __c_data_sram_flash_start__; extern uint32 __c_data_sram_flash_size__; extern uint32 __c_data_sram_ram_start__; extern uint32 __c_data_user_flash_start__; extern uint32 __c_data_user_flash_size__; extern uint32 __c_data_user_ram_start__; uint32* const c_memory_SRAM_ITCM_start = (uint32*) &__c_memory_SRAM_ITCM_start__; const uint32 c_memory_SRAM_ITCM_size = (uint32) &__c_memory_SRAM_ITCM_size__; uint32* const c_memory_SRAM_DTCM_start = (uint32*) &__c_memory_SRAM_DTCM_start__; const uint32 c_memory_SRAM_DTCM_size = (uint32) &__c_memory_SRAM_DTCM_size__; uint32* const c_memory_SRAM_AXI_start = (uint32*) &__c_memory_SRAM_AXI_start__; const uint32 c_memory_SRAM_AXI_size = (uint32) &__c_memory_SRAM_AXI_size__; uint32* const c_memory_SRAM_1_start = (uint32*) &__c_memory_SRAM_1_start__; const uint32 c_memory_SRAM_1_size = (uint32) &__c_memory_SRAM_1_size__; uint32* const c_memory_SRAM_2_start = (uint32*) &__c_memory_SRAM_2_start__; const uint32 c_memory_SRAM_2_size = (uint32) &__c_memory_SRAM_2_size__; uint32* const c_memory_SRAM_3_start = (uint32*) &__c_memory_SRAM_3_start__; const uint32 c_memory_SRAM_3_size = (uint32) &__c_memory_SRAM_3_size__; uint32* const c_memory_SRAM_4_start = (uint32*) &__c_memory_SRAM_4_start__; const uint32 c_memory_SRAM_4_size = (uint32) &__c_memory_SRAM_4_size__; const uint32* const c_code_isr_flash_start = (uint32*) &__c_code_isr_flash_start__; const uint32 c_code_isr_flash_size = (uint32) &__c_code_isr_flash_size__; uint32* const c_code_isr_ram_start = (uint32*) &__c_code_isr_ram_start__; const uint32* const c_code_sram_flash_start = (uint32*) &__c_code_sram_flash_start__; const uint32 c_code_sram_flash_size = (uint32) &__c_code_sram_flash_size__; uint32* const c_code_sram_ram_start = (uint32*) &__c_code_sram_ram_start__; const uint32* const c_data_sram_flash_start = (uint32*) &__c_data_sram_flash_start__; const uint32 c_data_sram_flash_size = (uint32) &__c_data_sram_flash_size__; uint32* const c_data_sram_ram_start = (uint32*) &__c_data_sram_ram_start__; const uint32* const c_data_user_flash_start = (uint32*) &__c_data_user_flash_start__; const uint32 c_data_user_flash_size = (uint32) &__c_data_user_flash_size__; uint32* const c_data_user_ram_start = (uint32*) &__c_data_user_ram_start__; STM32H753BIT6::zeroOutRAM(c_memory_SRAM_ITCM_start, c_memory_SRAM_ITCM_size); // SRAM ITCM STM32H753BIT6::zeroOutRAM(c_memory_SRAM_DTCM_start, c_memory_SRAM_DTCM_size); // SRAM DTCM STM32H753BIT6::zeroOutRAM(c_memory_SRAM_AXI_start, c_memory_SRAM_AXI_size); // SRAM AXI STM32H753BIT6::zeroOutRAM(c_memory_SRAM_4_start, c_memory_SRAM_4_size); // SRAM 4 STM32H753BIT6::copy_flashToRAM(c_code_isr_flash_start, c_code_isr_ram_start, c_code_isr_flash_size); STM32H753BIT6::copy_flashToRAM(c_code_sram_flash_start, c_code_sram_ram_start, c_code_sram_flash_size); STM32H753BIT6::copy_flashToRAM(c_data_sram_flash_start, c_data_sram_ram_start, c_data_sram_flash_size); sbi(RCC_AHB2_ENR, 29); // Enable SRAM 1 Clock in RCC sbi(RCC_AHB2_ENR, 30); // Enable SRAM 2 Clock in RCC sbi(RCC_AHB2_ENR, 31); // Enable SRAM 3 Clock in RCC sbi(RCC_AHB4_ENR, 28); // Enable BackupSRAM Clock in RCC STM32H753BIT6::zeroOutRAM(c_memory_SRAM_1_start, c_memory_SRAM_1_size); // SRAM 1 STM32H753BIT6::zeroOutRAM(c_memory_SRAM_2_start, c_memory_SRAM_2_size); // SRAM 2 STM32H753BIT6::zeroOutRAM(c_memory_SRAM_3_start, c_memory_SRAM_3_size); // SRAM 3 STM32H753BIT6::copy_flashToRAM(c_data_user_flash_start, c_data_user_ram_start, c_data_user_flash_size); System& system = System::get(); system.run(); system.reset(); } extern "C" { CODE_ISR void __dummyInterruptHandler__() { while(1) { } } } CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_WWDG(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_PVD_PVM(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_RTC_TAMPER_CSSLSE(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_RTC_WAKEUP(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_FLASH(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_RCC(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_EXTI_0(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_EXTI_1(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_EXTI_2(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_EXTI_3(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_EXTI_4(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DMA_1_CH0(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DMA_1_CH1(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DMA_1_CH2(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DMA_1_CH3(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DMA_1_CH4(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DMA_1_CH5(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DMA_1_CH6(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_ADC_1_2(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_FDCAN_1_INT0(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_FDCAN_2_INT0(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_FDCAN_1_INT1(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_FDCAN_2_INT1(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_EXTI_9_TO_5(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_TIMER_1_BREAK(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_TIMER_1_UPDATE(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_TIMER_1_TRIGGER_COMMUTATION(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_TIMER_1_CAPTURE_COMPARE(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_TIMER_2(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_TIMER_3(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_TIMER_4(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_I2C_1_EVENT(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_I2C_1_ERROR(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_I2C_2_EVENT(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_I2C_2_ERROR(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_SPI_1(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_SPI_2(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_USART_1(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_USART_2(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_USART_3(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_EXTI_15_TO_10(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_RTC_ALARM_EXTI(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_TIMER_8_BREAK_AND_TIMER_12(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_TIMER_8_UPDATE_AND_TIMER_13(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_TIMER_8_TRIGGER_COMMUTATION_AND_TIMER_14(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_TIMER_8_CAPTURE_COMPARE(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DMA_1_CH7(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_FMC(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_SDMMC_1(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_TIMER_5(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_SPI_3(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_UART_4(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_UART_5(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_TIMER_6_AND_DAC(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_TIMER_7(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DMA_2_CH0(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DMA_2_CH1(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DMA_2_CH2(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DMA_2_CH3(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DMA_2_CH4(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_ETHERNET(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_ETHERNET_WAKEUP(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_FDCAN_CALIBRATION(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_ARM_CORTEX_M7_SEND_EVEN(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DMA_2_CH5(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DMA_2_CH6(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DMA_2_CH7(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_USART_6(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_I2C_3_EVENT(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_I2C_3_ERROR(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_USB_HS_EP1_OUT(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_USB_HS_EP1_IN(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_USB_HS_WAKEUP(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_USB_HS(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DCMI(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_CRYPTO(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_HASH_RNG(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_FPU(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_UART_7(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_UART_8(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_SPI_4(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_SPI_5(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_SPI_6(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_SAI_1(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_LTDC(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_LTDC_ERROR(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DMA2D(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_SAI_2(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_QUADSPI(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_LP_TIMER_1(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_HDMI_CEC(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_I2C_4_EVENT(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_I2C_4_ERROR(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_SPDIF(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_USB_FS_EP1_OUT(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_USB_FS_EP1_IN(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_USB_FS_WAKEUP(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_USB_FS(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DMAMUX_1_OVERRUN(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_HR_TIMER_MASTER(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_HR_TIMER_A(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_HR_TIMER_B(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_HR_TIMER_C(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_HR_TIMER_D(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_HR_TIMER_E(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_HR_TIMER_FAULT(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DFSDM_FILTER_0(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DFSDM_FILTER_1(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DFSDM_FILTER_2(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DFSDM_FILTER_3(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_SAI_3(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_SWPMI(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_TIMER_15(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_TIMER_16(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_TIMER_17(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_MDIOS_WAKEUP(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_MDIOS(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_JPEG(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_MDMA(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_SDMMC_2(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_HSEM(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_ADC_3(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_DMAMUX_2_OVERRUN(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_BDMA_CH0(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_BDMA_CH1(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_BDMA_CH2(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_BDMA_CH3(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_BDMA_CH4(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_BDMA_CH5(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_BDMA_CH6(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_BDMA_CH7(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_COMP_1_2(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_LP_TIMER_2(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_LP_TIMER_3(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_LP_TIMER_4(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_LP_TIMER_5(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_LP_UART(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_WWDG_RESET(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_CRS(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_RAM_ECC(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_SAI_4(); CODE_ISR WEAK ALIAS(__dummyInterruptHandler__) NOTHROW void ISR_WAKEUP_PIN_0_TO_5(); uint32 CODE_HARDWARE(__startup__)() { STM32H753BIT6& stm32h753bit6 = STM32H753BIT6::get(); if(stm32h753bit6.startup() != OK) { return(0); } return(stm32h753bit6.get_rcc().get_clock_core()); }