library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity PWM_MODULE_CLK_EN is
    generic
	(
		P                              : integer := 1666667
	);
    port
	(
		CLK_100MHZ_PIN                 : in    std_logic;    
		ARESETN_PIN                    : in    std_logic;
		CLK_EN_OUT                     : out   std_logic
    ); 
end PWM_MODULE_CLK_EN;

architecture Behavioral of PWM_MODULE_CLK_EN is

signal COUNTER                         : integer range 0 to P-1 := 0;

begin

process(CLK_100MHZ_PIN)
begin
    if CLK_100MHZ_PIN = '1' and CLK_100MHZ_PIN'event then
	    CLK_EN_OUT                     <= '0';
        if ARESETN_PIN = '0' then
			COUNTER                    <= 0;
        else
			if COUNTER = P-1 then
				COUNTER                <= 0;
				CLK_EN_OUT             <= '1';
			else
				COUNTER                <= COUNTER +1;
			end if;
        end if;
    end if;
end process;

end Behavioral;